View XRT94L33_3413775.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s e corporation 48720 kato road, fremont ca, 94538 * (510) 668-7000 * fax (510) 668-7017 * www.exar.com march 2007 rev 2.0.0 general description features the XRT94L33 is a highly integrated sonet/sdh terminator designed for e3/ds3/sts-1 mapping/de-mapping functions from either the sts-3 or stm-1 data stream. the XRT94L33 interfaces directly to the optical transceiver the XRT94L33 processes the section, line and path overhead in the sonet/sdh data stream and also performs atm and ppp phy-layer processing. the processing of path overhead bytes within the sts-1s or tug-3s includes 64 bytes for storing the j1 bytes. path overhead bytes can be accessed through the microp rocessor interface or via serial interface. the XRT94L33 uses the internal e3/ds3 de- synchronizer circuit with an internal pointer leak algorithm for clock smoothing as well as to remove the jitter due to mapping and pointer movements. these de-synchronizer circuits do not need any external clock reference for its operation. the sonet/sdh transmit blocks allow flexible insertion of toh and poh bytes through both hardware and software. individual poh bytes for the transmitted sonet/sdh signal are mapped either from the XRT94L33 memory map or from external interface. a1, a2 framing pattern, c1 byte and h1, h2 pointer byte are generated. the sonet/sdh receive blocks receive sonet sts-3 signal or sdh stm-1 signal and perform the necessary transport and path overhead processing. the XRT94L33 provides a line side aps (automatic protection switching) interface by offering redundant receive serial interface to be switched at the frame boundary. the XRT94L33 provides 3 mappers for performing sts-1/vc-3 to sts-1/ds3/e3 mapping function, one for each sts-1/ds3/e3 framers. a prbs test pattern generation and detection is implemented to measure the bit-error performance. a general-purpose microprocessor interface is included for control, configuration and monitoring. applications ? network switches ? add/drop multiplexer ? w-dcs digital cross connect systems ? provides ds3/ e3 mapping/de-mapping for up to 3 tributaries through sonet sts-1 or sdh au- 3 and/or tug-3/au-4 containers ? generates and terminates sonet/sdh section, line and path layers ? integrated serdes with clock recovery circuit ? provides sonet frame scrambling and descrambling ? integrated clock synthesi zer that generates 155 mhz and 77.76 mhz clock from an external 12.96/19.44/77.76 mhz reference clock ? integrated 3 e3/ds3/sts-1 de-synchronizer circuit that de-jitter gapped clock to meet 0.05uipp jitter requirements ? access to line or section dcc ? level 2 performance monitoring for e3 and ds3 ? supports mixing of sts-1e and ds3 or e3 and ds3 tributaries ? utopia level 2 interface for atm or level 2p for packets ? e3 and ds3 framers for both transmit and receive directions ? complete transport/section overhead processing and generation per telcordia and itu standards ? single phy and multi-phy operations supported ? full line aps support for redundancy applications ? loopback support for both sonet/sdh as well as e3/ds3/sts-1 ? boundary scan capability with jtag ieee 1149 ? 8-bit microprocessor interface ? 3.3 v 5% power supply; 5 v input signal tolerance ? -40c to +85c operating temperature range ? available in a 504 ball tbga package
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 2 block diagram of the XRT94L33 telecom bus interface oc3 txrx sonet/sdh toh sonet/sdh poh sdh mux sonet/sdh poh utopia ii/iip interface telecom bus interface telecom bus interface telecom bus interface sonet/sdh poh sonet/sdh poh boundry scan microprocessor interface to ds3/e3 sts-1 telecom bus/ t3/e3/hdlc intf to ds3/e3 sts-1 telecom bus/ t3/e3/hdlc intf to ds3/e3 sts-1 telecom bus/ t3/e3/hdlc intf to oc3 to f.o. sts-1 channel 2 ds3/e3 mapper pointer justify sts-1 tx/rx toh & poh jitter attenuator & clock smoothing ds3/e3 framer hdlc controller plcp ppp processor atm processor sts-1 channel 1 ds3/e3 mapper pointer justify sts-1 tx/rx toh & poh jitter attenuator & clock smoothing ds3/e3 framer hdlc controller plcp ppp processor atm processor sts-1 channel 0 ds3/e3 mapper pointer justify sts-1 tx/rx toh & poh jitter attenuator & clock smoothing ds3/e3 framer hdlc controller plcp ppp processor atm processor ordering information p art n umber p ackage t ype o perating t emperature r ange XRT94L33ib 27 x 27 504 lead tbga -40c to +85c
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 3 1.0 XRT94L33 registers for sonet 1.1 the overall register map within the XRT94L33 the XRT94L33 employs a direct addressing scheme. the address locations for each of the ?register groups? (or register pages) is presented in the table below. table 1: the address register map for the XRT94L33 a ddress l ocation r egister n ame d efault v alue o peration c ontrol b lock r egisters 0x0000 ? 0x00ff reserved 0x0100 operation control register ? byte 3 0x00 0x0101 operation control register ? byte 2 0x00 0x0102 reserved 0x00 0x0103 operation control register ? byte 0 0x00 0x0104 operation status register ? byte 3 (device id) 0xe3 0x0105 operation status register ? byte 2 (revision id) 0x01 0x0106 ? 0x010a reserved 0x00 0x010b operation interrupt stat us register ? byte 0 0x00 0x010c ? 0x010e reserved 0x00 0x010f operation interrupt enable register ? byte 0 0x00 0x0110 ? 0x0111 reserved 0x00 0x0112 operation block interrupt st atus register ? byte 1 0x00 0x0113 operation block interrupt st atus register ? byte 0 0x00 0x0114 ? 0x0115 reserved 0x00 0x0116 operation block interrupt enable register ? byte 1 0x00 0x0117 operation block interrupt enable register ? byte 0 0x00 0x0118 ? 0x0119 reserved 0x00 0x011a reserved 0x00 0x011b mode control register ? byte 0 0x00 0x011c ? 0x011e reserved 0x00 0x011f loop-back control register ? byte 0 0x00 0x0120 channel interrupt indicator register ? receive sonet poh processor block 0x00 0x0121 reserved 0x00 0x0122 channel interrupt indicator register ? ds3/e3 framer block 0x00 0x0123 channel interrupt indicator register ? receive sts-1 poh processor block 0x00 0x0124 channel interrupt indicator register ? receive sts-1 toh processor block 0x00
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 4 0x0125 reserved 0x00 0x0126 channel interrupt indicator register ? sts-1/ds3/e3 mapper block 0x00 0x0127 ? 0x0129 reserved 0x00 0x012a ? 0x012f reserved 0x00 0x0130 ? 0x0131 reserved 0x11 0x0132 interface control register ? byte 1 0x00 0x0133 interface control register ? byte 0 0x00 0x0134 sts-3/stm-1 telecom bus control register ? byte 3 0x00 0x0135 sts-3/stm-1 telecom bus control register ? byte 2 0x00 0x0136 reserved 0x00 0x0137 sts-3/stm-1 telecom bus control register ? byte 0 0x00 0x0138 reserved 0x00 0x0139 interface control register ? byte 2 ? sts-3 telecom bus 2 0x00 0x013a interface control register ? byte 1 ? sts-3 telecom bus 1 0x00 0x013b interface control register ? byte 0 ? sts-3 telecom bus 0 0x00 0x013c interface control register ? sts- 1 telecom bus interrupt register 0x00 0x013d interface control register ? sts-1 te lecom bus interrupt status register 0x00 0x013e interface control register ? sts-1 telecom bus interrupt register # 2 0x00 0x013f interface control register ? sts-1 te lecom bus interrupt enable register 0x00 0x0140 ? 0x0146 reserved 0x00 0x0147 operation general purpose input/output register 0x00 0x0148 ? 0x014a reserved 0x00 0x014b operation general pur pose input/output direction register ? byte 0 0x00 0x014c ?0x014f reserved 0x00 0x0150 operation output contro l register ? byte 1 0x00 0x0151 ?0x0152 reserved 0x00 0x0153 operation output contro l register ? byte 0 0x00 0x0154 operation slow speed port control register ? byte 1 0x00 0x0155 ? 0x0156 reserved 0x00 0x0157 operation slow speed port control register ?byte 0 0x00 0x0158 operation ? ds3/e3/sts-1 clock fr equency out of range detection ? direction register 0x00 0x0159 reserved 0x00 0x015a operation ? ds3/e3/sts-1 clock freque ncy ? ds3 out of range detection 0x00
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 5 threshold register 0x015b operation ? ds3/e3/sts-1 clock fr equency ? sts-1/e3 out of range detection threshold register 0x00 0x015c reserved 0x00 0x015d operation ? ds3/e3/sts-1 frequency out of range interrupt enable register ? byte 0 0x00 0x015e reserved 0x00 0x015f operation ? ds3/e3/sts-1 frequency out of range interrupt status register ? byte 0 0x00 0x0160 ? 0x017f reserved 0x00 0x0180 aps mapping register 0x00 0x0181 aps control register 0x00 0x0182 ? 0x0193 reserved 0x00 0x0194 aps status register 0x00 0x0195 reserved 0x00 0x0196 aps status register 0x00 0x0197 aps status register 0x00 0x0198 aps interrupt register 0x00 0x0199 reserved 0x00 0x019a aps interrupt register 0x00 0x019b aps interrupt register 0x00 0x019c aps interrupt register 0x00 0x019d reserved 0x00 0x019e aps interrupt enable register 0x00 0x019f aps interrupt enable register 0x00 0x01a0 ? 0x01ff reserved 0x00 l ine i nterface c ontrol r egisters 0x0302 receive line interface control register ? byte 1 0x00 0x0303 receive line interface control register ? byte 0 0x00 0x0304 ? 0x0306 reserved 0x00 0x0307 receive line status register 0x00 0x0308 -0x030a reserved 0x00 0x030b receive line interrupt register 0x00 0x030c ? 0x030e reserved 0x00 0x030f receive line interrupt enable register 0x00
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 6 0x0310 ? 0x0382 reserved 0x00 0x0383 transmit line interface control register 0x00 r eceive sts-3 toh p rocessor b lock c ontrol r egisters 0x1000 ? 0x1102 reserved 0x1103 receive sts-3 transport control register ? byte 0 0x00 0x1104 ? 0x1105 reserved 0x00 0x1106 receive sts-3 transport status register ? byte 1 0x00 0x1107 receive sts-3 transport status register ? byte 0 0x02 0x1108 reserved 0x00 0x1109 receive sts-3 transport interrupt status register ? byte 2 0x00 0x110a receive sts-3 transport interrupt status register ? byte 1 0x00 0x110b receive sts-3 transport interrupt status register ? byte 0 0x00 0x110c reserved 0x00 0x110d receive sts-3 transport interrupt enable register ? byte 2 0x00 0x110e receive sts-3 transport interrupt enable register ? byte 1 0x00 0x110f receive sts-3 transport interrupt enable register ? byte 0 0x00 0x1110 receive sts-3 transport b1 byte error count ? byte 3 0x00 0x1111 receive sts-3 transport b1 byte error count ? byte 2 0x00 0x1112 receive sts-3 transport b1 byte error count ? byte 1 0x00 0x1113 receive sts-3 transport b1 byte error count ? byte 0 0x00 0x1114 receive sts-3 transport b2 byte error count ? byte 3 0x00 0x1115 receive sts-3 transport b2 byte error count ? byte 2 0x00 0x1116 receive sts-3 transport b2 byte error count ? byte 1 0x00 0x1117 receive sts-3 transport b2 byte error count ? byte 0 0x00 0x1118 receive sts-3 transport rei-l event count ? byte 3 0x00 0x1119 receive sts-3 transport rei-l event count ? byte 2 0x00 0x111a receive sts-3 transport rei-l event count ? byte 1 0x00 0x111b receive sts-3 transport rei-l event count ? byte 0 0x00 0x111c reserved 0x00 0x111d - 0 x111e reserved 0x00 0x111f receive sts-3 transport k1 byte value register 0x00 0x1120 ? 0x1122 reserved 0x00 0x1123 receive sts-3 transport k2 byte value register 0x00
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 7 0x1124 ? 0x1126 reserved 0x00 0x1127 receive sts-3 transport s1 byte value register 0x00 0x1128 ? 0x112a reserved 0x00 0x112b receive sts-3 transport ? in-sync threshold value register 0x00 0x112c, 0x112d reserved 0x00 0x112e receive sts-3 transport ? los threshold value ? msb 0xff 0x112f receive sts-3 transport ? los threshold value ? lsb 0xff 0x1130 reserved 0x00 0x1131 receive sts-3 transport ? sf set monitor interval ? byte 2 0x00 0x1132 receive sts-3 transport ? sf set monitor interval ? byte 1 0x00 0x1133 receive sts-3 transport ? sf set monitor interval ? byte 0 0x00 0x1134 ? 0x1135 reserved 0x00 0x1136 receive sts-3 transport ? sf set threshold ? byte 1 0x00 0x1137 receive sts-3 transport ? sf set threshold ? byte 0 0x00 0x1138, 0x1139 reserved 0x00 0x113a receive sts-3 transport ? sf clear threshold ? byte 1 0x00 0x113b receive sts-3 transport ? sf clear threshold ? byte 0 0x00 0x113c reserved 0x00 0x113d receive sts-3 transport ? sd set monitor interval ? byte 2 0x00 0x113e receive sts-3 transport ? sd set monitor interval ? byte 1 0x00 0x113f receive sts-3 transport ? sd set monitor interval ? byte 0 0x00 0x1140, 0x1141 reserved 0x00 0x1142 receive sts-3 transport ? sd set threshold ? byte 1 0x00 0x1143 receive sts-3 transport ? sd set threshold ? byte 0 0x00 0x1144, 0x1145 reserved 0x00 0x1146 receive sts-3 transport ? sd clear threshold ? byte 1 0x00 0x1147 receive sts-3 transport ? sd clear threshold ? byte 0 0x00 0x1148 ? 0x114a reserved 0x00 0x114b receive sts-3 transport ? force sef condition 0x00 0x114c, 0x114e reserved 0x00 0x114f receive sts-3 transport ? receive section trace message buffer control register 0x00 0x1150, 0x1151 reserved 0x00 0x1152 receive sts-3 transport ? sd burst error count tolerance ? byte 1 0x00
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 8 0x1153 receive sts-3 transport ? sd burst error count tolerance ? byte 0 0x00 0x1154, 0x1155 reserved 0x00 0x1156 receive sts-3 transport ? sf burst error count tolerance ? byte 1 0x00 0x1157 receive sts-3 transport ? sf burst error count tolerance ? byte 0 0x00 0x1158 reserved 0x00 0x1159 receive sts-3 transport ? receive sd clear monitor interval ? byte 2 0xff 0x115a receive sts-3 transport ? receive sd clear monitor interval ? byte 1 0xff 0x115b receive sts-3 transport ? receive sd clear monitor interval ? byte 0 0xff 0x115c reserved 0x00 0x115d receive sts-3 transport ? receive sf clear monitor interval ? byte 2 0xff 0x115e receive sts-3 transport ? receive sf clear monitor interval ? byte 1 0xff 0x115f receive sts-3 transport ? receive sf clear monitor ? byte 0 0xff 0x1160 ? 0x1162 reserved 0x00 0x1163 receive sts-3 transport ? auto ais control register 0x00 0x1164 ? 0x1166 reserved 0x00 0x1167 receive sts-3 transport ? serial port control register 0x00 0x1168 ? 0x116a reserved 0x00 0x116b receive sts-3 transport ? auto ais (in downstream sts-1s) control register 0x000 0x116c ? 0x1179 reserved 0x00 0x117a receive sts-3 transport ? toh capture indirect address 0x00 0x117b receive sts-3 transport ? toh capture indirect address 0x00 0x117c receive sts-3 transport ? toh capture indirect data 0x00 0x117d receive sts-3 transport ? toh capture indirect data 0x00 0x117e receive sts-3 transport ? toh capture indirect data 0x00 0x117f receive sts-3 transport ? toh capture indirect data 0x00 0x1180 reserved 0x00 r eceive sts-3 c poh p rocessor b lock 0x1181 reserved 0x00 0x1182 receive sts-3c path ? control register ? byte 1 0x00 0x1183 receive sts-3c path ? control register ? byte 0 0x00 0x1184 ? 0x1185 reserved 0x00 0x1186 receive sts-3c path ? status register ? byte 1 0x00 0x1187 receive sts-3c path ? status register ? byte 0 0x00
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 9 0x1188 reserved 0x00 0x1189 receive sts-3c path ? interrupt status register ? byte 2 0x00 0x118a receive sts-3c path ? interrupt status register ? byte 1 0x00 0x118b receive sts-3c path ? interrupt status register ? byte 0 0x00 0x118c reserved 0x00 0x118d receive sts-3c path ? interrupt enable register ? byte 2 0x00 0x118e receive sts-3c path ? interrupt enable register ? byte 1 0x00 0x118f receive sts-3c path ? interrupt enable register ? byte 0 0x00 0x1190 ? 0x1192 reserved 0x00 0x1193 receive sts-3c path ? sonet receive rdi-p register 0x00 0x1194 ? 0x1195 reserved 0x00 0x1196 receive sts-3c path ? receive path label byte (c2) byte register 0x00 0x1197 receive sts-3c path ? expected path label byte (c2) byte register 0x00 0x1198 receive sts-3c path ? b3 byte error count register ? byte 3 0x00 0x1199 receive sts-3c path ? b3 byte error count register ? byte 2 0x00 0x119a receive sts-3c path ? b3 byte error count register ? byte 1 0x00 0x119b receive sts-3c path ? b3 byte error count register ? byte 0 0x00 0x119c receive sts-3c path ? rei-p event count register ? byte 3 0x00 0x119d receive sts-3c path ? rei-p event count register ? byte 2 0x00 0x119e receive sts-3c path ? rei-p event count register ? byte 1 0x00 0x119f receive sts-3c path ? rei-p event count register ? byte 0 0x00 0x11a0 ? 0x11a2 reserved 0x00 0x11a3 receive sts-3c path ? receive path trace message byte control register 0x00 0x11a4 ? 0x11a5 reserved 0x00 0x11a6 receive sts-3c path ? pointer value register ? byte 1 0x00 0x11a7 receive sts-3c path ? pointer value register ? byte 0 0x00 0x11a8 ? 0x11aa reserved 0x00 0x11ab receive sts-3c path ? loss of pointe r ? concatenation status register 0x00 0x11ac ? 0x11b2 reserved 0x00 0x11b3 receive sts-3c path ? ais ? c oncatenation status register 0x00 0x11b4 ? 0x11ba reserved 0x00 0x11bb receive sts-3c path ? auto ais control register 0x00 0x11bc ? 0x11be reserved 0x00
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 10 0x11bf receive sts-3c path ? serial port control register 0x00 0x11c0 ? 0x11c2 reserved 0x00 0x11c3 receive sts-3c path - receive so net auto alarm register ? byte 0 0x00 0x11c4 ?0x11d2 reserved 0x00 0x11d3 receive sts-3c path ? receive j1 byte capture register 0x00 0x11d4 ? 0x11d6 reserved 0x00 0x11d7 receive sts-3c path ? receive b3 byte capture register 0x00 0x11d8 ? 0x11da reserved 0x00 0x11db receive sts-3c path ? receive c2 byte capture register 0x00 0x11dc ? 0x11de reserved 0x00 0x11df receive sts-3c path ? receive g1 byte capture register 0x00 0x11e0 ? 0x11e2 reserved 0x00 0x11e3 receive sts-3c path ? receive f2 byte capture register 0x00 0x11e4 ? 0x11e6 reserved 0x00 0x11e7 receive sts-3c path ? receive h4 byte capture register 0x00 0x11e8 ? 0x11ea reserved 0x00 0x11eb receive sts-3c path ? receive z3 byte capture register 0x00 0x11ec ? 0x11ee reserved 0x00 0x11ef receive sts-3c path ? receive z4 (k3) byte capture register 0x00 0x11f0 ? 0x11f2 reserved 0x00 0x11f3 receive sts-3c path ? receive z5 byte capture register 0x00 0x11f4 ? 0x12ff reserved 0x00 r eceive sts-3/stm-1 toh p rocessor b lock ? r eceive j0 (s ection ) t race m essage b uffer 0x1300 ? 0x133f receive sts-3/stm-1 toh processor block ? receive j0 (section) trace message buffer ? expected and received 0x00 0x1340 ? 0x13ff reserved 0x00 r eceive sts-3 c poh p rocessor b lock ? r eceive j1 (p ath ) t race m essage b uffer ? sts-3 c 0x1500 ? 0x153f receive sts-3c poh processor block ? receive j1 (path) trace message buffer 0x00 0x1540 ? 0x15ff reserved 0x00 r edundant r eceive sts-3 toh p rocessor b lock c ontrol r egisters 0x1600 ? 0x1702 reserved 0x1703 redundant receive sts-3 transport control register ? byte 0 0x00 0x1704 ? 0x1705 reserved 0x00 0x1706 redundant receive sts-3 transport status register ? byte 1 0x00
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 11 0x1707 redundant receive sts-3 transport status register ? byte 0 0x02 0x1708 reserved 0x00 0x1709 redundant receive sts-3 transport in terrupt status register ? byte 2 0x00 0x170a redundant receive sts-3 transport in terrupt status register ? byte 1 0x00 0x170b redundant receive sts-3 transport in terrupt status register ? byte 0 0x00 0x170c reserved 0x00 0x170d redundant receive sts-3 transport in terrupt enable register ? byte 2 0x00 0x170e redundant receive sts-3 transport in terrupt enable register ? byte 1 0x00 0x170f redundant receive sts-3 transport in terrupt enable register ? byte 0 0x00 0x1710 redundant receive sts-3 transport b1 byte error count ? byte 3 0x00 0x1711 redundant receive sts-3 transport b1 byte error count ? byte 2 0x00 0x1712 redundant receive sts-3 transport b1 byte error count ? byte 1 0x00 0x1713 redundant receive sts-3 transport b1 byte error count ? byte 0 0x00 0x1714 redundant receive sts-3 transport b2 byte error count ? byte 3 0x00 0x1715 redundant receive sts-3 transport b2 byte error count ? byte 2 0x00 0x1716 redundant receive sts-3 transport b2 byte error count ? byte 1 0x00 0x1717 redundant receive sts-3 transport b2 byte error count ? byte 0 0x00 0x1718 redundant receive sts-3 transport rei-l event count ? byte 3 0x00 0x1719 redundant receive sts-3 transport rei-l event count ? byte 2 0x00 0x171a redundant receive sts-3 transport rei-l event count ? byte 1 0x00 0x171b redundant receive sts-3 transport rei-l event count ? byte 0 0x00 0x171c - 0 x171e reserved 0x00 0x171f redundant receive sts-3 transport k1 byte value register 0x00 0x1720 ? 0x1722 reserved 0x00 0x1723 redundant receive sts-3 transport k2 byte value register 0x00 0x1724 ? 0x1726 reserved 0x00 0x1727 redundant receive sts-3 transport s1 byte value register 0x00 0x1728 ? 0x172a reserved 0x00 0x172b redundant receive sts-3 transport ? in-sync threshold value 0x00 0x172c, 0x172d reserved 0x00 0x172e redundant receive sts-3 transport ? los threshold value ? msb 0xff 0x172f redundant receive sts-3 transport ? los threshold value ? lsb 0xff 0x1730 reserved 0x00
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 12 0x1731 redundant receive sts-3 transport ? sf set monitor interval ? byte 2 0x00 0x1732 redundant receive sts-3 transport ? sf set monitor interval ? byte 1 0x00 0x1733 redundant receive sts-3 transport ? sf set monitor interval ? byte 0 0x00 0x1734 ? 0x1735 reserved 0x00 0x1736 redundant receive sts-3 transport ? sf set threshold ? byte 1 0x00 0x1737 redundant receive sts-3 transport ? sf set threshold ? byte 0 0x00 0x1738, 0x1739 reserved 0x00 0x173a redundant receive sts-3 transport ? sf clear threshold ? byte 1 0x00 0x173b redundant receive sts-3 transport ? sf clear threshold ? byte 0 0x00 0x173c reserved 0x00 0x173d redundant receive sts-3 transport ? sd set monitor interval ? byte 2 0x00 0x173e redundant receive sts-3 transport ? sd set monitor interval ? byte 1 0x00 0x173f redundant receive sts-3 transport ? sd set monitor interval ? byte 0 0x00 0x1740, 0x1741 reserved 0x00 0x1742 redundant receive sts-3 transport ? sd set threshold ? byte 1 0x00 0x1743 redundant receive sts-3 transport ? sd set threshold ? byte 0 0x00 0x1744, 0x1745 reserved 0x00 0x1746 redundant receive sts-3 transport ? sd clear threshold ? byte 1 0x00 0x1747 redundant receive sts-3 transport ? sd clear threshold ? byte 0 0x00 0x1748 ? 0x174a reserved 0x00 0x174b redundant receive sts-3 transport ? force sef condition 0x00 0x174c, 0x1751 reserved 0x00 0x1752 redundant receive sts-3 transport ? sd burst error count tolerance ? byte 1 0x00 0x1753 redundant receive sts-3 transport ? sd burst error count tolerance ? byte 0 0x00 0x1754, 0x1755 reserved 0x00 0x1756 redundant receive sts-3 transport ? sf burst error count tolerance ? byte 1 0x00 0x1757 redundant receive sts-3 transport ? sf burst error count tolerance ? byte 0 0x00 0x1758 reserved 0x00 0x1759 redundant receive sts-3 transport ? receive sd clear monitor interval ? byte 2 0xff 0x175a redundant receive sts-3 transport ? receive sd clear monitor interval ? byte 1 0xff
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 13 0x175b redundant receive sts-3 transport ? receive sd clear monitor interval ? byte 0 0xff 0x175c reserved 0x00 0x175d redundant receive sts-3 transport ? receive sf clear monitor interval ? byte 2 0xff 0x175e redundant receive sts-3 transport ? receive sf clear monitor interval ? byte 1 0xff 0x175f redundant receive sts-3 transport ? receive sf clear monitor ? byte 0 0xff 0x1760 ? 0x1766 reserved 0x00 0x1767 redundant receive sts-3 transport ? serial port control register 0x00 0x1768 ? 0x1779 reserved 0x00 0x177a redundant receive sts-3 transport ? toh capture indirect address 0x00 0x177b redundant receive sts-3 transport ? toh capture indirect address 0x00 0x177c redundant receive sts-3 transport ? toh capture indirect data 0x00 0x177d redundant receive sts-3 transport ? toh capture indirect data 0x00 0x177e redundant receive sts-3 transport ? toh capture indirect data 0x00 0x177f redundant receive sts-3 transport ? toh capture indirect data 0x00 0x1780 ? 0x17ff reserved 0x00 t ransmit sts-3 toh p rocessor b lock c ontrol r egisters 0x1800 ? 0x1901 reserved 0x00 0x1902 transmit sts-3 transport ? sonet transmit control register ? byte 1 0x00 0x1903 transmit sts-3 transport ? sonet transmit control register ? byte 0 0x00 0x1904 ? 0x1916 reserved 0x00 0x1917 transmit sts-3 transport ? transmit a1 error mask ? low register ? byte 0 0x00 0x1918 ? 0x191e reserved 0x00 0x191f transmit sts-3 transport ? transmit a2 error mask ? low register ? byte 0 0x00 0x1920 ? 0x1921 reserved 0x00 0x1923 transmit sts-3 transport ? b1 byte error mask register 0x00 0x1924 ? 0x1926 reserved 0x00 0x1927 transmit sts-3 transport ? transmit b2 byte error mask register ? byte 0 0x00 0x1928 ? 0x192a reserved 0x00 0x192b transmit sts-3 transport ? transmit b2 bit error mask register ? byte 0 0x00 0x192c ? 0x192d reserved 0x00 0x192e transmit sts-3 transport ? k1k2 (aps) byte value register ? byte 1 0x00 0x192f transmit sts-3 transport ? k1k2 (aps) byte value register ? byte 0 0x00
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 14 0x1930 ? 0x1931 reserved 0x00 0x1933 transmit sts-3 transport ? rdi-l control register 0x00 0x1934 ? 0x1936 reserved 0x00 0x1937 transmit sts-3 transport ? m0m1 byte value register 0x00 0x1938 ? 0x193a reserved 0x00 0x193b transmit sts-3 transport ? s1 byte value register 0x00 0x193c ? 0x193e reserved 0x00 0x193f transmit sts-3 transport ? f1 byte value register 0x00 0x1940 ? 0x1942 reserved 0x00 0x1943 ? 0x1946 transmit sts-3 transport ? e1 byte value register 0x00 0x1947 transmit sts-3 transport ? e2 byte value register 0x00 0x1948 ? 0x194a reserved 0x00 0x194b transmit sts-3 transport ? j0 byte value register 0x00 0x194c ? 0x194e reserved 0x00 0x194f transmit sts-3 transport ? j0 byte control register 0x00 0x1950 ? 0x1952 reserved 0x00 0x1953 transmit sts-3 transport ? serial port control register 0x00 0x1954 ?0x1980 reserved 0x00 t ransmit sts-3 c poh p rocessor b lock 0x1981 reserved 0x00 0x1982 transmit sts-3c path ? sonet control register ? byte 1 0x00 0x1983 transmit sts-3c path ? sonet control register- byte 0 0x00 0x1984 ? 0x1992 reserved 0x00 0x1993 transmit sts-3c path ? transmit j1 byte value register 0x00 0x1994 ? 0x1996 reserved 0x00 0x1997 transmit sts-3c path ? b3 byte mask register 0x00 0x1998 ? 0x199a reserved 0x00 0x199b transmit sts-3c path ? transmit c2 byte value register 0x00 0x199c ? 0x199e reserved 0x00 0x199f transmit sts-3c path ? transmit g1 byte value register 0x00 0x19a0 ? 0x19a2 reserved 0x00 0x19a3 transmit sts-3c path ? transmit f2 byte value register 0x00 0x19a4 ?0x19a6 reserved 0x00
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 15 0x19a7 transmit sts-3c path ? transmit h4 byte value register 0x00 0x19a8 ? 0x19aa reserved 0x00 0x19ab transmit sts-3c path ? transmit z3 byte value register 0x00 0x19ac ? 0x19ae reserved 0x00 0x19af transmit sts-3c path ? transmit z4 byte value register 0x00 0x19b0 ? 0x19b2 reserved 0x00 0x19b3 transmit sts-3c path ? transmit z5 byte value register 0x00 0x19b4 ? 0x19b6 reserved 0x00 0x19b7 transmit sts-3c path ? transmit path control register ? byte 0 0x00 0x19b8 ? 0x19ba reserved 0x00 0x19bb transmit sts-3c path- transmit j1 byte control register 0x00 0x19bc ?0x19be reserved 0x00 0x19bf transmit sts-3c path ? transmit arbitrary h1 byte pointer register 0x00 0x19c0 ? 0x19c2 reserved 0x00 0x19c3 transmit sts-3c path ? transmit arbitrary h2 byte pointer register 0x00 0x19c4 ? 0x19c5 reserved 0x00 0x19c6 transmit sts-3c path ? transmit pointer byte register ?byte 1 0x00 0x19c7 transmit sts-3c path ? transmit po inter byte register ? byte 0 0x00 0x19c8 reserved 0x00 0x19c9 transmit sts-3c path ? rdi-p control register ? byte 2 0x00 0x19ca transmit sts-3c path ?rdi-p control register ? byte 1 0x00 0x19cb transmit sts-3c path ? rdi-p control register ? byte 0 0x00 0x19cc ?0x19ce reserved 0x00 0x19cf transmit sts-3c path ? transmit path serial port control register 0x00 0x19d0 ? 0x1aff reserved 0x00 t ransmit sts-3 toh p rocessor b lock ? t ransmit j0 (s ection ) t race m essage b uffer 0x1b00 ? 0x1b3f transmit sts-3 toh processor block ? transmit j0 (section) trace message buffer 0x00 0x1b40 ? 0x1bff reserved 0x00 t ransmit sts-3 c poh p rocessor b lock ? t ransmit j1 (p ath ) t race m essage b uffer 0x1d00 ? 0x1d3f transmit sts-3c poh processor block ?transmit j1 (path) trace message buffer 0x00 0x1d40 ? 0x1dff reserved 0x00 r eceive sonet poh p rocessor b lock c ontrol r egisters note: n represents the ?channel number? and ranges in value from 0x02 to 0x04
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 16 0xn000 ? 0xn181 reserved 0x00 0xn182 receive sonet path ? control register ? byte 1 0x00 0xn183 receive sonet path ? control register ? byte 0 0x00 0xn184, 0xn185 reserved 0x00 0xn186 receive sonet path ? status register ? byte 1 0x00 0xn187 receive sonet path ? status register ? byte 0 0x00 0xn188 reserved 0x00 0xn189 receive sonet path ? interrupt status register ? byte 2 0x00 0xn18a receive sonet path ? interrupt status register ? byte 1 0x00 0xn18b receive sonet path ? interrupt status register ? byte 0 0x00 0xn18c reserved 0x00 0xn18d receive sonet path ? interrupt enable register ? byte 2 0x00 0xn18e receive sonet path ? interrupt enable register ? byte 1 0x00 0xn18f receive sonet path ? interrupt enable register ? byte 0 0x00 0xn190 ? 0xn192 reserved 0x00 0xn193 receive sonet path ? sonet receive rdi-p register 0x00 0xn194, 0xn195 reserved 0x00 0xn196 receive sonet path ? received path label register 0x00 0xn197 receive sonet path ? expected path label register 0x00 0xn198 receive sonet path ? b3 byte error count register ? byte 3 0x00 0xn199 receive sonet path ? b3 byte error count register ? byte 2 0x00 0xn19a receive sonet path ? b3 byte error count register ? byte 1 0x00 0xn19b receive sonet path ? b3 byte error count register ? byte 0 0x00 0xn19c receive sonet path ? rei-p event count register ? byte 3 0x00 0xn19d receive sonet path ? rei-p event count register ? byte 2 0x00 0xn19e receive sonet path ? rei-p event count register ? byte 1 0x00 0xn19f receive sonet path ? rei-p event count register ? byte 0 0x00 0xn1a0 ? 0xn1a2 reserved 0x00 0xn1a3 receive sonet path ? receiver path trace message control register 0x00 0xn1a4, 0xn1a5 reserved 0xn1a6 receive sonet path ? pointer value ? byte 1 0x00 0xn1a7 receive sonet path ? pointer value ? byte 0 0x00 0xn1a8 ? 0xn1aa reserved 0x00
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 17 0xn1ab receive sonet path ? loss of pointe r ? concatenation status register 0x00 0xn1ac ? 0xn1b2 reserved 0x00 0xn1b3 receive sonet path ? ais - c oncatenation status register 0x00 0xn1b4 ? 0xn1ba reserved 0x00 0xn1bb receive sonet path ? auto ais control register 0x00 0xn1bc ? 0xn1be reserved 0x00 0xn1bf receive sonet path ? serial port control register 0x00 0xn1c0 ? 0xn1c2 reserved 0x00 0xn1c3 receive sonet path ? sonet receiv e auto alarm register ? byte 0 0x00 0xn1c4 ? 0xn1d2 reserved 0x00 0xn1d3 receive sonet path ? receive j1 byte capture register 0x00 0xn1d4 ? 0xn1d6 reserved 0x00 0xn1d7 receive sonet path ? receive b3 byte capture register 0x00 0xn1d8 ? 0xn1da reserved 0x00 0xn1db receive sonet path ? receive c2 byte capture register 0x00 0xn1dc ? 0xn1de reserved 0x00 0xn1df receive sonet path ? receive g1 byte capture register 0x00 0xn1e0 ? 0xn1e2 reserved 0x00 0xn1e3 receive sonet path ? receive f2 byte capture register 0x00 0xn1e4 ? 0xn1e6 reserved 0x00 0xn1e7 receive sonet path ? receive h4 byte capture register 0x00 0xn1e8 ? 0xn1ea reserved 0x00 0xn1eb receive sonet path ? receive z3 byte capture register 0x00 0xn1ec ? 0xn1ee reserved 0x00 0xn1ef receive sonet path ? receive z4 (k3) byte capture register 0x00 0xn1f0 ? 0xn1f2 reserved 0x00 0xn1f3 receive sonet path ? receive z5 byte capture register 0x00 0xn1f4 ? 0xn2ff reserved ds3/e3 f ramer b lock r egisters note: n represents the ?channel number? and ranges in value from 0x02 to 0x04 0xn300 operating mode register 0x23 0xn301 i/o control register 0xa0
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 18 0xn302 ? 0xn303 reserved 0x00 0xn304 block interrupt enable register 0x00 0xn305 block interrupt status register 0x00 0xn306 ? 0xn30b reserved 0x00 0xn30c test register 0x00 0xn30d payload hdlc control register 0x00 0xn30e ? 0xn30f reserved 0x00 0xn310 rxds3 configuration an d status register rxe3 configuration and st atus register # 1 ? g.832 rxe3 configuration and st atus register # 2 ? g.751 0x02 0xn311 rxds3 status register rxe3 configuration and st atus register # 2 ? g.832 rxe3 configuration and st atus register # 2 ? g.751 0x67 0xn312 rxds3 interrupt enable register rxe3 interrupt enable register # 1 ? g.832 rxe3 interrupt enable register # 1 ? g.751 0x00 0xn313 rxds3 interrupt status register rxe3 interrupt enable register # 2 ? g.832 rxe3 interrupt enable register # 2 ? g.751 0x00 0xn314 rxds3 sync detect enable register rxe3 interrupt status register # 1 ? g.832 rxe3 interrupt status register # 1 ? g.751 0x00 0xn315 rxe3 interrupt status register # 2 ? g.832 rxe3 interrupt status register # 2 ? g.751 0x00 0xn316 rxds3 feac register 0x7e 0xn317 rxds3 feac interrupt en able/status register 0x00 0xn318 rxds3 lapd control register rxe3 lapd control register 0x00 0xn319 rxds3 lapd status register rxe3 lapd status register 0x00 0xn31a rxe3 nr byte register ? g.832 rxe3 service bit register ?g.751 0x00 0xn31b rxe3 gc byte register ? g.832 0x00 0xn31c rxe3 ttb-0 register ? g.832 0x00 0xn31d rxe3 ttb-1 register ? g.832 0x00
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 19 0xn31e rxe3 ttb-2 register ? g.832 0x00 0xn31f rxe3 ttb-3 register ?g.832 0x00 0xn320 rxe3 ttb-4 register ?g.832 0x00 0xn321 rxe3 ttb-5 register ?g.832 0x00 0xn322 rxe3 ttb-6 register ? g.832 0x00 0xn323 rxe3 ttb-7 register ? g.832 0x00 0xn324 rxe3 ttb-8 register ? g.832 0x00 0xn325 rxe3 ttb-9 register ? g.832 0x00 0xn326 rxe3 ttb-10 register ? g.832 0x00 0xn327 rxe3 ttb-11 register ?g.832 0x00 0xn328 rxe3 ttb-12 register ? g.832 0x00 0xn329 rxe3 ttb-13 register ? g.832 0x00 0xn32a rxe3 ttb-14 register ? g.832 0x00 0xn32b rxe3 ttb-15 register ?g.832 0x00 0xn32c rxe3 ssm register ?g.832 0x00 0xn32d ? 0xn32e reserved 0x00 0xn32f rxds3 pattern register 0x00 0xn330 txds3 configuration register txe3 configuration register ? g.832 txe3 configuration register ? g.751 0x00 0xn331 txds3 feac configurati on and status register 0x00 0xn332 txds3 feac register 0x7e 0xn333 txds3 lapd configuration register txe3 lapd configuration register 0x08 0xn334 txds3 lapd status/interrupt register txe3 lapd status/interrupt register 0x00 0xn335 txds3 m-bit mask register txe3 gc byte register ? g.832 txe3 service bits register ? g.751 0x00 0xn336 txds3 f-bit mask # 1 register txe3 ma byte register ? g.832 0x00 0xn337 txds3 f-bit mask # 2 register txe3 nr byte register ? g.832 0x00 0xn338 txds3 f-bit mask # 3 register txe3 ttb-0 register ? g.832 0x00
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 20 0xn339 txds3 f-bit mask # 4 register txe3 ttb-1 register ? g.832 0x00 0xn33a txe3 ttb-2 register ? g.832 0x00 0xn33b txe3 ttb-3 register ? g.832 0x00 0xn33c txe3 ttb-4 register ? g.832 0x00 0xn33d txe3 ttb-5 register ? g.832 0x00 0xn33e txe3 ttb-6 register ? g.832 0x00 0xn33f txe3 ttb-7 register ? g.832 0x00 0xn340 txe3 ttb-8 register ?g.832 0x00 0xn341 txe3 ttb-9 register ? g.832 0x00 0xn342 txe3 ttb-10 register ? g.832 0x00 0xn343 txe3 ttb-11 register ? g.832 0x00 0xn344 txe3 ttb-12 register ? g.832 0x00 0xn345 txe3 ttb-13 register ? g.832 0x00 0xn346 txe3 ttb-14 register ? g.832 0x00 0xn347 txe3 ttb-15 register ?g.832 0x00 0xn348 txe3 fa1 error mask register ? g.832 txe3 fas error mask upper register ? g.751 0x00 0xn349 txe3 fa2 error mask register ? g.832 txe3 fas error mask lower register ? g.751 0x00 0xn34a txe3 bip-8 mask register ? g.832 txe3 bip-4 mask register ? g.751 0x00 0xn34b tx ssb register ? g.832 0x00 0xn34c txds3 pattern register 0x0c 0xn34d receive ds3/e3 ais/pdi-p alarm enable register 0x00 0xn34e pmon excessive zero count register - msb 0x00 0xn34f pmon excessive zero count register- lsb 0x00 0xn350 pmon lcv event count register - msb 0x00 0xn351 pmon lcv event count register - lsb 0x00 0xn352 pmon framing bit/byte error count register - msb 0x00 0xn353 pmon framing bit/byte error count register - lsb 0x00 0xn354 pmon parity error event count register - msb 0x00 0xn355 pmon parity error event count register - lsb 0x00 0xn356 pmon febe event count register- msb 0x00
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 21 0xn357 pmon febe event count register ? lsb 0x00 0xn358 pmon cp-bit error count register - msb 0x00 0xn359 pmon cp-bit error count register - lsb 0x00 0xn35a ? 0xn367 reserved 0x00 0xn368 pmon prbs bit error count register - msb 0x00 0xn369 pmon prbs bit error count register - lsb 0x00 0xn36a ? 0xn36b reserved 0x00 0xn36c pmon holding register 0x00 0xn36d one second error status register 0x00 0xn36e one second ? lcv count accumulator register - msb 0x00 0xn36f one second ? lcv count accumulator register - lsb 0x00 0xn370 one second ? parity error accumulator register - msb 0x00 0xn371 one second ? parity error accumulator register - lsb 0x00 0xn372 one second ? cp bit error accumulator register - msb 0x00 0xn373 one second ? cp bit error accumulator register - lsb 0x00 0xn374 ? 0xn37f reserved 0x00 0xn380 line interface drive register 0x00 0xn381 reserved 0x00 0xn382 reserved 0x00 0xn383 transmit lapd byte count register 0x00 0xn384 receive lapd byte count register 0x00 0xn385 ? 0xn3af reserved 0x00 0xn3b0 transmit lapd memory inaddress locationregister 0x00 0xn3b1 transmit lapd memory indirect data register 0x00 0xn3b2 receive lapd memory inaddress locationregister 0x00 0xn3b3 receive lapd memory indirect data register 0x00 0xn3b4 ? 0xn3ef reserved 0x00 0xn3f0 receive ds3/e3 configuration regist er ? secondary frame synchronizer block ? byte 1 0x10 0xn3f1 receive ds3/e3 configuration regist er ? secondary frame synchronizer block ? byte 0 0x10 0xn3f2 receive ds3/e3 ais/pdi-p alarm enable register ? secondary frame synchronizer block 0x00 0xn3f3 ? 0xn3f7 reserved 0x00 0xn3f8 receive ds3/e3 interrupt enable register ? secondary frame synchronizer 0x00
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 22 block 0xn3f9 receive ds3/e3 interrupt status regi ster ? secondary frame synchronizer block 0x00 0xn3fa ? 0xn4ff reserved 0x00 r eceive sonet poh p rocessor b lock ? r eceive j1 (p ath ) t race m essage b uffer note: n represents the ?channel number? and ranges in value from 0x02 to 0x04 0xn500 ? 0xn53f receive sonet poh processor block ? receive j1 (path) trace message buffer ? expected and received 0x00 0xn540 ? 0xn7ff reserved 0x00 t ransmit sonet poh p rocessor b lock r egisters note: n represents the ?channel number? and ranges in value from 0x02 to 0x04) 0xn800 ? 0xn981 reserved 0x00 0xn982 transmit sonet path ? sonet control register ? byte 1 0x00 0xn983 transmit sonet path ? sonet control register ? byte 0 0x00 0xn984 ? 0xn8992 reserved 0x00 0xn993 transmit sonet path ? transmitter j1 byte value register 0x00 0xn994 ? 0xn995 reserved 0x00 0xn996 transmit sonet path ? b3 byte control register 0x00 0xn997 transmit sonet path ? b3 byte mask register 0x00 0xn998 ? 0xn99a reserved 0x00 0xn99b transmit sonet path ? transmit c2 byte value register 0x00 0xn99c ? 0xn99e reserved 0x00 0xn99f transmit sonet path ? transmit g1 byte value register 0x00 0xn9a0 ? 0xn9a2 reserved 0x00 0xn9a3 transmit sonet path ? transmit f2 byte value register 0x00 0xn9a4 ? 0xn9a6 reserved 0x00 0xn9a7 transmit sonet path ? transmit h4 byte value register 0x00 0xn9a8 ? 0xn9aa reserved 0x00 0xn9ab transmit sonet path ? transmit z3 byte value register 0x00 0xn9ac ? 0xn9ae reserved 0x00 0xn9af transmit sonet path ? transmit z4 byte value register 0x00 0xn9b0 ? 0xn9b2 reserved 0x00 0xn9b3 transmit sonet path ? transmit z5 byte value register 0x00 0xn9b4 ? 0xn9b6 reserved 0x00
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 23 0xn9b7 transmit sonet path ? transmit path control register ? byte 0 0x00 0xn9b8 ? 0xn9ba reserved 0x00 0xn9bb transmit sonet path ? transmit path trace message control register 0x00 0xn9bc ? 0xn9be reserved 0x00 0xn9bf transmit sonet path ? transmit arbitrary h1 byte pointer register 0x94 0xn9c0 ? 0xn9c2 reserved 0x00 0xn9c3 transmit sonet path ? transmit arbitrary h2 byte pointer register 0x00 0xn9c4 ? 0xn9c5 reserved 0x00 0xn9c6 transmit sonet path ? transmit po inter byte register ? byte 1 0x02 0xn9c7 transmit sonet path ? transmit po inter byte register ? byte 0 0x0a 0xn9c8 reserved 0x00 0xn9c9 transmit sonet path ? rdi-p control register ? byte 2 0x40 0xn9ca transmit sonet path ? rdi-p control register ? byte 1 0xc0 0xn9cb transmit sonet path ? rdi-p control register ? byte 0 0xa0 0xn9cc ? 0xn9ce reserved 0x00 0xn9cf transmit sonet path ? transmit path serial port control register 0x00 0xn9d0 ? 0xn9ff reserved 0x00 ds3/e3 m apper b lock r egister note: n represents the ?channel number? and ranges in value from 0x02 to 0x04 0xna00 ? 0xnb00 unused 0x00 0xnb01 mapper control register ? byte 2 0x00 0xnb02 mapper control register ? byte 1 0x03 0xnb03 mapper control register ? byte 0 0x80 0xnb04, 0xnb05 unused 0x00 0xnb06 receive mapper status register ? byte 1 0x03 0xnb07 receive mapper status register ? byte 0 0x00 0xnb08 ? 0xnb0a unused 0x00 0xnb0b receive mapper interrupt status register ? byte 0 0x00 0xnb0c ? 0xnb0e unused 0x00 0xnb0f receive mapper interrupt enable register ? byte 0 0x00 0xnb10 ? 0xnb12 unused 0x00 0xnb13 t3/e3 routing register byte 0x00
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 24 0xnb14 ? 0xnb16 reserved 0x00 0xnb17 jitter attenuator ? clock smoother/routing register 0x00 0xnb18 ? 0xncff reserved 0x00 t ransmit sonet poh p rocessor b lock ? t ransmit j1 (p ath ) t race m essage b uffer note: n represents the ?channel number? and ranges in value from 0x02 to 0x04 0xnd00 ? 0xnd3f transmit sonet poh processor block ? transmit j1 (path) trace message buffer 0x00 0xnd40 ? 0xneff reserved 0x00 r eceive sts-1 toh and poh p rocessor b lock r egisters note: n represents the ?channel number? and ranges in value from 0x05 to 0x07 0xn000 ? 0xn102 reserved 0x00 0xn103 receive sts-1 transport control register ? byte 0 0x00 0xn104 ? 0xn105 reserved 0x00 0xn106 receive sts-1 transport status register ? byte 1 0x00 0xn107 receive sts-1 transport status register ? byte 0 0x02 0xn108 reserved 0x00 0xn109 receive sts-1 transport interrupt status register ? byte 2 0x00 0xn10a receive sts-1 transport interrupt status register ? byte 1 0x00 0xn10b receive sts-1 transport interrupt status register ? byte 0 0x00 0xn10c reserved 0x00 0xn10d receive sts-1 transport interrupt enable register ? byte 2 0x00 0xn10e receive sts-1 transport interrupt enable register ? byte 1 0x00 0xn10f receive sts-1 transport interrupt enable register ? byte 0 0x00 0xn110 receive sts-1 transport b1 byte error count ? byte 3 0x00 0xn111 receive sts-1 transport b1 byte error count ? byte 2 0x00 0xn112 receive sts-1 transport b1 byte error count ? byte 1 0x00 0xn113 receive sts-1 transport b1 byte error count ? byte 0 0x00 0xn114 receive sts-1 transport b2 byte error count ? byte 3 0x00 0xn115 receive sts-1 transport b2 byte error count ? byte 2 0x00 0xn116 receive sts-1 transport b2 byte error count ? byte 1 0x00 0xn117 receive sts-1 transport b2 byte error count ? byte 0 0x00 0xn118 reserved 0x00 0xn119 receive sts-1 transport rei-l event count ? byte 3 0x00 0xn11a receive sts-1 transport rei-l event count ? byte 2 0x00
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 25 0xn11b receive sts-1 transport rei-l event count ? byte 1 0x00 0xn11c receive sts-1 transport rei-l event count ? byte 0 0x00 0xn11d ? 0xn11e reserved 0x00 0xn11f receive sts-1 transport ? received k1 byte value register 0x00 0xn120 ? 0xn122 reserved 0x00 0xn123 receive sts-1 transport ? received k2 byte value register 0x00 0xn124 ? 0xn126 reserved 0x00 0xn127 receive sts-1 transport ? received s1 byte value register 0x00 0xn128 ? 0xn12d reserved 0x00 0xn12e receive sts-1 transport ? los threshold value ? msb 0xff 0xn12f receive sts-1 transport ? los threshold value ? lsb 0xff 0xn130 reserved 0x00 0xn131 receive sts-1 transport ? receive sf set monitor interval ? byte 2 0x00 0xn132 receive sts-1 transport ? receive sf set monitor interval ? byte 1 0x00 0xn133 receive sts-1 transport ? receive sf set monitor interval ? byte 0 0x00 0xn134, 0xn135 reserved 0x00 0xn136 receive sts-1 transport ? receive sf set threshold ? byte 1 0x00 0xn137 receive sts-1 transport ? receive sf set threshold ? byte 0 0x00 0xn138 ? 0xn139 reserved 0x00 0xn13a receive sts-1 transport ? receive sf clear threshold ? byte 1 0x00 0xn13b receive sts-1 transport ? receive sf clear threshold ? byte 0 0x00 0xn13c reserved 0x00 0xn13d receive sts-1 transport ? receive sd set monitor interval ? byte 2 0x00 0xn13e receive sts-1 transport ? receive sd set monitor interval ? byte 1 0x00 0xn13f receive sts-1 transport ? receive sd set monitor interval ? byte 0 0x00 0xn140 ? 0xn141 reserved 0x00 0xn142 receive sts-1 transport ? receive sd set threshold ? byte 1 0x00 0xn143 receive sts-1 transport ? receive sd set threshold ? byte 0 0x00 0xn144, 0xn145 reserved 0x00 0xn146 receive sts-1 transport ? receive sd clear threshold ? byte 1 0x00 0xn147 receive sts-1 transport ? sd clear threshold ? byte 0 0x00 0xn14b ? 0xn14a reserved 0x00 0xn14b receive sts-1 transport ? force sef condition 0x00
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 26 0xn14c ? 0xn14e reserved 0x00 0xn14f receive sts-1 transport ? receive section trace message buffer control register 0x00 0xn150 ? 0xn151 reserved 0xn152 receive sts-1 transport ? receive sd burst error count tolerance ? byte 1 0x00 0xn153 receive sts-1 transport ? receive sd burst error count tolerance ? byte 0 0x00 0xn154, 0xn155 reserved 0x00 0xn156 receive sts-1 transport ? receive sf burst error count tolerance ? byte 1 0x00 0xn157 receive sts-1 transport ? receive sf burst error count tolerance ? byte 0 0x00 0xn158 reserved 0x00 0xn159 receive sts-1 transport ? receive sd clear monitor interval ? byte 2 0x00 0xn15a receive sts-1 transport ? receive sd clear monitor interval ? byte 1 0x00 0xn15b receive sts-1 transport ? receive sd clear monitor interval ? byte 0 0x00 0xn15c reserved 0x00 0xn15d receive sts-1 transport ? receive sf clear monitor interval ? byte 2 0x00 0xn15e receive sts-1 transport ? receive sf clear monitor interval ? byte 1 0x00 0xn15f receive sts-1 transport ? receive sf clear monitor interval ? byte 0 0x00 0xn160 ? 0xn162 reserved 0x00 0xn163 receive sts-1 transport ? auto ais control register 0x00 0xn164 ? 0xn16a reserved 0x00 0xn16b receive sts-1 transport ? auto ais (in downstream sts-1s) control register 0x00 0xn16c ? 0xn182 reserved 0x00 0xn183 receive sts-1 path ? control register ? byte 2 0x00 0xn184 - 0xn185 reserved 0x00 0xn186 receive sts-1 path ? control register ? byte 1 0xn187 receive sts-1 path ? status register ? byte 0 0x00 0xn188 reserved 0x00 0xn189 receive sts-1 path ? interrupt status register ? byte 2 0x00 0xn18a receive sts-1 path ? interrupt status register ? byte 1 0x00 0xn18b receive sts-1 path ? interrupt status register ? byte 0 0x00 0xn18c reserved 0x00 0xn18d receive sts-1 path ? interrupt enable register ? byte 2 0x00 0xn18e receive sts-1 path ? interrupt enable register ? byte 1 0x00
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 27 0xn18f receive sts-1 path ? interrupt enable register ? byte 0 0x00 0xn190 ? 0xn192 reserved 0x00 0xn193 receive sts-1 path ? sonet receive rdi-p register 0x00 0xn194, 0xn195 reserved 0x00 0xn196 receive sts-1 path ? received path label value (c2 byte) register 0x00 0xn197 receive sts-1 path ? expected path label value (c2 byte) register 0x00 0xn198 receive sts-1 path ? b3 byte error count register ? byte 3 0x00 0xn199 receive sts-1 path ? b3 byte error count register ? byte 2 0x00 0xn19a receive sts-1 path ? b3 byte error count register ? byte 1 0x00 0xn19b receive sts-1 path ? b3 byte error count register ? byte 0 0x00 0xn19c receive sts-1 path ? rei-p event count register ? byte 3 0x00 0xn19d receive sts-1 path ? rei-p event count register ? byte 2 0x00 0xn19e receive sts-1 path ? rei-p event count register ? byte 1 0x00 0xn19f receive sts-1 path ? rei-p event count register ? byte 0 0x00 0xn1a0 ? 0xn1a5 reserved 0x00 0xn1a6 receive sts-1 path ? pointer value register ? byte 1 0x00 0xn1a7 receive sts-1 path ? pointer value register ? byte 0 0x00 0xn1a8 ? 0xn1ba reserved 0x00 0xn1bb receive sts-1 path ? auto ais control register 0x00 0xn1bc ? 0xn1be reserved 0x00 0xn1bf receive sts-1 path ? serial port control register 0x00 0xn1c0 ? 0xn1c2 reserved 0x00 0xn1c3 receive sts-1 path ? sonet receive auto alarm register ? byte 0 0x00 0xn1c4 ?0xn1d2 reserved 0x00 0xn1d3 receive sts-1 path ? receive j1 byte capture register 0x00 0xn1d4 ? 0xn1d6 reserved 0x00 0xn1d7 receive sts-1 path ? receive b3 byte capture register 0x00 0xn1d8 ? 0xn1da reserved 0x00 0xn1db receive sts-1 path ? receive c2 byte capture register 0x00 0xn1dc ? 0xn1de reserved 0x00 0xn1df receive sts-1 path ? receive g1 byte capture register 0x00 0xn1e0 ? 0xn1e2 reserved 0x00
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 28 0xn1e3 receive sts-1 path ? receive f2 byte capture register 0x00 0xn1e4 ? 0xn1e6 reserved 0x00 0xn1e7 receive sts-1 path ? receive h4 byte capture register 0x00 0xn1e8 ? 0xn1ea reserved 0x00 0xn1eb receive sts-1 path ? receive z3 byte capture register 0x00 0xn1ec ? 0xn1ee reserved 0x00 0xn1ef receive sts-1 path ? receive z4 (k3) byte capture register 0x00 0xn1f0 ? 0xn1f2 reserved 0x00 0xn1f3 receive sts-1 path ? receive z5 byte capture register 0x00 0xn1f4 ? 0xn1ff reserved 0x00 r eceive sts-1 toh p rocessor b lock ? r eceive j0 (s ection ) t race m essage b uffer note: n represents the ?channel number? and ranges in value from 0x05 to 0x07 0xn300 ? 0xn33f receive sts-1 poh processor block ? receive j0 (section) trace message buffer ? expected and received 0x00 0xn340 ? 0xn3ff reserved 0x00 r eceive sts-1 poh p rocessor b lock ? r eceive j1 (p ath ) t race m essage b uffer note: n represents the ?channel number? and ranges in value from 0x05 to 0x07 0xn500 ? 0xn53f receive sts-1 poh processor block ? receive j1 (path) trace message buffer ? expected and received 0x00 0xn540 ? 0xn5ff reserved 0x00 t ransmit sts-1 toh and poh p rocessor b lock r egisters note: n represents the ?channel numbers? and ranges in value from 0x05 to 0x07) 0xn800 ? 0xn901 reserved 0x00 0xn902 transmit sts-1 transport ? sonet transmit control register ? byte 1 0x00 0xn903 transmit sts-1 transport ? sonet transmit control register ? byte 0 0x00 0xn904 ? 0xn922 reserved 0x00 0xn923 transmit sts-1 transport ? b1 byte error mask register 0x00 0xn924 ? 0xn92a reserved 0x00 0xn92b transmit sts-1 transport ? transmit b2 bit error mask register ? byte 0 0x00 0xn92c ? 0xn92d reserved 0x00 0xn92e transmit sts-1 transport ? k1k2 (aps) byte value register ? byte 1 0x00 0xn92f transmit sts-1 transport ? k1k2 (aps) byte value register ? byte 0 0x00 0xn930 ? 0xn932 reserved 0x00 0xn933 transmit sts-1 transport ? rdi-l control register 0x00
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 29 0xn934 ? 0xn936 reserved 0x00 0xn937 transmit sts-1 transport ? m0m1 byte value register 0x00 0xn938 - 0xn93a reserved 0x00 0xn93b transmit sts-1 transport ? s1 byte value register 0x00 0xn93c ? 0xn93e reserved 0x00 0xn93f transmit sts-1 transport ? f1 byte value register 0x00 0xn940 ? 0xn942 reserved 0x00 0xn943 transmit sts-1 transport ? e1 byte value register 0x00 0xn944 ? 0xn946 reserved 0x00 0xn947 transmit sts-1 transport ? e2 byte value register 0x00 0xn948 ? 0xn94a reserved 0x00 0xn94b transmit sts-1 transport ? j0 byte value register 0x00 0xn94c ? 0xn94e reserved 0x00 0xn94f transmit sts-1 transport ? section trace message control register 0x00 0xn950 ? 0xn981 reserved 0x00 0xn982 transmit sts-1 path ? sonet control register ? byte 1 0x00 0xn983 transmit sts-1 path ? sonet control register ? byte 0 0x00 0xn984 ? 0xn992 reserved 0x00 0xn993 transmit sts-1 path ? transmitter j1 byte value register 0x00 0xn994 ? 0xn995 reserved 0x00 0xn996 transmit sts-1 path ? b3 byte control register 0x00 0xn997 transmit sts-1 path ? b3 byte mask register 0x00 0xn998 ? 0xn99a reserved 0x00 0xn99b transmit sts-1 path ? transmit c2 byte value register 0x00 0xn99c ? 0xn99e reserved 0x00 0xn99f transmit sts-1 path ? transmit g1 byte value register 0x00 0xn9a0 ? 0xn9a2 reserved 0x00 0xn9a3 transmit sts-1 path ? transmit f2 byte value register 0x00 0xn9a4 ? 0xn9a6 reserved 0x00 0xn9a7 transmit sts-1 path ? transmit h4 byte value register 0x00 0xn9a8 ? 0xn9aa reserved 0x00 0xn9ab transmit sts-1 path ? transmit z3 byte value register 0x00 0xn9ac ? 0xn9ae reserved 0x00
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 30 0xn9af transmit sts-1 path ? transmit z4 byte value register 0x00 0xn9b0 ? 0xn9b2 reserved 0x00 0xn9b3 transmit sts-1 path ? transmit z5 byte value register 0x00 0xn9b4 ? 0xn9b6 reserved 0x00 0xn9b7 transmit sts-1 path ? transmit path control register ? byte 0 0x00 0xn9b8 ? 0xn9ba reserved 0x00 0xn9bb transmit sts-1 path ? transmit path trace message control register 0x00 0xn9bc ? 0xn9be reserved 0x00 0xn9bf transmit sts-1 path ? transmit arbitrary h1 byte pointer register 0x94 0xn9c0 ? 0xn9c2 reserved 0x00 0xn9c3 transmit sts-1 path ? transmit arbitrary h2 byte pointer register 0x00 0xn9c4 ? 0xn9c5 reserved 0x00 0xn9c6 transmit sts-1 path ? transmit po inter byte register ? byte 1 0x02 0xn9c7 transmit sts-1 path ? transmit po inter byte register ? byte 0 0x0a 0xn9c8 reserved 0x00 0xn9c9 transmit sts-1 path ? rdi-p control register ? byte 2 0x40 0xn9c2 transmit sts-1 path ? rdi-p control register ? byte 1 0xc0 0xn9cb transmit sts-1 path ? rdi-p control register ? byte 0 0xa0 0xn9cc ? 0xn9ce reserved 0x00 0xn9cf transmit sts-1 path ? transmit path serial port control register 0x00 0xn9d0 ?0xn9ff reserved 0x00 t ransmit sts-1 toh p rocessor b lock ? t ransmit j0 (p ath ) t race m essage b uffer note: n represents the ?channel number? and ranges in value from 0x05 to 0x07 0xnb00 ? 0xnb3f transmit sts-1 poh processor block ? transmit j0 (path) trace message buffer 0x00 0xnb40 ? 0xnbff reserved 0x00 t ransmit sts-1 poh p rocessor b lock ? t ransmit j1 (p ath ) t race m essage b uffer note: n represents the ?channel number? and ranges in value from 0x05 to 0x07 0xnd00 ? 0xnd3f transmit sts-1 poh processor block ? transmit j1 (path) trace message buffer 0x00 0xnd40 ? 0xndff reserved 0x00
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 31 1.2 the operation control block the operation control block is responsible for the following functions. ? control of the interrupt structure (a t the highest level within the XRT94L33) ? control of the clock synthesizer block ? control of the sts-3/stm-1 telecom bus interface ? control of the sts-1 telecom bus interfaces the register map for the operation co ntrol block is presented in the table below. additionally, a detailed description of each of the ?operation contro l? block registers is presented below. 1.2.1 operation control block register table 2: operation control register address map a ddress l ocation r egister n ame d efault v alue 0x0000 ? 0x00ff reserved 0x00 0x0100 operation control register ? byte 3 0x00 0x0101 operation control register ? byte 2 0x00 0x0102 reserved 0x00 0x0103 operation control register ? byte 0 0x00 0x0104 operation status register ? byte 3 (device id) 0xe3 0x0105 operation status register ? byte 2 (revision id) 0x01 0x0106 ? 0x010a reserved 0x00 0x010b operation interrupt stat us register ? byte 0 0x00 0x010c ? 0x010e reserved 0x00 0x010f operation interrupt enable register ? byte 0 0x00 0x0110 ? 0x0111 reserved 0x00 0x0112 operation block interrupt st atus register ? byte 1 0x00 0x0113 operation block interrupt st atus register ? byte 0 0x00 0x0114 ? 0x0115 reserved 0x00 0x0116 operation block interrupt enable register ? byte 1 0x00 0x0117 operation block interrupt enable register ? byte 0 0x00 0x0118 ? 0x0119 reserved 0x00 0x0111a reserved 0x00 0x011b mode control register ? byte 0 0x00 0x011c ? 0x011e reserved 0x00 0x011f loop-back control register ? byte 0 0x00 0x0120 channel interrupt indicator ? receive sonet poh processor block 0x00
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 32 a ddress l ocation r egister n ame d efault v alue 0x0121 reserved 0x00 0x0122 channel interrupt indicator ? ds3/e3 framer block 0x00 0x0123 channel interrupt indicator ? receive sts-1 poh processor block 0x00 0x0124 channel interrupt indicator ? receive sts-1 toh processor block 0x00 0x0125 reserved 0x00 0x0126 channel interrupt indicator ? sts-1/ds3/e3 mapper block 0x00 0x0127 reserved 0x00 0x0128 reserved 0x00 0x0129 reserved 0x00 0x012a reserved 0x00 0x012b ? 0x012f unused 0x00 0x012e reserved 0x00 0x012f reserved 0x00 0x0130 reserved 0x00 0x0131 reserved 0x00 0x0132 interface control register ? byte 1 0x00 0x0133 interface control register ? byte 0 0x00 0x0134 sts-3/stm-1 telecom bus control register ? byte 3 0x00 0x0135 sts-3/stm-1 telecom bus control register ? byte 2 0x00 0x0136 reserved 0x00 0x0137 sts-3/stm-1 telecom bus control register ? byte 0 0x00 0x0138 reserved 0x00 0x0139 interface control register ? byte 2 ? sts-1 telecom bus 2 0x00 0x013a interface control register ? byte 1 ? sts-1 telecom bus 1 0x00 0x013b interface control register ? byte 0 ? sts-1 telecom bus 0 0x00 0x013c interface control register ? sts- 1 telecom bus interrupt register 0x00 0x013d interface control register ? sts-1 te lecom bus interrupt status register 0x00 0x013e interface control register ? sts-1 telecom bus interrupt register # 2 0x00 0x013f interface control register ? sts-1 telecom bus interrupt enable register 0x00 0x0140 ? 0x0145 reserved 0x00 0x0146 reserved 0x00 0x0147 operation general purpos e input/output register 0x00
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 33 a ddress l ocation r egister n ame d efault v alue 0x0148 ? 0x0149 reserved 0x00 0x014a reserved 0x00 0x014b operation general pu rpose input/output dir ection register 0x00 0x014c ? 0x014f reserved 0x00 0x0150 operation output contro l register ? byte 1 0x00 0x0151 ?0x0152 reserved 0x00 0x0153 operation output contro l register ? byte 0 0x00 0x0154 operation slow speed port control register ? byte 1 0x00 0x0155 ? 0x0156 reserved 0x00 0x0157 operation slow speed port control register ?byte 0 0x00 0x0158 operation ? ds3/e3/sts-1 clock frequency out of range detection ? direction register 0x00 0x0159 reserved 0x00 0x015a operation ? ds3/e3/sts-1 clock frequency ? ds3 out of range detection threshold register 0x00 0x015b operation ? ds3/e3/sts-1 clock frequency ? sts-1/e3 out of range detection threshold register 0x00 0x015c reserved 0x00 0x015d operation ? ds3/e3/sts-1 frequency out of range interrupt enable register ? byte 0 0x00 0x015e reserved 0x00 0x015f operation ? ds3/e3/sts-1 frequency out of range interrupt status register ? byte 0 0x00 0x0160 ? 0x017f reserved 0x00 0x0180 aps mapping register 0x00 0x0181 aps control register 0x00 0x0182 ? 0x0193 reserved 0x00 0x0194 aps status register 0x00 0x0195 reserved 0x00 0x0196 aps status register 0x00 0x0197 aps status register 0x00 0x0198 aps interrupt register 0x00 0x0199 reserved 0x00 0x019a aps interrupt register 0x00 0x019b aps interrupt register 0x00
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 34 a ddress l ocation r egister n ame d efault v alue 0x019c aps interrupt register 0x00 0x019d reserved 0x00 0x019e aps interrupt enable register 0x00 0x019f aps interrupt enable register 0x00 0x01a0 ? 0x01ff reserved 0x00
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 35 1.2.2 o peration c ontrol r egister d escription table 3: operation control register ? byte 3 (address location= 0x0100) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 unused configuration control r/o r/o r/o r/o r/o r/w r/w r/w 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription bit 7 ? bit 2 unused r/o please set to ?0? for normal operation. bit 1 ? bit 0 configuration control r/w configuration control: these two read/write bit-fields permits the user to specify the mode/configuration that the XRT94L33 device should operate in. please set to ?01? for mapper applications.
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 36 table 4: operation control register ? byte 2 (address location= 0x0101) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 unused interrupt write clear/rur enable interrupt clear interrupt enable r/o r/o r/o r/o r/o r/w r/w r/w 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription bit 7 ? bit 3 unused r/o please set to ?0? for normal operation. bit 2 interrupt write to clear/rur r/w interrupt ? write to clear/rur select: this read/write bit-field permits the user to configure all of the ?source- level? interrupt status bits (within the XRT94L33) to either be ?write to clear? (wtc) or ?reset-upon-read? (rur) bits. 0 ? configures all ?source-level? interrupt status register bits to function as ?reset-upon-read? (rur). 1 ? configures all ?source-level? interrupt status register bits to function as ?write-to-clear? (wtc). bit 1 enable interrupt clear r/w enable auto-clear of interrupts select: this read/write bit-field permits t he user to configure the XRT94L33 to automatically disable all inte rrupts that are activated. 0 ? configures the chip to not automatically disable any interrupts following their activation. 1 ? configures the chip to automatically disable all interrupts following their activation. bit 0 interrupt enable r/w interrupt enable: this read/write bit-field permits t he user to configure the XRT94L33 to generate interrupt requests to the microprocessor. 0 ? configures the chip to not generate interrupt to the microprocessor. all interrupts are disabled and the microproc essor must poll the register bits. 1 ? configures the chip to genera te interrupts the microprocessor.
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 37 table 5: operation control register ? byte 0 (address location= 0x0103) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 reserved sw reset r/w r/w r/o r/o r/w r/o r/o r/w 1 1 0 0 0 0 0 0 b it n umber n ame t ype d escription bits 7 - 1 unused r/o please set to ?0? for normal operation bit 0 sw reset r/w software reset ? sonet block: this read/write bit-field permits the user to command a software reset to the sonet/sdh block. if the user invokes a software reset to the sonet/sdh blocks then all of the internal state machines will be reset to their default conditions; and each of the receive sts-1/sts-3 toh processor blocks will undergo a re-frame operation. a ?0? to ?1? transition, within this bit-field commands this software reset. notes: this software reset does not reset the command registers to their default state. this can only be achieved by executing a ?hardware reset? (e.g., by pulling the reset_l* input pin ?low?). this software reset does not affect the ds3/e3 framer blocks. the software reset bit-fiel d, for the ds3/e3 framer block can be found in each of the 3 ?ds3 /e3 operating mode? registers (address location= 0xnf00).
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 38 table 6: operation status register ? byte 3 (address location= 0x0104) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 device id value r/o r/o r/o r/o r/o r/o r/o r/o 1 1 1 0 0 0 1 1 b it n umber n ame t ype d escription 7 ? 0 device id value r/o device id value: this read-only bit-field is set to the value ?0xe3? and permits the user?s software code to uniquely identify this device as being the XRT94L33. table 7: operation status register ? byte 2 (address location= 0x0105) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 revision number value r/o r/o r/o r/o r/o r/o r/o r/o 0 0 0 0 0 0 0 1 b it n umber n ame t ype d escription 7 ? 0 revision number value r/o revision numbervalue: this read-only bit-field is set to the value that corresponds to its revision number. revision a silicon will be set to the value ?0x01?. this register permits the user?s software code to uniquely identify the revision number of this device.
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 39 table 8: operation interrupt status register ? byte 0 (address location= 0x010b) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 unused tb parity error interrupt status r/o r/o r/o r/o r /o r/o r/o rur/wtc 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription bit 7 ? bit 1 unused r/o please set to ?0? for normal operation bit 0 tb parity error interrupt status rur/ wtc telecom bus parity error interrupt status: this ?reset-upon-read? bit-field indicates whether or not the ?detection of 155.52mbps telecom bus ? parity error? interrupt has occurred since the last read of this register bit. 0 ? indicates that the ?detection of 155.52mbps telecom bus ? parity error? interrupt has not occurred since the last read of this register bit. 1 ? indicates that the ?detection of 155.52mbps telecom bus ? parity error? interrupt has occurred since the last of this register bit. note: this register bit is only acti ve if the 155.52mbps port is configured to operate via the telecom bus. table 9: operation interrupt enable register ? byte 0 (address location= 0x010f) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 unused telecom bus parity error interrupt enable r/o r/o r/o r/o r/o r/o r/o r/w 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription bit 7 ? bit 1 unused r/o please set to ?0? for normal operation bit 0 tb parity error interrupt enable r/w telecom bus parity e rror interrupt enable: this ?read/write? bit-field permits the user to either enable or disable the ?detection of 155.52mbps telecom bus ? parity error? interrupt. 0 ? disables the ?detection of 155.52mbps telecom bus ? parity error? interrupt. 1 ? enables the ?detection of 155.52mbps telecom bus ? parity error? interrupt. note: this register bit is only acti ve if the 155.52mbps port is configured to operate via the telecom bus.
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 40 table 10: operation block interrupt status re gister ? byte 1 (address location= 0x0112) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 operation control block interrupt status ds3/e3 mapper block interrupt status unused receive sts-1 toh processor block interrupt status receive sts-1 poh processor block interrupt status ds3/e3 framer block interrupt status receive line interface block interrupt status unused r/o r/o r/o r/o r/o r/o r/o r/o 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 operation control block interrupt status r/o operation control block interrupt status: this read-only bit-field indicates whether or not an operation control block-related interrupt is awaiting service. 0 ? indicates that no operation cont rol block interrupts are awaiting service. 1 ? indicates that at least one ?ope ration control block? interrupt is awaiting service. 6 ds3/e3 mapper block interrupt status r/o ds3/e3 mapper block interrupt status: this read-only bit-field indicates whether or not a ds3/e3 mapper block-related interrupt is awaiting service. 0 ? indicates that no ds3/e3 mapper block interrupt is awaiting service. 1 ? indicates that at least one ?ds3/e3 mapper block? interrupt is awaiting service. 5 unused r/o 4 receive sts-1 toh processor block interrupt status r/o receive sts-1 toh processor block interrupt status: this read-only bit-field indicates whether or not an ?receive sts-1 toh processor? block interrupt is awaiting service. 0 ? indicates that no ?receive sts-1 toh processor? block interrupt is awaiting service. 1 ? indicates that at least one ?r eceive sts-1 toh processor? block interrupt is awaiting service. 3 receive sts-1 poh processor block interrupt status r/o receive sts-1 path overhead (poh) processor block interrupt status: this read-only bit-field indicates whether or not an ?receive sts-1 poh processor? block interrupt is awaiting service. 0 ? indicates that no ?receive sts-1 poh processor? block interrupt is awaiting service. 1 ? indicates that at least one ?receive sts-1 poh processor? block interrupt is awaiting service. 2 ds3/e3 framer block interrupt status r/o ds3/e3 framer block interrupt status this read-only bit-field indicates whether or not a ?ds3/e3 framer block? interrupt is awaiting service.
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 41 0 ? indicates that no ?ds3/e3 framer? block interrupt is awaiting service. 1 ? indicates that at least one ?ds3/e3 framer? block interrupt is awaiting service. 1 receive line interface block interrupt status r/o receive line interface block interrupt status this read-only bit-field indicates whether or not a ?receive line interface block? interrupt is awaiting service. 0 ? indicates that no ?receive line in terface? block interrupt is awaiting service. 1 ? indicates that at least one ?receive line interface? block interrupt is awaiting service. 0 unused r/o table 11: operation block interrupt status re gister ? byte 0 (address location= 0x0113) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 unused receive sts-3 toh processor block interrupt status receive sonet poh processor block interrupt status unused r/o r/o r/o r/o r/o r/o r/o r/o 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 unused r/o 6 receive sts-3 toh processor block interrupt status r/o receive sts-3 toh processor block interrupt status: this read-only bit-field indicates whether or not a ?receive sts-3 toh processor block? interrupt is awaiting service. 0 ? indicates that no ?receive sts-3 toh processor block? interrupt is awaiting service. 1 ? indicates that at least one ?receive sts-3 toh processor block? interrupt is awaiting service. 5 receive sonet poh processor block interrupt status r/o receive sonet poh processor block interrupt status: this read-only bit-field indicates whether or not a ?receive sonet poh processor block? interrupt is awaiting service. 0 ? indicates that no ?receive sonet poh processor block? interrupt is awaiting service. 1 ? indicates that at least one ?receive sonet poh processor block? interrupt is awaiting service. 4 - 0 unused r/o
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 42 table 12: operation block interrupt enable register ? byte 1 (address location= 0x0116) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 operation control block interrupt enable ds3/e3 mapper block interrupt enable unused receive sts-1 toh processor block interrupt enable receive sts-1 poh processor block interrupt enable ds3/e3 framer block interrupt enable receive line interface block interrupt enable unused r/w r/w r/o r/w r/w r/w r/w r/o 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 operation control block interrupt enable r/w operation control block interrupt enable: this read/write bit-field permits the user to either enable or disable the operation control block for interrupt gener ation. if the user writes a ?0? into this register bit and disables the ?oper ation control block, then all ?operation control block? interrupts will be disabled for interrupt generation. if the user writes a ?1? into this regist er bit, he/she will still need to enable the individual ?operation control block? inte rrupt(s) at the ?source level? in order to enable that particular interrupt. 0 ? disables all ?operation control blo ck? interrupts within the device. 1 ? enables the ?operation control block? at the ?block-level? for interrupt generation 6 ds3/e3 mapper block interrupt enable r/w ds3/e3 mapper block interrupt enable: this read/write bit permits the user to either enable or disable the ds3/e3 mapper block for interrupt generation. if t he user writes a ?0? into this register bit, then all ?ds3/e3 mapper block? interrupts will be disabled for interrupt generation. if the user writes a ?1? into this regist er bit, he/she will still need to enable the individual ?ds3/e3 mapper block? interrupt(s) at the ?source level? in order to enable that particular interrupt. 0 ? disables all ?ds3/e3 mapper block? interrupts within the device. 1 ? enables the ?ds3/e3 mapper block? at the ?block-level? 5 unused r/o 4 receive sts-1 toh block interrupt enable r/w receive sts-1 toh (transport overhead) processor block interrupt enable : this read/write bit permits the user to either enable or disable the receive sts-1 toh processor block for interrupt g eneration. if the user writes a ?0? to this register bit and disables the ?rec eive sts-1 toh processor block? (for interrupt generation), then all ?receive sts-1 toh processor block? interrupts will be disabled for interrupt generation. if the user writes a ?1? to this register bit, he/she will still need to enable the individual ?receive sts-1 toh processor block? interrupt(s) at the ?s ource level? in order to enable that particular interrupt. 0 ? disables all ?receive sts-1 toh processor block? interrupts within the device. 1 ? enables the ?receive sts-1 toh processor block? at the ?block-level?. note: this bit-field is inactive if the XRT94L33 has been configured to operate in the sdh mode.
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 43 3 receive sts-1 poh block interrupt enable r/w receive sts-1 poh (path overhead) processor block interrupt enable: this read/write bit permits the user to either enable or disable the receive sts-1 poh processor block for interrupt gen eration. if the user writes a ?0? to this register bit and disables the ?rec eive sts-1 poh processor block? (for interrupt generation), then all ?receive sts-1 poh processor block? interrupts will be disabled for interrupt gener ation. if the user writes a ?1? to this register bit, he/she will still need to enable the individual ?receive sts-1 poh processor block? interrupt(s) at the ?s ource level? in order to enable that particular interrupt. 0 ? disables all ?receive sts-1 poh processor block? interrupts within the device. 1 ? enables the ?receive sts-1 poh processor block? at the ?block-level?. note: this bit-field is inactive if the XRT94L33 has been configured to operate in the sdh mode. 2 ds3/e3 framer block interrupt enable r/w ds3/e3 framer block interrupt enable: this read/write bit permits the user to either enable or disable the ds3/e3 framer block for interrupt generation. if the user writes a ?0? to this register bit and disables the ?ds3/e3 framer block? (for interrupt generation), then all ?ds3/e3 framer block? interrupts will be disabled for interrupt generation. if the user writes a ?1? to this register bit, he/she will still need to enable the individual ?ds3/e3 framer block? interrupt(s) at the ?source level? in order to enable that particular interrupt. 0 ? disables all ?ds3/e3 framer block? interrupts within the device. 1 ? enables the ?ds3/e3 framer block? at the ?block-level?. 1 receive line interface block interrupt enable r/w receive line interface block interrupt enable: this read/write bit permits the user to either enable or disable the receive line interface block for interrupt generation. if the user writes a ?0? to this register bit and disables the ?receive line interface block? (for interrupt generation), then all ?receive line interface block? interrupts will be disabled for interrupt generation. if the user writes a ?1? to this register bit, he/she will still need to enable the individual ?receive line interface block? interrupt(s) at the ?source level? in order to enable that particular interrupt. 0 ? disables all ?receive line interface block? interrupts within the device. 1 ? enables the ?receive line interface block? at the ?block-level?. 0 unused r/o
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 44 table 13: operation block interrupt enable register ? byte 0 (address location= 0x0117) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 unused receive sts-3 toh block interrupt enable receive sonet poh block interrupt enable unused r/o r/w r/w r/o r/o r/o r/o r/o 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 unused r/o 6 receive sts-3 toh block interrupt enable r/w receive sts-3 toh processor block interrupt enable: this read/write bit-field permits the user to either enable or disable the ?receive sts-3 toh processor block? for interrupt generation. if the user writes a ?0? to this register bit and disables the ?receive sts-3 toh processor block? (for interrupt gener ation), then all ?receive sts-3 toh processor block? interrupts will be disa bled for interrupt g eneration. if the user writes a ?1? to this register bit, he/she will still need to enable the individual ?receive sts-3 toh processor block? interrupt(s) at the ?source level? in order to enable that particular interrupt. 0 ? disables all ?receive sts-3 toh processor block? interrupts within the device. 1 ? enables the ?receive sts-3 toh processor block? at the ?block level? for interrupt generation. 5 receive sonet poh block interrupt enable r/w receive sonet poh processor block interrupt enable: this read/write bit-field permits the user to either enable or disable the ?receive sonet poh processor bl ock? for interrupt generation. if the user writes a ?0? into this r egister bit and disables the ?receive sonet poh processor block? (for inte rrupt generation), then all ?receive sonet processor block? interrupts will be disabled for interrupt generation. if the user writes a ?1? to this register bit, then he/she will still need to enable the individual ?receive sonet poh processor block? interrupt(s) at the ?source level? in order to enable that particular interrupt. 0 ? disables all ?receive sonet poh processor block? interrupts within the device. 1 ? enables the ?receive sonet poh processor block? at the ?block level? for interrupt generation. 4 - 0 unused r/o
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 45 table 14: mode control register ? byte 0 (address location= 0x011b) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 disable jitter attenuator fast lock tbus0_is_ sdh v1_pulse_ en tbus0_ma ster reserved au-3/tug-3* mapping select r/w r/w r/w r/w r/o r/o r/o r/w 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 disfastlock r/w disable jitter attenuator fast lock: this read/write bit field is used to disable the fast lock feature for the jitter attenuator block 0 ? fast lock feature is enabled 1 ? fast lock feature is disabled note: to configure the XRT94L33 such that it will comply with the telcordia gr-253-core aps recovery time requirements of 50ms, then the ?fast lock? feaure must be enabled within the jitter attenuator block, by se tting this bit-field to ?0? 6 tbus0_is_sdh telecom bus 0 operating in sdh mode this bit is used to qualify and process a highrate sdh signal for subrate telecom bus 0 operation. 0 - clearing this bit will disable sdh format signal validation on telecom bus 0. subrate teleco m bus 0 rxd[7:0] data bus ouput will be disabled. 1 - setting this bit will enable sdh format signal validation on telecom bus 0. it enables rxd[7:0] data bus output upon recepti on of a valid sdh signal format structure. note: this bit must be enabled in sdh mode for subrate telecom bus 0 operation. this bit is ignored and does not apply in sonet mode of operation. 5 v1_pulse_en v1 pulse enable this bit provides the option of usin g an additional pulse on the telecom drop bus rxd_c1j1 output pin and telecom add bus txa_c1j1 pin to denote the location or onset of v1 by te within the synchronous payload envelope/virtual container of t he sonet/sdh frame whenever the telecom bus is processing the virtua l tributary group/virtual container multi-frame boundary 0 - telecom bus 0 in sts-3/stm-1 mode will not indicate a v1 pulse on rxd_cij1v1 output pin and txa_c1j1v1 pin to indicate vt/vc multi-frame boundary. 1 - telecom bus 0 in sts-3/stm-1 mode has v1 pulse added on rxd_cij1v1 output pin and txa_c1j1v1 pin to indicate vt/vc multi-frame boundary 4 tbus0_master select phase timing reference this bit selects txa_c1j1v1 and txa_pl phase timing reference when operating the subrate add teleco m bus 0 in rephase off mode. 0 - add telecom bus 0 timin g in slave mode. txa _ c1j1v1 and txa _ pl
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 46 pins are inputs. 1 - add telecom bus 0 timing in master mode. txa_c1j1v1 and txa_pl pins are outputs. 3 - 1 unused r/o reserved 0 au-3/tug-3* r/w au-3/tug-3 mapping select: this read/write bit-field is used to to specify how the ds3/e3 data, associated with channels 0, 1 and 2 are mapped into an sdh signal, as indicated below. 0 ? ds3/e3 channels are mapped into a vc-3, a tu-3, and then finally a tug-3 structure, when being mapped into an stm-1 signal. 1 ? ds3/e3 channels are mapped into a vc-3 and then an au-3 when being mapped into an stm-1 signal. note: this register bit is only active if the XRT94L33 has been configured to operate in the sdh mode.
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 47 table 15: loop-back control register ? byte 0 (address location= 0x011f) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 unused loop-back[3:0] r/o r/o r/o r/o r/w r/w r/w r/w 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 - 4 unused r/o 3 - 0 loop-back[3:0] r/w loop-back mode[3:0] these four read/write bits-fields permit the user to configure the XRT94L33 to operate in a variety of loop-back modes, as is tabulated below. loop-back[3:0] resulting loop-back mode 0000 normal mode (e.g., no loop-back mode) 0001 remote line loop-back: in this mode, all data th at is received by the ?receive sts-3 toh processor? block will be routed to the ?transmit sts-3 toh processor block. note: if the user invokes this loop-back, then he/she must configure the transmit sts-3/stm-1 circuitry to operate in the loop-timing mode by setting bit 6 (sts-3 loop-timing mode) within the receive line interface control register ? byte 1, to ?1? (address location: 0x0302). 0010 local transport loop-back: in this mode, all data that is being output via the ?transmit sts-3 toh processor? block will also be internally routed to the ?receive sts-3 toh processor? block. notes: 1. if the user configures the XRT94L33 device to operate in the ?local transport loop-back? mode, then, in addition to ?routing? the transmit output sts-3 data back into the ?receive path?, the transmit output sts-3 data is still output via either the transmit sts-3 pecl interface or the transmit sts-3 telecom bus interface. 2. the user must disable all ?automatic transmission of ais-p/ais indicator upon defects? features (within the chip) in order to permit this loop-back to function properly. 0011 local path loop-back: in this mode, all data that is out p ut b y the
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 48 transmit sonet poh processor block (e.g., towards the ?transmit sts-3 toh processor? block) will be internally routed to the ?receive sonet poh processor? block. notes: 1. this setting applies to all 3 transmit sonet poh processor and receive sonet poh processor blocks within the XRT94L33 device. 2. the user must disable all ?automatic transmission of ais-p/ais indicator upon defects? features (within the chip) in order to permit this loop-back to function properly. 0100 - 1111 reserved ? do not use
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 49 table 16: channel interrupt indicator ? receive sonet poh processor block (address location= 0x0120) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 unused receive sts-3c poh processor block interrupt receive au-4 mapper/ vc-3 poh block interrupt receive sonet poh block interrupt ch 2 receive sonet poh block interrupt ch 1 receive sonet poh block interrupt ch 0 r/o r/o r/o r/o r/o r/o r/o r/o 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7-5 unused 4 receive sts-3c poh block interrupt r/o receive sts-3c poh processor block interrupt: this read/only bit-field indicates whether or not the ?receive sts-3c poh processor? block is current reques ting interrupt service, as described below. 0 ? indicates that the receive st s-3c poh processor block is not declaring an interrupt. 1 ? indicates that the receive sts-3c poh processor block is currently declaring an interrupt. note: this register bit is only active if the XRT94L33 has been configured to support an sts-3c signal via channel 0. 3 receive au-4 mapper/vc-3 poh block interrupt r/o receive au-4 mapper/vc-3 poh processor block interrupt: this read/only bit-field indicates whether or not the ?receive au-4 mapper/vc-3 poh processor? block is currently requesting interrupt service, as described below. 0 ? indicates that the receive au-4 mapper/vc-3 poh processor block is not currenty declaring an interrupt. 1 ? indicates that the receive au-4 mapper/vc-3 poh processor block is currently declaring an interrupt. note: this register bit is only if the XRT94L33 device has been configured to operate in the sdh/tug-3 mapper mode. 2 receive sonet poh block interrupt channel 2 r/o receive sonet poh processor block interrupt ? channel 2: this read/only bit-field indicates whether or not the ?receive sonet poh processor? block, associated with channel 2 is declaring an interrupt, as described below. 0 ? the receive sonet poh processor block, associated with channel 2 is not currently declaring an interrupt. 1 ? the receive sonet poh processor block, associated with channel 2 is currently declaring an interrupt. 1 receive sonet poh block interrupt channel 1 r/o receive sonet poh processor block interrupt ? channel 1: this read/only bit-field indicates whether or not the ?receive sonet poh processor? block, associated with channel 1 is declaring an interrupt, as described below. 0 ? the receive sonet poh processor block, associated with channel 9
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 50 is not declaring an interrupt. 1 ? the receive sonet poh processor block, associated with channel 9 is currently declaring an interrupt. 0 receive sonet poh block interrupt channel 0 r/o receive sonet poh processor block interrupt ? channel 0: this read/only bit-field indicates whether or not the ?receive sonet poh processor? block, associated with channel 0 is declaring an interrupt, as described below. 0 ? the receive sonet poh processor block, associated with channel 0 is not declaring an interrupt. 1 ? the receive sonet poh processor block, associated with channel 0 is currently declaring an interrupt.
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 51 table 17: channel interrupt indicator ? ds3/e3 framer block (address location= 0x0122) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 unused ds3/e3 framer block interrupt ch 2 ds3/e3 framer block interrupt ch 1 ds3/e3 framer block interrupt ch 0 r/o r/o r/o r/o r/o r/o r/o r/o 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 ?3 unused r/o 2 ds3/e3 framer block interrupt ch 2 r/o ds3/e3 framer block interrupt ? channel 2: this read/only bit-field indicates whether or not the ?ds3/e3 framer? block, associated with channel 2 is declaring an interrupt, as described below. 0 ? the ds3/e3 framer block, associated with channel 2 is not currently declaring an interrupt. 1 ? the ds3/e3 framer block, associated with channel 2 is currently declaring an interrupt. note: this bit-field is only active if channel 2 has been configured to operate in the ds3/e3 mode. 1 ds3/e3 framer block interrupt ch 1 r/o ds3/e3 framer block interrupt ? channel 1: this read/only bit-field indicates whether or not the ?ds3/e3 framer? block, associated with channel 1 is declaring an interrupt, as described below. 0 ? the ds3/e3 framer block, associated with channel 1 is not declaring an interrupt. 1 ? the ds3/e3 framer block, associated with channel 1 is currently declaring an interrupt. note: this bit-field is only active if channel 1 has been configured to operate in the ds3/e3 mode. 0 ds3/e3 framer block interrupt ch 0 r/o ds3/e3 framer block interrupt ? channel 0: this read/only bit-field indicates whether or not the ?ds3/e3 framer? block, associated with channel 0 is declaring an interrupt, as described below. 0 ? the ds3/e3 framer block, associated with channel 0 is not declaring an interrupt. 1 ? the ds3/e3 framer block, associated with channel 0 is currently declaring an interrupt. note: this bit-field is only active if channel 0 has been configured to operate in the ds3/e3 mode.
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 52 table 18: channel interrupt indicator ? receive sts-1 poh processor block (address location= 0x0123) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 unused receive sts-1 poh block interrupt ch 2 receive sts- 1 poh block interrupt ch 1 receive sts-1 poh block interrupt ch 0 r/o r/o r/o r/o r/o r/o r/o r/o 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 ? 3 unused r/o 2 receive sts-1 poh block interrupt channel 2 r/o receive sts-1 poh processor block interrupt ? channel 2: this read/only bit-field indicates whether or not the ?receive sts-1 poh processor? block, associated with channel 2 is declaring an interrupt, as described below. 0 ? the receive sts-1 poh processor block, associated with channel 2 is not declaring an interrupt. 1 ? the receive sts-1 poh processor block, associated with channel 2 is currently declaring an interrupt. note: this bit-field is only active if channel 2 has been configured to operate in the sts-1 mode. 1 receive sts-1 poh block interrupt channel 1 r/o receive sts-1 poh processor block interrupt ? channel 1: this read/only bit-field indicates whether or not the ?receive sts-1 poh processor? block, associated with channel 1 is declaring an interrupt, as described below. 0 ? the receive sts-1 poh processor block, associated with channel 1 is not declaring an interrupt. 1 ? the receive sts-1 poh processor block, associated with channel 1 is currently declaring an interrupt. note: this bit-field is only active if channel 1 has been configured to operate in the sts-1 mode. 0 receive sts-1 poh block interrupt channel 0 r/o receive sts-1 poh processor block interrupt ? channel 0: this read/only bit-field indicates whether or not the ?receive sts-1 poh processor? block, associated with channel 0 is declaring an interrupt, as described below. 0 ? the receive sts-1 poh processor block, associated with channel 0 is not declaring an interrupt. 1 ? the receive sts-1 poh processor block, associated with channel 0 is currently declaring an interrupt. note: this bit-field is only active if channel 0 has been configured to operate in the sts-1 mode.
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 53 table 19: channel interrupt indicator ? receive sts-1 toh processor block (address location= 0x0124) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 unused receive sts-1 toh block interrupt ch 2 receive sts-1 toh block interrupt ch 1 receive sts-1 toh block interrupt ch 0 r/o r/o r/o r/o r/o r/o r/o r/o 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 ? 3 unused r/o 2 receive sts-1 toh block interrupt channel 2 r/o receive sts-1 toh processor block interrupt ? channel 2: this read/only bit-field indicates whether or not the ?receive sts-1 toh processor? block, associated with channel 2 is declaring an interrupt, as described below. 0 ? the receive sts-1 toh processor block, associated with channel 2 is not declaring an interrupt. 1 ? the receive sts-1 toh processor block, associated with channel 2 is currently declaring an interrupt. note: this bit-field is only active if channel 2 has been configured to operate in the sts-1 mode. 1 receive sts-1 toh block interrupt channel 1 r/o receive sts-1 toh processor block interrupt ? channel 1: this read/only bit-field indicates whether or not the ?receive sts-1 toh processor? block, associated with channel 1 is declaring an interrupt, as described below. 0 ? the receive sts-1 toh processor block, associated with channel 1 is not declaring an interrupt. 1 ? the receive sts-1 toh processor block, associated with channel 1 is currently declaring an interrupt. note: this bit-field is only active if channel 1 has been configured to operate in the sts-1 mode. 0 receive sts-1 toh block interrupt channel 0 r/o receive sts-1 toh processor block interrupt ? channel 0: this read/only bit-field indicates whether or not the ?receive sts-1 toh processor? block, associated with channel 0 is declaring an interrupt, as described below. 0 ? the receive sts-1 toh processor block, associated with channel 0 is not declaring an interrupt. 1 ? the receive sts-1 toh processor block, associated with channel 0 is currently declaring an interrupt. note: this bit-field is only active if channel 0 has been configured to operate in the sts-1 mode.
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 54 table 20: channel interrupt indicator ?ds3/e3 mapper block (address location= 0x0126) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 unused ds3/e3 mapper block interrupt ch 2 ds3/e3 mapper block interrupt ch 1 ds3/e3 mapper block interrupt ch 0 r/o r/o r/o r/o r/o r/o r/o r/o 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 ? 3 unused r/o 2 ds3/e3 mapper block interrupt channel 2 r/o ds3/e3 mapper block interrupt ? channel 2: this read/only bit-field indicates whether or not the ?ds3/e3 mapper? block, associated with channel 2 is declaring an interrupt, as described below. 0 ? the ds3/e3 mapper block, associat ed with channel 2 is not declaring an interrupt. 1 ? the ds3/e3 mapper block, associated with channel 2 is currently declaring an interrupt. note: this bit-field is only active if channel 2 has been configured to operate in the ds3/e3 mode. 1 ds3/e3 mapper block interrupt channel 1 r/o ds3/e3 mapper block interrupt ? channel 1: this read/only bit-field indicates whether or not the ?ds3/e3 mapper? block, associated with channel 1 is declaring an interrupt, as described below. 0 ? the ds3/e3 mapper block, associat ed with channel 1 is not declaring an interrupt. 1 ? the ds3/e3 mapper block, associated with channel 1 is currently declaring an interrupt. note: this bit-field is only active if channel 1 has been configured to operate in the ds3/e3 mode. 0 ds3/e3 mapper block interrupt channel 0 r/o ds3/e3 mapper block interrupt ? channel 0: this read/only bit-field indicates whether or not the ?ds3/e3 mapper? block, associated with channel 0 is declaring an interrupt, as described below. 0 ? the ds3/e3 mapper block, associat ed with channel 0 is not declaring an interrupt. 1 ? the ds3/e3 mapper block, associated with channel 0 is currently declaring an interrupt. note: this bit-field is only active if channel 0 has been configured to operate in the ds3/e3 mode.
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 55 table 21: interface control register ? byte 1 (address location= 0x0132) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 unused receive sts-3/stm-1 line select[1:0] unused transmit sts-3/stm-1 line select[1:0] r/o r/o r/w r/w r/o r/o r/w r/w 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 ? 6 unused r/o 5 ? 4 receive sts- 3/stm-1 line select[1:0] r/w receive sts-3/stm-1 line select[1:0]: these two read/write bit-fields permit the user to configure the receive sts-3 toh processor block to either accept its sts-3/stm-1 data from the receive sts-3/stm-1 te lecom bus interface, or from the receive sts-3/stm-1 pecl interface. 0, 0 ? configures the receive sts-3 toh processor block to accept the incoming sts-3/stm-1 data via the receive sts-3/stm-1 pecl interface block 0, 1 ? configures the receive sts-3 toh processor block to accept the incoming sts-3/stm-1 data via the receive sts-3/stm-1 telecom bus interface block 1, 0 and 1, 1 ? do not use. 3 ? 2 unused r/o 1 ? 0 transmit sts- 3/stm-1 line select[1:0] r/w transmit sts-3/stm-1 line select[1:0]: these two read/write bit-fields permit the user to configure the transmit sts-3 toh processor block to output its outbound sts-3/stm- 1 data to either the transmit sts-3/stm-1 telecom bus interface, or to the transmit sts-3/stm-1 pecl interface. 0, 0 ? configures the transmit sts-3 toh processor block to output the outbound sts-3/stm-1 data via the transmit sts-3/stm-1 pecl interface block 0, 1 ? configures the transmit sts-3 toh processor block to output the outbound sts-3/stm-1 data via the transmit sts-3/stm-1 telecom bus interface block 1, 0 and 1, 1 ? do not use.
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 56 table 22: interface control register ? byte 0 (address location= 0x0133) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 sbsync_delay[7:0] r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 ? 0 sbsync_delay[7:0] r/w sts-1 telecom bus ? sync delay: the transmit sts-1 telecom bus is aligned to the ?txsbfp_in? input pin. the user is expected to apply a pulse (with the period of a 6.48mhz clock signal) at a rate of 8khz to the ?tx sbfp_in input (pin number g4). each transmit sts-1 telecom bus will align its transmission of the very first byte of a new sts-1 frame, with a pulse at this input pin. these read/write bit-fields permit the user to specify the amount of delay (in terms of 6.48mhz clock periods) that will exist between the rising edge of ?txsbfp_in? and the transmission of the very first byte, within a given sts-1 via the transmit sts-1 telecom bus. setting this register to ?0x00? c onfigures each of the transmit sts-1 telecom bus interfaces to transmit th e very first byte of a new sts-1 frame, upon detection of the rising edge of the ?txsbfp_in?. setting this register to ?0x01? c onfigures each of the transmit sts-1 telecom bus interfaces to delay its transmission of the very first byte of a new sts-1 frame, by one 6.48mhz clock period, and so on. note: this register is only active if at least one of the three sts-1 telecom bus interfaces are enabled.
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 57 table 23: sts-3/stm-1 telecom bus control register ? byte 3 (address location= 0x0134) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 hrsync_delay[15:8] r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 ? 0 hrsync_delay[15:8] r/w sts-3 telecom bus ? sync delay ? upper byte: the transmit sts-3 toh processor block will generate the outbound sts-3/stm-1 frames in alignment wi th the 8khz pulse that is being applied to the ?txsbfp_in? input pin. the user is expected to apply a pu lse (with the period of a 19.44mhz clock signal) at a rate of 8khz to the ?txsbfp_in input (pin number g4). the transmit sts-3/stm-1 telecom bus will align its transmission of the very first byte of a new sts-3/stm-1 frame, with a pulse at this input pin. these read/write bit-fields permit the user to specify the amount of delay (in terms of 19.44mhz clock periods) that will exist between the rising edge of ?txsbfp_in? and the transmission of the very first byte, within a given sts-3 via the transmit sts-3/stm-1 telecom bus. setting these two registers to ?0x0000? configures each of the transmit sts-3/stm-1 telecom bus interfaces to transmit the very first byte of a new sts-3 frame, upon detection of the rising edge of the ?txsbfp_in?. setting these register to ?0x0001? co nfigures each of the transmit sts- 3 telecom bus interfaces to delay its transmission of the very first byte of a new sts-3 frame, by one 19. 44mhz clock period, and so on. note: this register is also active if the user has configured the XRT94L33 device to transmit its outbound sts-3/stm-1 data via the transmit sts-3/stm-1 pecl interface block. as a consequence, the user can configure the XRT94L33 device to align its transmission of sts-3/stm-1 frames (via the transmit sts-3/stm-1 pecl interface) to the 8khz signal that is being applied to the ?txsbfp_in? input pin.
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 58 table 24: sts-3/stm-1 telecom bus control register ? byte 2 (address location= 0x0135) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 hrsync_delay[7:0] r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 ? 0 hrsync_delay[7:0] r/w sts-3 telecom bus ? sync delay ? lower byte: the transmit sts-3 toh processor block will generate the outbound sts-3/stm-1 frame in alignment with the 8khz pulse that is being applied to the ?txsbfp_in? input pin. the user is expected to apply a pu lse (with the period of a 19.44mhz clock signal) at a rate of 8khz to the ?txsbfp_in input (pin number g4). the transmit sts-3/stm-1 telecom bus will align its transmission of the very first byte of a new sts-3/stm-1 frame, with a pulse at this input pin. these read/write bit-fields (along with that within the ?interface control register ? byte 3) permit the user to specify the amount of delay (in terms of 19.44mhz clock periods) that will exist between the rising edge of ?txsbfp_in? and the transmission of the very first byte, within a given sts-3 via the transmit sts-3/stm-1 telecom bus. setting this register to ?0x0000? configures each of the transmit sts- 3/stm-1 telecom bus interfaces to transmit the very first byte of a new sts-3 frame, upon detection of the ri sing edge of the ?txsbfp_in?. setting this register to ?0x0001? configures each of the transmit sts-3 telecom bus interfaces to delay its transmission of the very first byte of a new sts-3 frame, by one 19. 44mhz clock period, and so on. note: this register is also active if the user has configured the XRT94L33 device to transmit its outbound sts-3/stm-1 data via the transmit sts-3/stm-1 pecl interface block. as a consequence, the user can configure the XRT94L33 device to align its transmission of sts-3/stm-1 frames (via the transmit sts-3/stm-1 pecl interface) to the 8khz signal that is being applied to the txsbfp_in input pin.
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 59 table 25: sts-3/stm-1 telecom bus control register ? byte 0 (address location= 0x0137) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 sts-3/stm- 1 telecom bus on telecom bus disable is sts-3 payload telecom bus parity type telecom bus j1 only telecom bus parity odd telecom bus parity disable sts-3 rephase off r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription bit 7 sts-3/stm-1 telecom bus on r/w sts-3/stm-1 telecom bus interface enable: this read/write permits the user to either enable or disable the sts- 3/stm-1 telecom bus interface, as described below. 0 ? disables the sts-3/stm-1 telecom bus interface is disabled: sts-3/stm-1 data will output via ?i nterleave/de-interleave? or ?clock/data? interface. 1 ? telecom bus interface is enabled: in this selection, the sts-3/stm-1 transmit and receive telecom bus interface will be enabled. bit 6 telecom bus tri- state r/w telecom bus tri-state: this read/write bit-field permits the user to ?tri-state? the telecom bus interface. 0 ? telecom bus interface is not tri-stated. 1 ? telecom bus interface is tri-stated. note: this read/write bit-field is ignored if the sts-3/stm-1 transmit and receive sts-3 telecom bus interface is disabled. bit 5 is sts-3 payload r/w is sts-3 payload: this read/write bit-field permits the user to configure sts-1 telecom bus interface # 0 to support the sts-3 rate, as described below. 0 ? configures all three sts-1 telecom bus interfaces to operate in the sts-1 mode. 1 ? configures sts-1 telecom bus interface # 0 to operate in the sts-3 mode. in this configuration setting, only sts-1 telecom bus interface # 0 will be active and will be operating at a rate of 19.44mhz. sts-1 telecom bus interfaces # 1 and 2 will be disabled. bit 4 telecom bus parity type r/w telecom bus parity type: this read/write bit-field permits the user to define the parameters, over which ?telecom bus? parity will be computed. 0 ? parity is computed/verified over the sts-3/stm-1 transmit and receive telecom bus ? data bus pins (e.g., txa_d[7:0] and rxd_d[7:0]). if the user implements this selection, then the following will happen. a. the sts-3/stm-1 transmit telecom bus interface will compute and output parity (via the ?txa_dp? output pin) based upon and coincident with the data being out put via the ?txa_d[7:0]? output pins.
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 60 b. the sts-3/stm-1 receive telecom bus interface will compute and verify the parity data (which is input via the ?rxd_dp? input pin) based upon the data which is being input (and latched) via the ?rxd_d[7:0]? input pins. 1 ? parity is computed/verified over the sts-3/stm-1 transmit and receive telecom bus ? data bus pins (e.g., txa_d[7:0] and rxd_d[7:0]); the c1j1 an d pl input/output pins. if the user implements this selection, then the following will happen. a. the sts-3/stm-1 transmit telecom bus interface will compute and output parity (via the ?txa_dp? output) based upon and coincident with (1) the data being output via the ?txa_d[7:0]? output pins, (2) the state of the ?txa_pl? output pin, and (3) the state of the ?txa_c 1j1? output pin. b. the sts-3/stm-1 transmit telecom bus interface will compute and verify the parity data (which is input via the ?rxd_dp? input pin) based upon (1) the data which is being input (and latched) via the ?rxd_d[7:0]? input pins, (2) the state of the ?rxd_pl? input pin, and (3) the state of the ?rxd_c1j1? input pin. note: this bit-field is disabled if the sts-3/stm-1 telecom bus is disabled. the user can configure the sts-3/stm-1 telecom bus to compute with either even or odd parity, by writing the appropriate data into bit 2 (telecom bus parity ? odd), within this register. bit 3 telecom bus j1 only r/w telecom bus ? j1 indicator only: this read/write bit-field permits the user to configure how the sts- 3/stm-1 transmit and receive telecom bus interface handles the ?txa_c1j1? and rxd_c1j1? signals, as described below. 0 ? c1 and j1 bytes this selection configures the following. c. the sts-3/stm-1 transmit telecom bus to pulse the ?txa_c1j1? output coincident to whenever the c1 and j1 bytes are being output via the ?txa_d[7:0]? output pins. d. the sts-3/stm-1 receive telecom bus will expect the ?rxd_c1j1? input to pulse ?high? coincident to whenever the c1 and j1 bytes are being sampled via the ?rxd_d[7:0]? input pins. 1 ? j1 bytes only this selection configures the following. e. the sts-3/stm-1 transmit telecom bus interface to only pulse the ?txa_c1j1? output pin coincide nt to whenever the j1 byte is being output via the ?txa_d[7:0]? output pins. note: the ?txa_c1j1? output pin will not be pulsed ?high? whenever the c1 byte is being output vi a the ?txa_d[7:0]? output pins f. the sts-3/stm-1 receive telecom bus interface will expect the ?rxd_c1j1? input to only pulse ?high? coincident to whenever the j1 byte is being sampled via the ?rxd_d[7:0]? input pins. note: the ?rxd_c1j1? input pin will not be pulsed ?high? whenever the c1 byte is being input via the ?rxd_d[7:0]? input pins bit 2 telecom bus parity odd r/w telecom bus parity ? odd parity select: this read/write bit-field permits the user to configure the sts-3/stm- 1 telecom bus interface to do the following.
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 61 i n the transmit (drop) direction the sts-3/stm-1 telecom bus to compute either the even or odd parity over the contents of the (1) txd_d[7:0] output pins, or (2) txd_d[7:0] output pins, the states of the txd_pl and txd_c1j1 output pins (depending upon user setting for bit 3). in the receive (add) direction receive sts-3/stm-1 telecom bus to compute and veri fy the even or odd parity over the conten ts of the (1) rxa_d[7:0] input pins, or (2) rxa_d[7:0] input pins, the states of the rxa_ pl and rxa_c1j1 input pins (depending upon user setting for bit 3). 0 ? configures transmit (drop) telecom bus to compute even parity and configures the receive (add) telecom bus to verify even parity. 1 ? configures transmit (drop) tele com bus to compute odd parity and configures the receive (add) telecom bus to verify odd parity. bit 1 telecom bus parity disable r/w telecom bus parity disable: this read/write bit-field permits the user to either enable or disable parity calculation and placement via t he ?txa_dp? output pin. this bit field also permits the user to enable or disable parity verification by the receive telecom bus. 0 ? enables parity calculation (on the transmit telecom bus) and disables parity verification (on the receive telecom bus. 1 ? disables parity calculation and verification bit 0 rephase off only r/w telecom bus ? rephase disable: this read/write bit-field permits the user to configure the receive sts-3/stm-1 telecom bus to intern ally compute the pointer bytes, based upon the data that it receives via the ?rxd_d[7:0] input pins. note: if the receive sts-3/stm-1 telecom bus is being provided with pulses denoting the c1 and j1 bytes (via the ?rxd_c1j1? input pin), then this feature is unnecessary. 1 ? disables rephase 0 ? enables rephase
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 62 table 26: interface control register ? byte 2 ? sts-1/stm-0 telecom bus interface ? channel 2 (address location= 0x0139) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 sts-1 telecom bus on channel 2 sts-1 telecom bus tri- state channel 2 unused sts-1 telecom bus parity type channel 2 sts-1 telecom bus j1 only sts-1 telecom bus parity odd sts-1 telecom bus parity disable sts-1 rephase off r/w r/w r/o r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription bit 7 sts-1 telecom bus on ? channel 2 r/w sts-1 telecom bus on ? channel 2: this read/write bit-field permits the us er to either enable or disable the sts-1 telecom bus interface associated with channel 2. if this particular sts-1 telecom bus interface is enabled, then all of the following events will occur. ? the transmit sts-1 telecom bus interface (associated with channel 2) will accept an sts-1 signal (in the ingress direction) and the XRT94L33 device will map this signal into an sts-3 signal. ? the XRT94L33 device will de-map out the sts-1 signal (associated with channel 2) and will output this sts- 1 data-stream via the receive sts-1 telecom bus interface (associated with channel 2). if the sts-1 telecom bus interface associated with channel 2 is disabled, then channel 2 will support the mapping (de-mapping) of ds3, e3 or sts-1 data into (from) the sts-3 signal via the ?liu interface?. 0 ? disables the sts-1 telecom bus interface associated with channel 2. in this mode, the liu interface (associated with channel 2) will now be enabled. depending upon user?s selection, the following functional blocks (within channel 2) will now be enabled. if channel 2 is configured to operate in the ds3/e3 mode: ? ds3/e3 framer block ? ds3/e3 mapper block ? ds3/e3 jitter attenuator/de-sync block if channel 2 is configured to operate in the sts-1 mode ? receive sts-1 toh processor block ? receive sts-1 poh processor block ? transmit sts-1 poh processor block ? transmit sts-1 toh processor block 1 ? enables the sts-1 telecom bus interface, associated with channel 2. in this mode, all ds3/e3 framer block and sts-1 toh/poh processor block circuitry associated with channel 2 will be disabled. bit 6 sts-1 telecom bus tri-state # 2 r/w sts-1 telecom bus tri-state ? channel 2: this read/write bit-field permits the user to ?tri-state? the telecom bus interface associated with channel 2
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 63 interface associated with channel 2. 0 ? telecom bus interface is not tri-stated. 1 ? telecom bus interface is tri-stated. note: this read/write bit-field is ignored if the transmit and receive sts-1 telecom bus interface (associated with channel 2) is disabled. bit 5 unused r/w bit 4 sts-1 telecom bus parity type ? channel 2 r/w sts-1 telecom bus parity type ? channel 2: this read/write bit-field permits the user to define the parameters, over which ?telecom bus? parity will be computed. 0 ? parity is computed/verified over the sts-1 transmit and receive telecom bus ? data bus pins (e.g., sts1txa_d_2[7:0] and sts1rxd_d_2[7:0]). if the user implements this selection, then the following will happen. g. the receive sts-1 telecom bus interface will compute and output parity (via the ?sts1rxd_dp_2? output pin) based upon and coincident with the data being output via the ?sts1rxd_2_d[7:0]? output pins. h. the transmit sts-1 telecom bus interface will compute and verify the parity data (which is input via the ?sts1txa_dp_2? input pin) based upon the data which is being input (and latched) via the ?sts1txa_2_d[7:0]? input pins. 1 ? parity is computed/verified over the transmit and receive sts-1 telecom bus ? data bus pins (e.g., sts1txa_2_d[7:0] and sts1rxd_2_d[7:0]); the sts1 txa_c1j1_2, sts1rxd_c1j1_2, sts1txa_pl_2 and sts1rxd_pl_2 input/output pins. if the user implements this selection, then the following will happen. a. the receive sts-1 telecom bus interface will compute and output parity (via the ?rxd_dp_2? output) based upon and coincident with (1) the data being output via the ?sts1rxd_2_d[7:0]? output pins, (2) the state of the ?sts1rxd_pl_2? output pin, and (3) the state of the ?sts1rxd_c1j1_2? output pin. b. the transmit sts-1 teleco m bus interface will compute and verify the parity data (which is input via the ?sts1txa_dp_2? input pin) based upon (1) the data which is being input (and latched) via the ?sts1txa_2_d[7:0]? input pins, (2) the state of the ?sts1txa_pl_2? input pin, and (3) the state of the ?sts1txa_c1j1_2? input pin. note: this bit-field is disabled if the sts-1 telecom bus is disabled. the user can configure the sts-1 telecom bus to compute with either even or odd parity, by writing the appropriate data into bit 2 (telecom bus parity ? odd) , within this register. bit 3 sts-1 telecom bus j1 only r/w sts-1 telecom bus interface ? j1 indicator only ? channel 2: this read/write bit-field permits t he user to configure how the transmit and receive sts-1 telecom bus interface handles the ?sts1txa_c1j1_2? and sts1rxd_c1j1_2? signals, as described below. 0 ? c1 and j1 bytes this selection configures the following. a. the receive sts-1 telecom bus interface to p ulse the
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 64 ?sts1rxd_c1j1_2? output coincident to whenever the c1 and j1 bytes are being output via the ?sts1rxd_2_d[7:0]? output pins. b. the transmit sts-1 telecom bus interface will expect the ?sts1txa_c1j1_2? input to be pulsed ?high? coincident to whenever the c1 and j1 bytes are being sampled via the ?sts1txa_2_d[7:0]? input pins. 1 ? j1 bytes only this selection configures the following. a. the receive sts-1 telecom bus interface to only pulse the ?sts1rxd_c1j1_2? output pin coincident to whenever the j1 byte is being output via the ?stsrx d_2_d[7:0]? output pins. note: in this setting, the ?sts1rxd_c1j1_2? output pin will not be pulsed ?high? whenever the c1 byte is being output via the ?sts1rxd_d_2[7:0]? output pins b. the transmit sts-1 telecom bus interface will expect the ?sts1txa_c1j1_2? input to only be pulsed ?high? coincident to whenever the j1 byte is being sampled via the ?sts1txa_2_d[7:0]? input pins. note: in this setting, the ?sts1txa_c1j1_2? input pin will not be pulsed ?high? whenever the c1 byte is being input via the ?sts1txa_2_d[7:0]? input pins bit 2 sts-1 telecom bus parity odd r/w sts-1 telecom bus interface parity ? odd parity select ? channel 2: this read/write bit-field permits the user to configure the sts-1 telecom bus interface, associated with channel 2 to do the following. in the receive (drop) direction receive sts-1 telecom bus interface will compute either the even or odd parity over the conten ts of the (1) sts1rxd_2_ d[7:0] output pins, or (2) sts1rxd_2_d[7:0] output pins, the states of the sts1rxd_pl_2 and sts1rxd_c1j1_2 output pins (depending upon user setting for bit 3). in the transmit (add) direction transmit sts-1 telecom bus interface will compute and verify the even or odd parity over the content s of the (1) sts1txa_2_d[ 7:0] input pins, or (2) sts1txa_2_d[7:0] input pins, the states of the sts1txa_pl_2 and sts1txa_c1j1_2 input pins (depending upon user setting for bit 3). 0 ? configures receive sts-1 (drop) telecom bus interface to compute even parity and configures the transmit sts-1 (add) telecom bus interface to verify even parity. 1 ? configures receive sts-1 (drop) telecom bus interface to compute odd parity and configures the transmi t sts-1 (add) telecom bus interface to verify odd parity. bit 1 sts-1 telecom bus parity disable r/w sts-1 telecom bus interface - parity disable ? channel 2: this read/write bit-field permits the user to either enable or disable parity calculation and placement via the ?stsrxd_dp_2? output pin. further, this bit-field also permits the user to enable or disable parity verification via the ?sts1txa_dp_2? input pin by the transmit telecom bus. 1 ? disables parity calculation (on the receive telecom bus) and disables parity verification (on the transmit telecom bus. 0 ? enables parity calculation and verification bit 0 sts-1 rephase off r/w sts-1 telecom bus interface ? rephase disable ? channel 2: this read/write bit-field p ermits the user to confi g ure the receive sts-1
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 65 off telecom bus to internally compute the pointer bytes, based upon the data that it receives via the ?rxd_d[7:0] input pins. note: if the receive sts-1 telecom bus is being provided with pulses denoting the c1 and j1 bytes (via the ?rxd_c1j1? input pin), then this feature is unnecessary. 1 ? disable rephase if the user implements this selection, then the transmit sts-1 telecom bus interface (associated with channel 2) will rely on the signaling that is provided via the ?sts1txa_c1j1_2? and ?sts1txa_pl_2? input pins, in order to determine the location of the sts-1 spe (within the ingress direction sts-1 signal) with respect to the sts-1 frame boundaries. 0 ? enable rephase if the user implements this selection, then the transmti sts-1 telecom bus interface (associated with channel 2) will not rely on the signaling that is provided via the ?sts1txa_c1j1_2? and the ?sts1txa_pl_2? input pins in order to determine t he location of the sts-1 spe (within the ingress direction sts-1 signal) with respectg to the sts-1 frame boundaries. in this case the transmit sts-1 toh and poh processor blocks (will be enabled) and will take on the role of locating the sts-1 spe within the ingress direction sts-1 signal.
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 66 table 27: interface control register ? byte 1 ? sts-1/stm-0 telecom bus interface - channel 1 (address location= 0x013a) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 sts-1 telecom bus on channel 1 sts-1 telecom bus tri- state channel 1 unused sts-1 telecom bus parity type channel 1 sts-1 telecom bus j1 only sts-1 telecom bus parity odd sts-1 telecom bus parity disable sts-1 rephase off r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription bit 7 sts-1 telecom bus on - channel 1 r/w sts-1 telecom bus on ? channel 1: this read/write bit-field permits the us er to either enable or disable the sts-1 telecom bus interface associated with channel 1. if this particular sts-1 telecom bus interface is enabled, then all of the following events will occur. ? the transmit sts-1 telecom bus interface (associated with channel 1) will accept an sts-1 signal (in the ingress direction) and the XRT94L33 device will map this signal into an sts-3 signal. ? the XRT94L33 device will de-map out the sts-1 signal (associated with channel 1) and will output this sts- 1 data-stream via the receive sts-1 telecom bus interface (associated with channel 1). if the sts-1 telecom bus interface associated with channel 1 is disabled, then channel 1 will support the mapping (de-mapping) of ds3, e3 or sts-1 data into (from) the sts-3 signal via the ?liu interface?. 0 ? disables the sts-1 telecom bus interface associated with channel 1. in this mode, the liu interface (associated with channel 1) will now be enabled. depending upon user?s selection, the following functional blocks (within channel 1) will now be enabled. if channel 1 is configured to operate in the ds3/e3 mode: ? ds3/e3 framer block ? ds3/e3 mapper block ? ds3/e3 jitter attenuator/de-sync block if channel 1 is configured to operate in the sts-1 mode: ? receive sts-1 toh processor block ? receive sts-1 poh processor block ? transmit sts-1 poh processor block ? transmit sts-1 toh processor block 1 ? enabes the sts-1 telecom bus interface, associated with channel 1. in this mode, all ds3/e3 framer block and sts-1 toh/poh processor block circuitry associated with channel 1 will be disabled.
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 67 bit 6 sts-1 telecom bus tri-state # 1 r/w sts-1 telecom bus tri-state ? channel 1: this read/write bit-field permits the user to ?tri-state? the telecom bus interface. 0 ? telecom bus interface is not tri-stated. 1 ? telecom bus interface is tri-stated. note: this read/write bit-field is ignored if the sts-1 transmit and receive telecom bus interface is disabled. bit 5 unused r/o bit 4 sts-1 telecom bus parity type # 1 r/w sts-1 telecom bus parity type ? channel 1: this read/write bit-field permits the user to define the parameters, over which ?telecom bus? parity will be computed. 0 ? parity is computed/verified over the sts-1 transmit and receive telecom bus ? data bus pins (e.g., sts1txa_d_1[7:0] and sts1rxd_d_1[7:0]). if the user implements this selection, then the following will happen. a. the sts-1 receive telecom bus interface will compute and output parity (via the ?sts1rxd_dp_1? output pin) based upon and coincident with the data being output via the ?sts1rxd_d_1[7:0]? output pins. b. the sts-1 transmit telecom bus interface will compute and verify the parity data (which is input via the ?sts1txa_dp_1? input pin) based upon the data which is being input (and latched) via the ?sts1txa_d_1[7:0]? input pins. 1 ? parity is computed/verified over the sts-1 transmit and receive telecom bus ? data bus pins (e.g., sts1txa_d_1[7:0] and sts1rxd_d_1[7:0]); the sts1 txa_c1j1_1, sts1rxd_c1j1_1, sts1txa_pl_1 and sts1rxd_pl_1 input/output pins. if the user implements this selection, then the following will happen. a. the sts-1 receive telecom bus interface will compute and output parity (via the ?sts1rxd_dp_1? output) based upon and coincident with (1) the data being output via the ?sts1rxd_d_1[7:0]? output pins, (2) the state of the ?sts1rxd_pl_1? output pin, and (3) the state of the ?sts1rxd_c1j1_1? output pin. b. the sts-1 transmit telecom bus interface will compute and verify the parity data (which is input via the ?sts1txa_dp_1? input pin) based upon (1) the data which is being input (and latched) via the ?sts1txa_d_1[7:0]? input pins, (2) the state of the ?sts1txa_pl_1? input pin, and (3) the state of the ?sts1txa_c1j1_1? input pin. note: this bit-field is disabled if the sts-1 telecom bus is disabled. the user can configure the sts-1 telecom bus to compute/verify with either even or odd parity, by writing the appropriate data into bit 2 (telecom bus parity ? odd) , within this register. bit 3 sts-1 telecom bus j1 only r/w telecom bus ? j1 indicator only ? channel 1: this read/write bit-field permits t he user to configure how the sts-1 transmit and receive telecom bus interface handles the ?sts1txa_c1j1_1? and sts1rxd_c1j1_1? signals, as described below. 0 ? c1 and j1 bytes this selection configures the following.
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 68 a. the sts-1 receive telecom bus to pulse the ?sts1rxd_c1j1_1? output coincident to whenever the c1 and j1 bytes are being output via the ?sts1rxd_d_1[7:0]? output pins. b. the sts-1 transmit telecom bus will expect the ?sts1txa_c1j1_1? input to pulse ?high? coincident to whenever the c1 and j1 bytes are being sampled via the ?sts1txa_d_1[7:0]? input pins. 1 ? j1 bytes only this selection configures the following. i. the sts-1 receive telecom bus interface to only pulse the ?sts1rxd_c1j1_1? output pin coincident to whenever the j1 byte is being output via the ?sts1r xd_d_1[7:0]? output pins. note: the ?sts1rxd_c1j1_1? output pin will not be pulsed ?high? whenever the c1 byte is being output via the ?sts1rxd_d_1[7:0]? output pins). j. the sts-1 transmit telecom bus interface will expect the ?sts1txa_c1j1_1? input to only pulse ?high? coincident to whenever the j1 byte is being sampled via the ?sts1txa_d_1[7:0]? input pins. note: the ?sts1txa_c1j1_1? input pin will not be pulsed ?high? whenever the c1 byte is being input via the ?sts1txa_d_1[7:0]? input pins). bit 2 sts-1 telecom bus parity odd r/w telecom bus parity ? odd parity select ? channel 1: this read/write bit-field permits the user to configure the sts-1 telecom bus interface, associated with channel 1 to do the following. in the receive (drop) direction receive sts-1 telecom bus to com pute either the eve n or odd parity over the contents of the (1) sts1rx d_d_1[7:0] output pins, or (2) sts1rxd_d_1[7:0] output pins, the states of the sts1rxd_pl_1 and ?sts1rxd_c1j1_1 output pins (depending upon user setting for bit 3). in the transmit (add) direction transmit sts-1 telecom bus to compute and verify the even or odd parity over the contents of the (1) sts1txa_d_1[7:0] input pins, or (2) sts1txa_d_1[7:0] input pins, the states of the sts1txa_pl_1 and sts1txa_c1j1_1 input pins (depending upon user setting for bit 3).0 ? configures receive (drop) telecom bus to compute even parity and configures the transmit (add) telecom bus to verify even parity1 ? configures receive (drop) telecom bus to compute odd parity and configures the transmit (add) telecom bus to verify odd parity. bit 1 sts-1 telecom bus parity disable r/w sts-1 telecom bus parity disable ? channel 1: this read/write bit-field permits the user to either enable or disable parity calculation and placement vi a the ?stsrxd_dp_1? output pin. further, this bit field also permits the user to enable or disable parity verification via the ?sts1txa_dp_1? input pin by the transmit telecom bus.1 ? disables parity calculation (on the receive telecom bus) and disables parity verification (on the transmit telecom bus. 0 ? enables parity calculation and verification bit 0 sts-1 rephase off r/w sts-1 telecom bus ? rephase disable ? channel 1: this read/write bit-field permits the user to configure the receive sts-1 telecom bus to internally compute the pointer bytes, based upon the data that it receives via t he ?rxd_d[7:0] input pins. if the receive sts-1 telecom bus is bein g p rovided with p ulses denotin g the c1 and j1 b y tes
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 69 (via the ?rxd_c1j1? input pin), then this feature is unnecessary. 1 ? disables rephase 0 ? enables rephase
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 70 table 28: interface control register ? byte 0 ? sts-1/stm-0 telecom bus 0 (address location= 0x013b) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 sts-1 telecom bus on # 0 sts-1 telecom bus tri- state # 0 sts-3c rephase off sts-1 telecom bus parity type # 0 sts-1 telecom bus j1 only sts-1 telecom bus parity odd sts-1 telecom bus parity disable sts-1 rephase off r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription bit 7 sts-1 telecom bus on # 0 r/w sts-1 telecom bus on ? channel 0: this read/write bit-field permits the us er to either enable or disable the telecom bus associated with sts-1 telecom bus # 0. if the sts-1 telecom bus is enabled, then an sts-1 signal will be mapped into (demapped from) the sts-3 signal. if sts-1 telecom bus interface ? channel 3 is disabled, then channel 0 will support the mapping of ds3, e3 or sts-1 into the sts-3 signal. 0 ? sts-1 telecom bus # 0 is disabled. in this mode, ds3/e3/sts-1 channel 0 will now be enabled. depending upon user?s selection, the following f unctional blocks (within channel 0) will now be enabled. if ds3/e3 framing is supported ? ds3/e3 framer block ? ds3/e3 mapper block ? ds3/e3 jitter attenuator/de-sync block if sts-1 framing is supported ? receive sts-1 toh processor block ? receive sts-1 poh processor block ? transmit sts-1 poh processor block ? transmit sts-1 toh processor block 1 ? sts-1 telecom bus # 0 is enabled. in this mode, all ds3/e3 framer bl ock and sts-1 circuitry associated with channel 0 will be disabled. bit 6 sts-1 telecom bus tri-state # 0 r/w sts-1 telecom bus tri-state ? channel 0: this read/write bit-field permits the user to ?tri-state? the telecom bus interface. 0 ? telecom bus interface is not tri-stated. 1 ? telecom bus interface is tri-stated. note: this read/write bit-field is ignored if the sts-1 transmit and receive telecom bus interface is disabled. bit 5 sts-3c rephase off r/o sts-3c while rephase off: this read/write bit-field permits the user to configure the sts-1 telecom bus # 0 to p rocess sts-3c data while the ?re p hase? feature is disabled. if
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 71 the user configures the sts-1 teleco m bus interface to process sts-3c data then the following f unctional blocks (within t he XRT94L33 dev ice) will now become active. ? the transmit sts-3c poh processor block ? the receive sts-3c poh processor block 0 ? configures sts-1 telecom bus # 0 to process sts-3 data. 1 ? configures sts-1 telecom bus # 0 to process sts-3c data. note: this bit-field is only active if sts-1 telecom bus interface # 0 has been configured to support ?sts-3? operation. this bit-field ignored if sts-1 telecom bus interface # 0 has been configured to operate in the sts-1 mode. bit 4 sts-1 telecom bus parity type # 0 r/w sts-1 telecom bus parity type ? channel 0: this read/write bit-field permits the user to define the parameters, over which ?telecom bus? parity will be computed. 0 ? parity is computed/verified over the transmit and receive sts-1 telecom bus ? data bus pins (e.g., sts1txa_d_0[7:0] and sts1rxd_d_0[7:0]). if the user implements this selection, then the following will happen. a. the sts-1 receive telecom bus interface will compute and output parity (via the ?sts1rxd_dp_0? output pin) based upon and coincident with the data being output via the ?sts1rxd_d_0[7:0]? output pins. b. the sts-1 transmit telecom bus interface will compute and verify the parity data (which is input via the ?sts1txa_dp_0? input pin) based upon the data which is being input (and latched) via the ?sts1txa_d_0[7:0]? input pins. 1 ? parity is computed/verified over the sts-1 transmit and receive telecom bus ? data bus pins (e.g., sts1txa_d_0[7:0] and sts1rxd_d_0[7:0]); the sts1 txa_c1j1_0, sts1rxd_c1j1_0, sts1txa_pl_0 and sts1rxd_pl_0 input/output pins. if the user implements this selection, then the following will happen. a. the sts-1 receive telecom bus interface will compute and output parity (via the ?sts1rxd_dp_0? output) based upon and coincident with (1) the data being output via the ?sts1rxd_d_0[7:0]? output pi ns, (2) the state of the ?sts1rxd_pl_0? output pin, and (3) the state of the ?sts1rxd_c1j1_0? output pin. b. the sts-1 transmit telecom bus interface will compute and verify the parity data (which is input via the ?sts1txa_dp_0? input pin) based upon (1) the data which is being input (and latched) via the ?sts1txa_d_0[7:0]? input pins, (2) the state of the ?sts1txa_pl_0? input pin, and (3) the state of the ?sts1txa_c1j1_0? input pin. note: this bit-field is disabled if the sts-1 telecom bus is disabled. the user can configure the sts-1 telecom bus to compute/verify with either even or odd parity, by writing the appropriate data into bit 2 (telecom bus parity ? odd), within this register. bit 3 sts-1 telecom bus j1 only r/w telecom bus ? j1 indicator only ? channel 0: this read/write bit-field permits t he user to configure how the sts-1 transmit and receive telecom bus interface handles the ? sts1txa c1j1 0 ? and sts1rxd c1j1 0 ? signals as described below
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 72 ?sts1txa_c1j1_0? and sts1rxd_c1j1_0? signals, as described below. 0 ? c1 and j1 bytes this selection configures the following. a. the sts-1 receive telecom bus to pulse the ?sts1rxd_c1j1_0? output coincident to whenever the c1 and j1 bytes are being output via the ?sts1rxd_d_0[7:0]? output pins. b. the sts-1 transmit telecom bus will expect the ?sts1txa_c1j1_0? input to pulse ?high? coincident to whenever the c1 and j1 bytes are being sampled via the ?sts1txa_d_0[7:0]? input pins. 1 ? j1 bytes only this selection configures the following. k. the sts-1 receive telecom bus interface to only pulse the ?sts1rxd_c1j1_0? output pin coincident to whenever the j1 byte is being output via the ?sts 1rxd_d_0[7:0]? output pins. note: the ?sts1rxd_c1j1_0? output pin will not be pulsed ?high? whenever the c1 byte is being output via the ?sts1rxd_d_0[7:0]? output pins l. the sts-1 transmit telecom bus interface will expect the ?sts1txa_c1j1_0? input to only pulse ?high? coincident to whenever the j1 byte is being sampled via the ?sts1txa_d_0[7:0]? input pins. note: the ?sts1txa_c1j1_0? input pin will not be pulsed ?high? whenever the c1 byte is being input via the ?sts1txa_d_0[7:0]? input pins bit 2 sts-1 telecom bus parity odd r/w telecom bus parity ? odd parity select ? channel 0: this read/write bit-field permits the user to configure the sts-1 telecom bus interface, associated with channel 0 to do the following. in the receive (drop) direction receive sts-1 telecom bus to com pute either the eve n or odd parity over the contents of the (1) sts1rx d_d_0[7:0] output pins, or (2) sts1rxd_d_0[7:0] output pins, the states of the sts1rxd_pl_0 and ?sts1rxd_c1j1_0 output pins (depending upon user setting for bit 3). in the transmit (add) direction transmit sts-1 telecom bus to compute and verify the even or odd parity over the contents of the (1) sts1txa_d_0[7:0] input pins, or (2) sts1txa_d_0[7:0] input pins, the states of the sts1txa_pl_0 and sts1txa_c1j1_0 input pins (depending upon user setting for bit 3). 0 ? configures receive (drop) telecom bus to compute even parity and configures the transmit (add) telecom bus to verify even parity 1 ? configures receive (drop) telecom bus to compute odd parity and configures the transmit (add) telecom bus to verify odd parity. bit 1 sts-1 telecom bus parity disable r/w sts-1 telecom bus parity disable ? channel 0: this read/write bit-field permits the user to either enable or disable parity calculation and placement vi a the ?stsrxd_dp_0? output pin. further, this bit field also permits the user to enable or disable parity verification via the ?sts1txa_dp_0? input pin by the transmit telecom bus. 1 ? disables parity calculation (on the receive telecom bus) and disables parity verification (on the transmit telecom bus.
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 73 0 ? enables parity calculation and verification bit 0 sts-1 rephase off r/w sts-1 telecom bus ? rephase disable ? channel 0: this read/write bit-field permits the user to configure the transmit sts- 1 telecom bus (associated with channel 0) to internally compute the pointer bytes, based upon the data that it receives via the ?sts1txa_d[7:0] input pins. note: if the transmit sts-1 telecom bus is being provided with pulses denoting the c1 and j1 bytes (via the ?sts1txa_c1j1? input pin), then this feature is unnecessary. 1 ? disables rephase 0 ? enables rephase
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 74 table 29: interface control register ? sts-1/stm-0 telecom bus interrupt enable/status register (address location= 0x013c) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 unused sts-1 telecom bus # 2 rxparity error interrupt status tb1 rxparity error interrupt status tb0 rxparity error interrupt status unused tb2 rxparity error interrupt enable tb1 rxparity error interrupt enable tb0 rxparity error interrupt enable r/o rur rur rur r/o r/w r/w r/w 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 unused r/o 6 telecom bus # 2 receive parity error interrupt status rur sts-1 telecom bus # 2 ? receive parity error interrupt status: this reset-upon-read bit-field indicates whether or ?sts-1 telecom bus ? channel 2? has declared a ?receive parity error? interrupt since the last read of this register. 0 ? the ?receive parity error? interrupt has not occurred since the last read of this register. 1 ? the ?receive parity error? interrupt has occurred since the last read of this register. note: this bit-field is only active if ?sts-1 telecom bus ? channel 2? has been enabled. 5 telecom bus # 1 receive parity error interrupt status rur sts-1 telecom bus # 1 ? receive parity error interrupt status: this reset-upon-read bit-field indicates whether or ?sts-1 telecom bus ? channel 1? has declared a ?receive parity error? interrupt since the last read of this register. 0 ? the ?receive parity error? interrupt has not occurred since the last read of this register. 1 ? the ?receive parity error? interrupt has occurred since the last read of this register. note: this bit-field is only active if ?sts-1 telecom bus ? channel 1? has been enabled. 4 telecom bus # 0 receive parity error interrupt status rur sts-1 telecom bus # 0 ? receive parity error interrupt status: this reset-upon-read bit-field indicates whether or ?sts-1 telecom bus ? channel 3? has declared a ?receive parity error? interrupt since the last read of this register. 0 ? the ?receive parity error? interrupt has not occurred since the last read of this register. 1 ? the ?receive parity error? interrupt has occurred since the last read of this register. note: this bit-field is only active if ?sts-1 telecom bus ? channel 0? has been enabled. 3 unused r/o
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 75 2 telecom bus # 2 ? receive parity error interrupt enable r/w sts-1 telecom bus # 2 ? receive parity error interrupt enable this read/write bit-field permits the us er to either enable or disable the ?receive parity error? interrupt for st s-1 telecom bus ? channel 2. if the user enables this interrupt, then sts-1 telecom bus ? channel 2 will generate an interrupt anytime the ?rec eive sts-1 telecom bus? detects a parity error within the incoming sts-1 data. 0 ? disables the ?receive parity error? interrupt. 1 ? enables the ?receive parity error? interrupt. note: this bit-field is only active if ?sts-1 telecom bus ? channel 2? has been enabled. 1 telecom bus # 1 ? receive parity error interrupt enable r/w sts-1 telecom bus # 1 ? receive parity error interrupt enable this read/write bit-field permits the us er to either enable or disable the ?receive parity error? interrupt for sts-1telecom bus ? channel 1. if the user enables this interrupt, then sts-1 telecom bus ? channel 1 will generate an interrupt anytime the ?rec eive sts-1 telecom bus? detects a parity error within the incoming sts-1 data. 0 ? disables the ?receive parity error? interrupt. 1 ? enables the ?receive parity error? interrupt. note: this bit-field is only active if ?sts-1 telecom bus ? channel 1? has been enabled. 0 telecom bus # 0 ? receive parity error interrupt enable r/w sts-1 telecom bus # 0 ? receive parity error interrupt enable this read/write bit-field permits the us er to either enable or disable the ?receive parity error? interrupt for st s-1 telecom bus ? channel 0. if the user enables this interrupt, then sts-1 telecom bus ? channel 0 will generate an interrupt anytime the ?rec eive sts-1 telecom bus? detects a parity error within the incoming sts-1 data. 0 ? disables the ?receive parity error? interrupt. 1 ? enables the ?receive parity error? interrupt. note: this bit-field is only active if ?sts-1 telecom bus ? channel 0? has been enabled.
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 76 table 30: interface control register ? sts-1/st m-0 telecom bus fifo status register (address location = 0x013d) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 unused unused sts-1 telecom bus tx overrun bus 2 sts-1 telecom bus tx underrun bus 2 sts-1 telecom bus tx overrun bus 1 sts-1 telecom bus tx underrun bus 1 sts-1 telecom bus tx overrun bus 0 sts-1 telecom bus tx underrun bus 0 r/o r/o r/o r/o r/o r/o r/o r/o 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 unused r/o 6 unused r/o 5 sts-1 telecom bus ? txfifo overrun # 2 r/o sts-1 telecom bus ? transmit fifo overrun indicator ? channel 2: this read-only bit-field indicates whether or not ?sts-1 telecom bus ? channel 2? is currently declaring a ?transmit fifo overrun? condition. 0 ? indicates that ?sts-1 telecom bus ? channel 2? is not declaring a ?transmit fifo overrun? condition. 1 ? indicates that ?sts-1 telecom bus ? channel 2? is currently declaring a ?transmit fifo overrun? condition. note: this bit-field is only active if ?sts-1 telecom bus ? channel 2? has been enabled. 4 sts-1 telecom bus ? txfifo underrun # 2 r/o sts-1 telecom bus ? transmit fifo underrun indicator ? channel 2: this read-only bit-field indicates whether or not ?sts-1 telecom bus ? channel 3? is currently declaring a ?transmit fifo underrun? condition. 0 ? indicates that ?sts-1 telecom bus ? channel 2? is not declaring a ?transmit fifo underrun? condition. 1 ? indicates that ?sts-1 telecom bus ? channel 2? is currently declaring a ?transmit fifo underrun? condition. note: this bit-field is only active if ?sts-1 telecom bus ? channel 2? has been enabled. 3 sts-1 telecom bus ? txfifo overrun # 1 r/o sts-1 telecom bus ? transmit fifo overrun indicator ? channel 1: this read-only bit-field indicates whether or not ?sts-1 telecom bus ? channel 1? is currently declaring a ?transmit fifo overrun? condition. 0 ? indicates that ?sts-1 telecom bus ? channel 1? is not declaring a ?transmit fifo overrun? condition. 1 ? indicates that ?sts-1 telecom bus ? channel 1? is currently declaring a ?transmit fifo overrun? condition. note: this bit-field is only active if ?sts-1 telecom bus ? channel 1? has been enabled. 2 sts-1 telecom bus ? txfifo underrun # 1 r/o sts-1 telecom bus ? transmit fifo underrun indicator ? channel 1: this read-only bit-field indicates whether or not ?sts-1 telecom bus ? channel 1? is currently declaring a ?transmit fifo underrun? condition. 0 ? indicates that ?sts-1 telecom bus ? channel 1? is not declarin g a
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 77 ?transmit fifo underrun? condition. 1 ? indicates that ?sts-1 telecom bus ? channel 1? is currently declaring a ?transmit fifo underrun? condition. note: this bit-field is only active if ?sts-1 telecom bus ? channel 1? has been enabled. 1 sts-1 telecom bus ? txfifo overrun # 0 r/o sts-1 telecom bus ? transmit fifo overrun indicator ? channel 0: this read-only bit-field indicates whether or not ?sts-1 telecom bus ? channel 0? is currently declaring a ?transmit fifo overrun? condition. 0 ? indicates that ?sts-1 telecom bus ? channel 0? is not declaring a ?transmit fifo overrun? condition. 1 ? indicates that ?sts-1 telecom bus ? channel 0? is currently declaring a ?transmit fifo overrun? condition. note: this bit-field is only active if ?sts-1 telecom bus ? channel 0? has been enabled. 0 sts-1 telecom bus ? txfifo underrun # 0 r/o sts-1 telecom bus ? transmit fifo underrun indicator ? channel 0: this read-only bit-field indicates whether or not ?sts-1 telecom bus ? channel 0? is currently declaring a ?transmit fifo underrun? condition. 0 ? indicates that ?sts-1 telecom bus ? channel 0? is not declaring a ?transmit fifo underrun? condition. 1 ? indicates that ?sts-1 telecom bus ? channel 0? is currently declaring a ?transmit fifo underrun? condition. note: this bit-field is only active if ?sts-1 telecom bus ? channel 0? has been enabled.
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 78 table 31: interface control register ? sts-1/stm- 0 telecom bus fifo interrupt status register (address location= 0x013e) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 unused unused sts-1 telecom bus # 2 tx overrun interrupt status sts-1 telecom bus # 2 tx underrun interrupt status sts-1 telecom bus # 1 tx overrun interrupt status sts-1 telecom bus # 1 tx underrun interrupt status sts-1 telecom bus # 0 tx overrun interrupt status sts-1 telecom bus # 0 tx underrun interrupt status r/o r/o rur rur rur rur rur rur 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 unused r/o 6 unused r/o 5 sts-1 telecom bus # 2 ? txfifo overrun interrupt status rur sts-1 telecom bus ? txfifo overrun interrupt status ? channel 2: this reset-upon-read bit-field indicates whether or not ?sts-1 telecom bus ? channel 2? has declared a ?txfifo overrun? interrupt since the last read of this register. 0 ? indicates that ?sts-1 telecom bus ? channel 2? has not declared a ?txfifo overrun? interrupt since the last read of this register. 1 ? indicates that ?sts-1 telecom bus ? channel 2? has declared a ?txfifo overrun? interrupt since the last read of this register. note: this bit-field is only active if ?sts-1 telecom bus ? channel 2? has been enabled. 4 sts-1 telecom bus # 2 ? txfifo underrun interrupt status rur sts-1 telecom bus ? txfifo underrun interrupt status ? channel 2: this reset-upon-read bit-field indicates whether or not ?sts-1 telecom bus ? channel 2? has declared a ?txfifo underrun? interrupt since the last read of this register. 0 ? indicates that ?sts-1 telecom bus ? channel 2? has not declared a ?txfifo underrun? interrupt since the last read of this register. 1 ? indicates that ?sts-1 telecom bus ? channel 2? has declared a ?txfifo overrun? interrupt since the last read of this register. note: this bit-field is only active if ?sts-1 telecom bus ? channel 2? has been enabled. 3 sts-1 telecom bus # 1 ? txfifo overrun interrupt status rur sts-1 telecom bus ? txfifo overrun interrupt status ? channel 1: this reset-upon-read bit-field indicates whether or not ?sts-1 telecom bus ? channel 1? has declared a ?txfifo overrun? interrupt since the last read of this register. 0 ? indicates that ?sts-1 telecom bus ? channel 1? has not declared a ?txfifo overrun? interrupt since the last read of this register. 1 ? indicates that ?sts-1 telecom bus ? channel 1? has declared a ?txfifo overrun? interrupt since the last read of this register. note: this bit-field is only active if ?sts-1 telecom bus ? channel 1? has been enabled. 2 sts-1 telecom bus # 1 ? rur sts-1 telecom bus ? txfifo underrun interrupt status ? channel 1:
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 79 txfifo underrun interrupt status this reset-upon-read bit-field indicates whether or not ?sts-1 telecom bus ? channel 1? has declared a ?txfifo underrun? interrupt since the last read of this register. 0 ? indicates that ?sts-1 telecom bus ? channel 1? has not declared a ?txfifo underrun? interrupt since the last read of this register. 1 ? indicates that ?sts-1 telecom bus ? channel 1? has declared a ?txfifo overrun? interrupt since the last read of this register. note: this bit-field is only active if ?sts-1 telecom bus ? channel 1? has been enabled. 1 sts-1 telecom bus # 0 ? txfifo overrun interrupt status rur sts-1 telecom bus ? txfifo overrun interrupt status ? channel 0: this reset-upon-read bit-field indicates whether or not ?sts-1 telecom bus ? channel 0? has declared a ?txfifo overrun? interrupt since the last read of this register. 0 ? indicates that ?sts-1 telecom bus ? channel 0? has not declared a ?txfifo overrun? interrupt since the last read of this register. 1 ? indicates that ?sts-1 telecom bus ? channel 0? has declared a ?txfifo overrun? interrupt since the last read of this register. note: this bit-field is only active if ?sts-1 telecom bus ? channel 0? has been enabled. 0 sts-1 telecom bus # 0 ? txfifo underrun interrupt status rur sts-1 telecom bus ? txfifo underrun interrupt status ? channel 0: this reset-upon-read bit-field indicates whether or not ?sts-1 telecom bus ? channel 0? has declared a ?txfifo underrun? interrupt since the last read of this register. 0 ? indicates that ?sts-1 telecom bus ? channel 0? has not declared a ?txfifo underrun? interrupt since the last read of this register. 1 ? indicates that ?sts-1 telecom bus ? channel 0? has declared a ?txfifo overrun? interrupt since the last read of this register. note: this bit-field is only active if ?sts-1 telecom bus ? channel 0? has been enabled.
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 80 table 32: interface control register ? sts-1/stm- 0 telecom bus fifo interrupt enable register (address location= 0x013f) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 unused unused sts-1 telecom bus # 2 tx overrun interrupt enable sts-1 telecom bus # 2 tx underrun interrupt enable sts-1 telecom bus # 1 tx overrun interrupt enable sts-1 telecom bus # 1 tx underrun interrupt enable sts-1 telecom bus # 0 tx overrun interrupt enable sts-1 telecom bus # 0 tx underrun interrupt enable r/o r/o r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 unused r/o 6 unused r/o 5 sts-1 telecom bus # 2 txfifo overrun interrupt enable sts-1 telecom bus ? txfifo overrun interrupt enable ? channel 2: this read/write bit-field permits the user to either enable or disable the ?txfifo overrun? interrupt, associated with sts-1 telecom bus ? channel 2. if the user enables this interrupt, then the ?sts-1 telecom bus ? channel 2? will generate an interrupt anytime it declares the ?txfifo overrun? condition. 0 ? disables the ?txfifo overrun? interrupt, associated with ?sts-1 telecom bus ? channel 2. 1 ? enables the ?txfifo overrun? interrupt, associated with ?sts-1 telecom bus ? channel 2. note: this bit-field is only active if ?sts-1 telecom bus ? channel 2? has been enabled. 4 sts-1 telecom bus # 2 txfifo underrun interrupt enable r/w sts-1 telecom bus ? txfifo underrun interrupt enable ? channel 2: this read/write bit-field permits the user to either enable or disable the ?txfifo underrun? interrupt, associated with sts-1 telecom bus ? channel 2. if the user enables this interrupt, then the ?sts-1 telecom bus ? channel 2? will generate an interrupt anytime it declares the ?txfifo underrun? condition. 0 ? disables the ?txfifo underrun? interrupt, associated with ?sts-1 telecom bus ? channel 2. 1 ? enables the ?txfifo underrun? interrupt, associated with ?sts-1 telecom bus ? channel 2. note: this bit-field is only active if ?sts-1 telecom bus ? channel 2? has been enabled. 3 sts-1 telecom bus # 1 txfifo overrun interrupt enable r/w sts-1 telecom bus ? txfifo overrun interrupt enable ? channel 1: this read/write bit-field permits the user to either enable or disable the ?txfifo overrun? interrupt, associated with sts-1 telecom bus ? channel 1. if the user enables this interrupt, then the ?sts-1 telecom bus ? channel 1? will generate an interrupt anytime it declares the ?txfifo overrun? condition. 0 ? disables the ?txfifo overrun? interrupt, associated with ?sts-1 telecom bus ? channel 1. 1 ? enables the ?txfifo overrun? interru p t, associated with ?sts-1
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 81 telecom bus ? channel 1. note: this bit-field is only active if ?sts-1 telecom bus ? channel 1? has been enabled. 2 sts-1 telecom bus # 1 txfifo underrun interrupt enable r/w sts-1 telecom bus ? txfifo underrun interrupt enable ? channel 1: this read/write bit-field permits the user to either enable or disable the ?txfifo underrun? interrupt, associated with sts-1 telecom bus ? channel 1. if the user enables this interrupt, then the ?sts-1 telecom bus ? channel 1? will generate an interrupt anytime it declares the ?txfifo underrun? condition. 0 ? disables the ?txfifo underrun? interrupt, associated with ?sts-1 telecom bus ? channel 1. 1 ? enables the ?txfifo underrun? interrupt, associated with ?sts-1 telecom bus ? channel 1. note: this bit-field is only active if ?sts-1 telecom bus ? channel 1? has been enabled. 1 sts-1 telecom bus # 0 txfifo overrun interrupt enable r/w sts-1 telecom bus ? txfifo overrun interrupt enable ? channel 0: this read/write bit-field permits the user to either enable or disable the ?txfifo overrun? interrupt, associated with sts-1 telecom bus ? channel 0. if the user enables this interrupt, then the ?sts-1 telecom bus ? channel 0? will generate an interrupt anytime it declares the ?txfifo overrun? condition. 0 ? disables the ?txfifo overrun? interrupt, associated with ?sts-1 telecom bus ? channel 0. 1 ? enables the ?txfifo overrun? interrupt, associated with ?sts-1 telecom bus ? channel 0. note: this bit-field is only active if ?sts-1 telecom bus ? channel 0? has been enabled. 0 sts-1 telecom bus # 0 txfifo underrun interrupt enable r/w sts-1 telecom bus ? txfifo underrun interrupt enable ? channel 0: this read/write bit-field permits the user to either enable or disable the ?txfifo underrun? interrupt, associated with sts-1 telecom bus ? channel 3. if the user enables this interrupt, then the ?sts-1 telecom bus ? channel 0? will generate an interrupt anytime it declares the ?txfifo underrun? condition. 0 ? disables the ?txfifo underrun? interrupt, associated with ?sts-1 telecom bus ? channel 0. 1 ? enables the ?txfifo underrun? interrupt, associated with ?sts-1 telecom bus ? channel 0. note: this bit-field is only active if ?sts-1 telecom bus ? channel 0? has been enabled.
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 82 table 33: operation general purpose input/output register ? byte 0 (address location= 0x0147) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 gpio_7 gpio_6 gpio_5 gpio_4 gpio_3 gpio_2 gpio_1 gpio_0 r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 gpio_7 r/w general purpose input/output pin # 7: the exact function of this read/write bit-field depends upon whether the ?gpio_7? pin is configured to be an input or an output pin. if gpio_7 is configured to be an input pin: if gpio_7 is configured to be an input pin, then this register bit operates as a read-only bit-field that reflects the state of the ?gpio_7? (pin number aa25) input pin. if the ?gpio_7? input pin is pulled to a lo gic ?high?, then this register bit will be set to ?1?. conversely, if the ?gpio_7? input pin is pulled to a logic ?low?, then this register bit will be set to ?0?. if gpio_7 is configured to be an output pin: if gpio_7 is configured to be an output pi n, then the user can control the logic level of ?gpio_7? by writing the appr opriate value into this bit-field. setting this bit-field to ?0? causes the gpio_7 output pin to be driven ?low?. conversely, setting this bit-field to ?1? causes the gpio_7 output pin to be driven ?high?. note: this register bit-field is only active if sts-1 telecom bus ? channel 2 is enabled. 6 gpio_6 r/w general purpose input/output pin # 6: the exact function of this read/write bit-field depends upon whether the ?gpio_6? pin is configured to be an input or an output pin. if gpio_6 is configured to be an input pin: if gpio_6 is configured to be an input pin, then this register bit operates as a read-only bit-field that reflects the st ate of the ?gpio_6? (pin number w24) input pin. if the ?gpio_6? input pin is pulled to a lo gic ?high?, then this register bit will be set to ?1?. conversely, if the ?gpio_6? input pin is pulled to a logic ?low?, then this register bit will be set to ?0?. if gpio_6 is configured to be an output pin: if gpio_6 is configured to be an output pi n, then the user can control the logic level of ?gpio_6? by writing the appr opriate value into this bit-field. setting this bit-field to ?0? causes the gpio_6 output pin to be driven ?low?. conversely, setting this bit-field to ?1? causes the gpio_6 output pin to be driven ?high?. note: this register bit-field is only active if sts-1 telecom bus ? channel 2 is enabled. 5 gpio_5 r/w general purpose input/output pin # 5: the exact function of this read/write bit-field depends upon whether the ?gpio_5? pin is configured to be an input or an output pin.
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 83 if gpio_5 is configured to be an input pin: if gpio_5 is configured to be an input pin, then this register bit operates as a read-only bit-field that reflects the state of the ?gpio_5? (pin number ac26) input pin. if the ?gpio_5? input pin is pulled to a lo gic ?high?, then this register bit will be set to ?1?. conversely, if the ?gpio_5? input pin is pulled to a logic ?low?, then this register bit will be set to ?0?. if gpio_5 is configured to be an output pin: if gpio_5 is configured to be an output pi n, then the user can control the logic level of ?gpio_5? by writing the appr opriate value into this bit-field. setting this bit-field to ?0? causes the gpio_5 output pin to be driven ?low?. conversely, setting this bit-field to ?1? causes the gpio_5 output pin to be driven ?high?. note: this register bit-field is only active if sts-1 telecom bus ? channel 1 is enabled. 4 gpio_4 r/w general purpose input/output pin # 4: the exact function of this read/write bit-field depends upon whether the ?gpio_4? pin is configured to be an input or an output pin. if gpio_4 is configured to be an input pin: if gpio_4 is configured to be an input pin, then this register bit operates as a read-only bit-field that reflects the st ate of the ?gpio_4? (pin number y25) input pin. if the ?gpio_4? input pin is pulled to a lo gic ?high?, then this register bit will be set to ?1?. conversely, if the ?gpio_4? input pin is pulled to a logic ?low?, then this register bit will be set to ?0?. if gpio_4 is configured to be an output pin: if gpio_4 is configured to be an output pi n, then the user can control the logic level of ?gpio_4? by writing the appr opriate value into this bit-field. setting this bit-field to ?0? causes the gpio_4 output pin to be driven ?low?. conversely, setting this bit-field to ?1? causes the gpio_4 output pin to be driven ?high?. note: this register bit-field is only active if sts-1 telecom bus ? channel 1 is enabled. 3 gpio_3 r/w general purpose input/output pin # 3: the exact function of this read/write bit-field depends upon whether the ?gpio_3? pin is configured to be an input or an output pin. if gpio_3 is configured to be an input pin: if gpio_3 is configured to be an input pin, then this register bit operates as a read-only bit-field that reflects the state of the ?gpio_3? (pin number ab26) input pin. if the ?gpio_3? input pin is pulled to a lo gic ?high?, then this register bit will be set to ?1?. conversely, if the ?gpio_3? input pin is pulled to a logic ?low?, then this register bit will be set to ?0?. if gpio_3 is configured to be an output pin: if gpio_3 is configured to be an output pi n, then the user can control the logic level of ?gpio_3? by writing the appr opriate value into this bit-field. setting this bit-field to ?0? causes the gpio_3 output pin to be driven ?low?. conversely, setting this bit-field to ?1? causes the gpio_3 output pin to be driven ?high?.
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 84 note: this register bit-field is only active if sts-1 telecom bus ? channel 1 is enabled. 2 gpio_2 r/w general purpose input/output pin # 2: the exact function of this read/write bit-field depends upon whether the ?gpio_2? pin is configured to be an input or an output pin. if gpio_2 is configured to be an input pin: if gpio_2 is configured to be an input pin, then this register bit operates as a read-only bit-field that reflects the st ate of the ?gpio_2? (pin number v23) input pin. if the ?gpio_2? input pin is pulled to a lo gic ?high?, then this register bit will be set to ?1?. conversely, if the ?gpio_2? input pin is pulled to a logic ?low?, then this register bit will be set to ?0?. if gpio_2 is configured to be an output pin: if gpio_2 is configured to be an output pi n, then the user can control the logic level of ?gpio_2? by writing the appr opriate value into this bit-field. setting this bit-field to ?0? causes the gpio_2 output pin to be driven ?low?. conversely, setting this bit-field to ?1? causes the gpio_2 output pin to be driven ?high?. note: this register bit-field is only active if sts-1 telecom bus ? channel 0 is enabled. 1 gpio_1 r/w general purpose input/output pin # 1: the exact function of this read/write bit-field depends upon whether the ?gpio_1? pin is configured to be an input or an output pin. if gpio_1 is configured to be an input pin: if gpio_1 is configured to be an input pin, then this register bit operates as a read-only bit-field that reflects the state of the ?gpio_1? (pin number ac27) input pin. if the ?gpio_1? input pin is pulled to a lo gic ?high?, then this register bit will be set to ?1?. conversely, if the ?gpio_1? input pin is pulled to a logic ?low?, then this register bit will be set to ?0?. if gpio_1 is configured to be an output pin: if gpio_1 is configured to be an output pi n, then the user can control the logic level of ?gpio_1? by writing the appr opriate value into this bit-field. setting this bit-field to ?0? causes the gpio_1 output pin to be driven ?low?. conversely, setting this bit-field to ?1? causes the gpio_1 output pin to be driven ?high?. note: this register bit-field is only active if sts-1 telecom bus ? channel 0 is enabled. 0 gpio_0 r/w general purpose input/output pin # 0: the exact function of this read/write bit-field depends upon whether the ?gpio_0? pin is configured to be an input or an output pin. if gpio_0 is configured to be an input pin: if gpio_0 is configured to be an input pin, then this register bit operates as a read-only bit-field that reflects the st ate of the ?gpio_0? (pin number w25) input pin. if the ?gpio_0? input pin is pulled to a lo gic ?high?, then this register bit will be set to ?1?. conversely, if the ?gpio_0? input pin is pulled to a logic ?low?, then this register bit will be set to ?0?.
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 85 if gpio_0 is configured to be an output pin: if gpio_0 is configured to be an output pi n, then the user can control the logic level of ?gpio_0? by writing the appr opriate value into this bit-field. setting this bit-field to ?0? causes the gpio_0 output pin to be driven ?low?. conversely, setting this bit-field to ?1? causes the gpio_0 output pin to be driven ?high?. note: this register bit-field is only active if sts-1 telecom bus ? channel 0 is enabled.
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 86 table 34: operation general purpose input/output direction register 0 (address location= 0x014b) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 gpio_dir[7:0] r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 gpio_dir[7] r/w gpio_7 direction select: this read/write bit-field permits the user to configure the ?gpio_7? pin (pin number aa25) to function as either an input or an output pin. 0 ? configures gpio_7 to function as an input pin. 1 ? configures gpio_7 to function as an output pin. note: this register bit-field is only active if sts-1 telecom bus interface ? channel 2 is enabled. 6 gpio_dir[6] r/w gpio_6 direction select: this read/write bit-field permits the user to configure the ?gpio_6? pin (pin number w24) to function as either an input or an output pin. 0 ? configures gpio_6 to function as an input pin. 1 ? configures gpio_6 to function as an output pin. note: this register bit-field is only active if sts-1 telecom bus interface ? channel 2 is enabled. 5 gpio_dir[5] r/w gpio_5 direction select: this read/write bit-field permits the user to configure the ?gpio_5? pin (pin number ac26) to function as either an input or an output pin. 0 ? configures gpio_5 to function as an input pin. 1 ? configures gpio_5 to function as an output pin. note: this register bit-field is only active if sts-1 telecom bus interface ? channel 1 is enabled. 4 gpio_dir[4] r/w gpio_4 direction select: this read/write bit-field permits the user to configure the ?gpio_4? pin (pin number y25) to function as either an input or an output pin. 0 ? configures gpio_4 to function as an input pin. 1 ? configures gpio_4 to function as an output pin. note: this register bit-field is only active if sts-1 telecom bus interface ? channel 1 is enabled. 3 gpio_dir[3] r/w gpio_3 direction select: this read/write bit-field permits the user to configure the ?gpio_3? pin (pin number ab26) to function as either an input or an output pin. 0 ? configures gpio_3 to function as an input pin. 1 ? configures gpio_3 to function as an output pin. note: this register bit-field is only active if sts-1 telecom bus interface ? channel 1 is enabled.
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 87 2 gpio_dir[2] r/w gpio_2 direction select: this read/write bit-field permits the user to configure the ?gpio_2? pin (pin number v23) to function as either an input or an output pin. 0 ? configures gpio_2 to function as an input pin. 1 ? configures gpio_2 to function as an output pin. note: this register bit-field is only active if sts-1 telecom bus interface ? channel 0 is enabled. 1 gpio_dir[1] r/w gpio_1 direction select: this read/write bit-field permits the user to configure the ?gpio_1? pin (pin number ac27) to function as either an input or an output pin. 0 ? configures gpio_1 to function as an input pin. 1 ? configures gpio_1 to function as an output pin. note: this register bit-field is only active if sts-1 telecom bus interface ? channel 0 is enabled. 0 gpio_dir[0] r/w gpio_0 direction select: this read/write bit-field permits the user to configure the ?gpio_0? pin (pin number w25) to function as either an input or an output pin. 0 ? configures gpio_0 to function as an input pin. 1 ? configures gpio_0 to function as an output pin. note: this register bit-field is only active if sts-1 telecom bus interface ? channel 0 is enabled.
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 88 table 35: operation output control register ? byte 1 (address location= 0x0150) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 8khz or stuff out enable 8khz out select egress direction monitored ? stuff output unused r/w r/w r/w r/o r/o r/o r/o r/o 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 8khz or stuff out enable r/w 8khz or stuff output enable ? lof output pin: this read/write bit-field, along wi th bit 6 (8khz out select) permits the user to define the role of the lof output pin (pin ad11). the relationship between the states of these bit-fields and the corresponding role of the lof output pi n is presented below. bit 7 (8khz or stuff out enable) bit 6 (8khz out select) role of lof output pin 0 0 lof or ais-l indicator 0 1 lof or ais-l indicator 1 0 bit stuff indicator output 1 1 8khz output note: 1. if bit 7 is set to ?0?, then bit 1 (ais -l output enable) within the ?receive sts-3 transport ? auto ais (in down stream sts-1s) control register (address location= 0x116b) will indict ate whether or not pin ad11 is the ?lof? or the ?ais-l? output indicator. 2. if bit 1 (ais-l output enable) is set to ?0?, then pin ad11 will function as the lof output indicator. 3. if bit 1 (ais-l output enable) is set to ?1?, then pin ad11 will function as the ais-l output indicator. 6 8khz out select r/w 8khz out ? lof output pin: this read/write bit-field, along wi th bit 6 (8khz out select) permits the user to define the role of the lof output pin (pin ad11). the relationship between the states of these bit-fields and the corresponding role of the lof output pi n is presented below. bit 7 (8khz or stuff out enable) bit 6 (8khz out select) role of lof output pin 0 0 lof or ais-l indicator 0 1 lof or ais-l indicator 1 0 bit stuff indicator output 1 1 8khz output
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 89 5 egress direct monitored ?stuff output r/w egress direction monitored ? stuff output: if the lof output pin has been conf igured to function as a ?stuff indicator? output, then it can be confi gured to reflect the current stuff opportunities of the channel designated by bits 7 through 4 (stuff indicator channel select[3:0]) with in the operation output control register ? byte 0. this read/write bit-field permits the user to configure the lof output pin to either reflect the ?current st uff opportunities? for the ingress or egress path of the selected channel. 0 ? configures the lof output pin to reflect the ?current stuff opportunity? of the ingress path of the ?selected? channel. 1 ? configures the lof output pin to reflect the ?current stuff opportunity? of the egress path of the ?selected? channel. note: this bit-field will be ignored if the ?selected? channel has been configured to operate in the sts-1 mode. 4 ? 0 unused r/o
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 90 table 36: operation output control register ? byte 0 (address location= 0x0153) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 unused stuff indicator channel select[1:0] unused 8khz source channel select[1:0] r/o r/o r/w r/w r/o r/o r/w r/w 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 ? 6 unused r/o 5 ? 4 stuff indicator channel select[1:0] r/w stuff indicator ? ch annel select[1:0]: these two (2) read/write bit-fields permit the user to identify which of the 3 channels should have their ?bit-stuff opportunity? status reflected on the lof output pin. setting these bit-fields to [0, 0] configures the lof output pin to reflect the bit-stuff opportunity status of ch annel 0. likewise, setting these bit- fields to [1, 0] configures the lof output pin to reflect the bit-stuff opportunity status of channel 2. note: these bit-fields are ignored if any of the following are true. 1. if the corresponding channel has been configured to operate in the sts-1 mode. 2. if the lof output pin has been conf igured to function as the lof or ais-l indicator output. 3. if the lof output pin has been conf igured to function as an 8khz output pin. 3 ? 2 unused r/o 1 ? 0 8khz source channel select[1:0] r/w 8khz source channel select[1:0]: if the lof output pin has been config ured to output an 8khz clock output signal, then the XRT94L33 will derive this 8khz clock signal, from the ingress ds3/e3 or receive sts-1 signal of the ?selected? channel. these two(2) read/write bit-fields permit the user to specify the ?selected? channel. setting these bit-fields to [0, 0] c onfigures the lof output pin to output an 8khz clock signal, that is deriv ed from the ingress ds3/e3 or receive sts-1 input signal of channel 0. likewise, setting these bit- fields to [1, 0] configures the lof output pin to reflect the bit-stuff opportunity status of channel 2. note: these bit-fields are ignored if any of the following are true. 1. if the lof output pin has been conf igured to function as the lof or ais-l indicator output. 2. if the lof output pin has been configured to function as the ?stuff indicator? output pin.
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 91 table 37: operation slow speed port control register ? byte 1 (address location= 0x0154) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 ssi port enable ssi port ? insert direction ssi port - force all zeros pattern unused sse port enable sse port ? insert direction sse port - force all zeros pattern unused r/w r/w r/w r/o r/w r/w r/w r/o 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 ssi port enable r/w slow-speed ingress ? interface port enable: this read/write bit-field permits t he user to enable or disable the ssi (slow-speed ingress) interface port. if the ssi interface port is enabled, then it can be used to do either of the following. ? to monitor (e.g., to drop out a replica of) the ds3, e3 or sts-1 signal, that is traveling in the ingress direc tion ds3/e3 or receive sts-1 path of the ?selected? channel within the XRT94L33 device. ? to insert (e.g., to add-in) and overwr ite the ds3, e3 or sts-1 signal, that is traveling in the ingress direction ds3/e3 or receive sts-1 path of the ?selected? channel within the XRT94L33 device. 0 ? disables the ssi interface port. 1 ? enables the ssi interface port. 6 ssi port ? insert direction r/w slow-speed ingress ? interface port ? insert direction: this read/write bit-field permits the user to configure the ssi interface port to either monitor (e.g., extract) an ?ingress direction ds3/e3? or ?receive sts-1? signal, or to replace (e.g., insert) a ds3, e3 or sts-1 signal into the ingress ds3/e3 or receive sts-1 path of the ?selected? channel. if the user configures the ssi interface port to monitor a given ds3, e3 or sts-1 signal, then the ssi interface will then be configured to be an ?output? interface. in this case , the ssi interface port will consist of an ?ssi_pos?, ?ssi_neg? and ?ssi_clk? output signal s. additionally, a copy of the selected ingress direction ds3/e3 or receive sts-1 signal will be output via this output port. if the user configures the ssi interfac e port to replace (e.g., insert) an ?ingress ds3/e3? or receive sts-1 si gnal, then the ssi interface will then be configured to be an ?input? interface. in this case, the ssi interface port will consist of an ?ssi_pos?, ?ssi _neg? and ?ssi_clk? input signals. additionally, the ds3, e3 or sts-1 signal that is applied at this input port will overwrite that of the selected ?ingr ess direction ds3/e3? or the receive sts-1 signal. 0 ? configures the ssi interface as an output port that will permit the user to monitor the ?selected? ingress ds 3/e3 or receive sts-1 signal. 1 ? configures the ssi interface as an input port. in this configuration, the ds3, e3 or sts-1 signal that is input via this port will replace/overwrite the ?ingress? ds3/e3 or receive sts-1 si gnal, within the ?selected? channel, prior to being mapped into sts-3. note: this bit-field will be ignored if t he ssi interface port is disabled.
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 92 5 ssi port - force all zeros pattern r/w slow speed ingress ? interface port ? force all zeros pattern: this read/write bit-field permits the user to force the ingress ds3/e3 or receive sts-1 signal, within the ?selected? channel to an ?all zeros? pattern. 0 ? configures the selected ingress direction ds3/e3 or receive sts-1 signal (within the ?selected? channel) to flow to the ds3/e3 mapper block or to the transmit sonet poh proce ssor block, in a normal manner. 1 ? forces the data, within the selected ingress direction ds3/e3 or receive sts-1 signal (within the ?selected? channel) to an ?all zeros? pattern. note: this bit-field will be ignored if t he ssi interface port is disabled. 4 unused r/o 3 sse port enable r/w slow-speed egress ? interface port enable: this read/write bit-field permits the user to enable or disable the sse (slow speed egress) interface port. if the sse interface port is enabled, then it can be used to do either of the following. ? to monitor (e.g., to drop out a replica of) the ds3, e3 or sts-1 signal, that is traveling in the egress direc tion ds3/e3 or transmit sts-1 path of the ?selected? channel within the XRT94L33 device. ? to insert (e.g., to add in) and overwrite the ds3, e3 or sts-1 signal, that is traveling in the engress direction ds3/e3 or transmit sts-1 path of the ?selected? channel within the XRT94L33 device. 0 ? disables the sse interface port 1 ? enables the sse interface port. 2 sse port ? insert direction r/w slow speed egress ? interface port ? insert direction: this read/write bit-field permits the user to configure the sse interface port to either monitor (e.g., extract) an ?egress direction ds3/e3? or ?transmit sts-1? signal, or to replac e (e.g., insert) a ds3, e3 or sts-1 signal into the egress direction ds3/e3 or transmit sts-1 path of the ?selected? channel. if the user configures the sse interfac e port to monitor a given ds3, e3 or sts-1 signal, then the sse interface wil then be configured to be an ?output? interface. in this case, t he sse interface port will consist of an ?sse_pos?, ?sse_neg? and ?sse_clk? output signals. additionally, a copy of the selected egress direction ds3/e3 or transmit sts-1 signal will be output via this output port. if the user configures the sse interfac e port to replace (e.g., insert) an ?egress ds3/e3? or transmit sts-1 signal, then the sse interface will then be configured to be an ?input? interface. in this case, the sse interface port will consist of an ?sse_pos?, ?sse_neg? and ?sse_clk? input signals. additionally, the ds3, e3 or sts-1 signal, that is applied at this input port will overwrite that of the selected ?egress direction ds3/e3? or the transmit sts-1 signal. 0 ? configures the sse interface as an ou tput port that will permit the user to monitor the ?selected? egress ds3/e3 or transmit sts-1 signal.. 1 ? configures the sse interface as an in put port. in this configurat ion, the ds3, e3 or sts-1 signal that is input via this port will replace/overwrite the ?egress? ds3/e3 or transmit sts-1 signal, within the ?selected? channel, prior to being mapped into sts-3.
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 93 note: this bit-field will be ignored if the sse interface port is disabled. 1 sse port - force all zeros pattern r/w slow speed egress ? interface port ? force to all zeros: this read/write bit-field permits the user to force the egress ds3/e3 or transmit sts-1 signal, within the ?selected? channel to an ?all zeros? pattern. 0 ? configures the selected egress direction ds3/e3 or transmit sts-1 signal (within the ?selected? channel) to flow to the ds3/e3/sts-1 liu ic in a normal manner. 1 ? forces the data, within the se lected egress direction ds3/e3 or transmit sts-1 signal (within the ?selected? channel) to an ?all zeros? pattern. note: this bit-field will be ignored if the sse interface port is disabled. 0 unused r/o
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 94 table 38: operation slow speed port control register ? byte 0 (address location= 0x0157) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 unused ssi_channel_select[1:0] unused sse_channel_select[1:0] r/o r/o r/w r/w r/o r/o r/w r/w 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 ? 6 unused r/o 5 ? 4 ssi_channel_select[ 1:0]: r/w slow-speed ingress ? interface port ? channel select[1:0]: these read/write bit-fields permit t he user to select which of the 3 ingress direction ds3/e3 or receive sts-1 signals will be processed via the ssi interface port. setting ssi_channel_select[1:0] to [0, 0] configures the ssi interface port to process the ingress direction ds3/e3 or receive sts-1 signal associated with channel 0. likewise, setting ssi_channel_select[1:0] to [1, 0] configures the ssi interface port to process the ingress ds3/e3 or receive sts-1 signal associated with channel 2. note: these bit-fields are ignored if t he ssi interface port is disabled. 3 ?2 unused r/o 1 ? 0 sse_channel_select [1:0] r/w slow speed egress ? interface port ? channel select[1:0]: these read/write bit-fields permit t he user to select which of the 3 egress direction ds3/e3 or receive sts-1 signals will be processed via the sse interface port. setting sse_channel_select[1:0] to [0 , 0] configures the sse interface port to process the egress direction ds3/e3 or transmit sts-1 signal associated with channel 0. likewi se, setting sse_channel_select[1:0] to [1, 0] configures the sse interface por t to process the egress ds3/e3 or transmit sts-1 signal associated with channel 2. note: these bit-fields are ignored if t he sse interface port is disab led.
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 95 table 39: operation ? ds3/e3/sts-1 clock frequenc y out of range detection ? direction register (address location= 0x0158) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 unused on_egress direction r/o r/o r/o r/o r/o r/o r/o r/w 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 ? 1 unused r/o 0 on_egress_direction r/w frequency out of range detection on egress direction : this read/write bit-field permits the user to configure the ?ds3/e3/sts-1 clock frequency ? out of range detector? to operate in either the ingress or egress direction. 0 ? configures the ds3/e3/sts-1 clock frequency ? out of range detector? to operate on the ds3, e3 or sts-1 clock signals in the ingress direction. 1 ? configures the ds3/e3/sts-1 clock frequency ? out of range detector? to operate on the ds3, e3 or sts-1 clock signals in the egress direction. table 40: operation ? ds3/e3/sts-1clock frequency ? ds3 out of range detection threshold register (address location= 0x015a) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 ds3_out_of_range_detect ion_threshold[7:0] r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 ? 0 ds3_out_of_range_ detection_thr r/w ds3 out of range ? detection threshold[7:0]: these eight read/write bit-fields permit the user to define (in terms of ppm) the frequency difference that must exist between a given ds3 signal (in either the ingress or egress direction) and that of the refclk45 input clock signal; before the XRT94L33 will declare a ?ds3 clock frequency ? out of range? condition.
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 96 table 41: operation ? ds3/e3/sts-1clock frequency ? sts-1/e3 out of range detection threshold registers (address location= 0x015b) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 sts-1/e3_out_of_range_detection_threshold[7:0] r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 ? 0 sts1/e3_out_of_ran ge_detection_thr r/w sts-1/e3 out of range ? detection threshold[7:0]: these eight read/write bit-fields permit the user to define (in terms of ppm) the frequency difference that must exist between a given sts-1 or e3 signal (in either the ingress or egress direction) and that of the refclk51/refclk34 input clock signal; before the XRT94L33 will declare a ?sts-1/e3 clock frequency ? out of range? condition. table 42: operation ? ds3/e3/sts-1 frequency out of range interrupt enable register ? byte 0 (address location=0x015d) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 unused out of range ? channel 2 interrupt enable out of range ? channel 1 interrupt enable out of range ? channel 0 interrupt enable r/o r/o r/o r/o r/o r/w r/w r/w 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7-3 unused r/o 2 out of range ? channel 2 interrupt enable r/w ds3/e3/sts-1 frequency ? out of range ? channel 2 ? interrupt enable: this read/write bit-field permits the user to either enable or disable the ?ds3/e3/sts-1 frequency ? out of range? interrupt for channel 2. if the user enables this interrupt, then the XRT94L33 will generate an interrupt anytime the frequency of the ds3, e3 or sts-1 signal (in the selected direction ? ingre ss or egress) within channel 2, differs from its corresponding reference clock signal (e.g., refclk45, refclk34 or refclk51) by its ?out of range detection threshold? (in terms of ppm) or more. 0 ? disables the ?ds3/e3/sts-1 frequency ? out of range? interrupt for channel 2. 1 ? enables the ?ds3/e3/sts-1 frequency - out of range? interrupt for channel 2. 1 out of range ? channel 1 interrupt enable r/w ds3/e3/sts-1 frequency ? out of range ? channel 1 ? interrupt enable: this read/write bit-field permits the user to either enable or disable the ?ds3/e3/sts-1 fre q uenc y ? out of ran g e? interru p t
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 97 for channel 1. if the user enables this interrupt, then the XRT94L33 will generate an interrupt anytime the frequency of the ds3, e3 or sts-1 signal (in the selected direction ? ingre ss or egress) within channel 1, differs from its corresponding reference clock signal (e.g., refclk45, refclk34 or refclk51) by its ?out of range detection threshold? (in terms of ppm) or more. 0 ? disables the ?ds3/e3/sts-1 frequency ? out of range? interrupt for channel 1. 1 ? enables the ?ds3/e3/sts-1 frequency - out of range? interrupt for channel 1. 0 out of range ? channel 0 interrupt enable r/w ds3/e3/sts-1 frequency ? out of range ? channel 0 ? interrupt enable: this read/write bit-field permits the user to either enable or disable the ?ds3/e3/sts-1 frequency ? out of range? interrupt for channel 0. if the user enables this interrupt, then the XRT94L33 will generate an interrupt anytime the frequency of the ds3, e3 or sts-1 signal (in the selected direction ? ingre ss or egress) within channel 0, differs from its corresponding reference clock signal (e.g., refclk45, refclk34 or refclk51) by its ?out of range detection threshold? (in terms of ppm) or more. 0 ? disables the ?ds3/e3/sts-1 frequency ? out of range? interrupt for channel 0. 1 ? enables the ?ds3/e3/sts-1 frequency - out of range? interrupt for channel 0.
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 98 table 43: operation ? ds3/e3/sts-1 frequency out of range interrupt status register ? byte 0 (address location=0x015f) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 unused out of range ? channel 2 interrupt status out of range ? channel 1 interrupt status out of range ? channel 0 interrupt status r/o r/o r/o r/o r/o rur rur rur 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7-3 unused r/o 2 out of range ? channel 2 interrupt status rur ds3/e3/sts-1 frequency ? out of range ? channel 2 ? interrupt status: this reset-upon-read bit-field indicates whether or not the XRT94L33 has declares the ?ds3/e3/sts-1 frequency ? out of range? interrupt for channel 2, since the last read of this register. 0 ? indicates that the ?ds3/e3/st s-1 frequency - out of range? interrupt for channel 2 has not occu rred since the last read of this register. 1 ? indicates that the ?ds3/e3/ sts-1 frequency ? out of range? interrupt for channel 2 has occurred since the last read of this register. 1 out of range ? channel 1 interrupt status rur ds3/e3/sts-1 frequency ? out of range ? channel 1 ? interrupt status: this reset-upon-read bit-field indicates whether or not the XRT94L33 has declares the ?ds3/e3/sts-1 frequency ? out of range? interrupt for channel 1, since the last read of this register. 0 ? indicates that the ?ds3/e3/st s-1 frequency - out of range? interrupt for channel 1 has not occu rred since the last read of this register. 1 ? indicates that the ?ds3/e3/ sts-1 frequency ? out of range? interrupt for channel 1 has occurred since the last read of this register. 0 out of range ? channel 0 interrupt status rur ds3/e3/sts-1 frequency ? out of range ? channel 0 ? interrupt status: this reset-upon-read bit-field indicates whether or not the XRT94L33 has declares the ?ds3/e3/sts-1 frequency ? out of range? interrupt for channel 0, since the last read of this register. 0 ? indicates that the ?ds3/e3/st s-1 frequency - out of range? interrupt for channel 0 has not occu rred since the last read of this register. 1 ? indicates that the ?ds3/e3/ sts-1 frequency ? out of range? interrupt for channel 0 has occurred since the last read of this register.
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 99 table 44: aps mapping register (address location= 0x0180) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 protection channel[3:0] working channel[3:0] r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7-4 protection channel[3:0] r/w protection channel[3:0]: these register bits are only acti ve if the XRT94L33 device has been configured to operate in either t he atm uni or ppp over the sts-3c mode. these register bits are not active for aggregation applications. 3-0 working channel[3:0] r/w working channel[3:0]: these register bits are only acti ve if the XRT94L33 device has been configured to operate in either t he atm uni or ppp over the sts-3c mode. these register bits are not active for aggregation applications. table 45: aps control register - 1:1 & 1:n protection map (address location= 0x0181) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 aps group enable invoke payload aps protection channel timing source receive payload bypass aps group reset line port in use line aps auto switch enable line aps switch r/w r/w r/w r/w r/w r/o r/w r/w 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 aps group enable r/w aps group enable: this register bit is only active if the XRT94L33 device has been configured to operate in either the atm uni or ppp over sts-3c mode. this register bit is not active for aggregation applications. 6 invoke payload aps r/w invoke payload aps: this register bit is only active if the XRT94L33 device has been configured to operate in either the atm uni or ppp over sts-3c mode. this register bit is not active for aggregation applications. 5 protection channel timing source r/w protection channel timing source: this register bit is only active if the XRT94L33 device has been configured to operate in either the atm uni over ppp over sts-3c mode. this register bit is not active for aggregation applications. 4 receive payload bypass r/w receive payload bypass: this read/write bit-field permits the user to bypass the receive payload of protection channel. 0 ? receive payload is not bypassed. 1 ? receive payload is bypassed.
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 100 3 aps group reset r/w aps group reset: this register bit is only active if the XRT94L33 device has been configured to operate in either the atm uni or ppp over sts-3c mode. this register bit is not active for aggregation applications. 2 line port in use r/o line port in use: this read-only bit-field permits the user to check and identify which receive sts-3/stm-1 pecl interface port is currently being used to receive the incoming sts-3/stm-1 data 0 ? indicates that the primary rece ive sts-3/stm-1 pecl interface port is the ?current port in use?. 1 ? indicates that the redundant receive sts-3/stm-1 pecl interface port is the ?current port in use.? 1 line aps auto switch enable r/w line aps auto switch enable: this read/write bit-field permits the user to configure the XRT94L33 to automatically switch from the ?prima ry? to the ?redundant? port, whenever the primary receive sts-3 toh proc essor block declares the los (loss of signal) defect condition. 0 ? disables the aps auto switch f eature. in this mode, the XRT94L33 will not automatically switch from the ?primary? port to the ?redundant? port, whenever the primary receive sts-3 toh processor block declares the los defect condition. 1 ? enables the aps auto switch featur e. in this mode, the XRT94L33 device will automatically switch from the ?primary? port to the ?redundant? port, whenever the primary sts-3 toh processor block declares the los defect condition. note: this ?aps auto switch? feat ure cannot be used to support ?revertive? switching (e.g., switching from the redundant to the primary port whenever the redundant receive sts-3 toh processor block declares the los defect condition). 0 line aps switch r/w line aps switch: this read/write bit-field permits the user to command a line aps switch (from one port to the other) via software control. 0 ? configures each of the three (3) receive sonet poh processor blocks to accept the incoming sone t traffic from the primary receive sts-3 toh processor block. 1 ? configures each of the three (3) receive sonet poh processor blocks to accept the incoming sonet traffic from the redundant receive sts-3 toh processor block.
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 101 table 46: aps status register (address location= 0x0194) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 unused receive aps parity check enable receive aps parity - odd transmit aps parity check enable transmit aps parity - odd transmit aps parity error detected receive aps parity error detected r/o r/o r/w r/w r/w r/w r/o r/o 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7-6 unused r/o 5 receive aps parity check enable r/w receive aps parity check enable: this register bit is only active if the XRT94L33 device has been configured to operate in the ?atm uni? or ?ppp over sts-3c? mode. this register bit is not active for aggregation applications. 4 receive aps parity ? odd r/w receive aps parity - odd: this register bit is only active if the XRT94L33 device has been configured to operate in the ?atm uni? or ?ppp over sts-3c? mode. this register bit is not active for aggregation applications. 3 transmit aps parity check enable r/w transmit aps parity check enable: this register bit is only active if the XRT94L33 device has been configured to operate in the ?atm uni? or ?ppp over sts-3c? mode. this register bit is not active for aggregation applications. 2 transmit aps parity - odd r/w transmit aps parity - odd: this register bit is only active if the XRT94L33 device has been configured to operate in the ?atm uni? or ?ppp over sts-3c? mode. this register bit is not active for aggregation applications. 1 transmit aps parity error detected r/o transmit aps parity error detected: this register bit is only active if the XRT94L33 device has been configured to operate in the ?atm uni? or ?ppp over sts-3c? mode. this register bit is not active for aggregation applications. 0 receive aps parity error detected r/o receive aps parity error detected: this register bit is only active if the XRT94L33 device has been configured to operate in the ?atm uni ? or ?ppp over sts-3c? mode. this register bit is not active for aggregation applications.
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 102 table 47: aps status register (address location= 0x0196) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 unused aps group fifo overflow status r/o r/o r/o r/o r/o r/o r/o r/o 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7-1 unused r/o 0 aps group fifo overflow status r/o aps group fifo overflow status: this register bit is only acti ve if the XRT94L33 device has been configured to o perate in the ?atm uni? or ?ppp over sts-3c? mode. this register bit is not active for aggregation applications. table 48: aps status register (address location= 0x0197) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 unused aps group fifo underflow status r/o r/o r/o r/o r/o r/o r/o r/o 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7-1 unused r/o 0 aps group fifo underflow status r/o aps group fifo underflow status: this register bit is only active if the XRT94L33 device has been configured to operate in the ?atm uni? or ?ppp over sts-3c? mode. this register bit is not active for aggregation applications.
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 103 table 49: aps interrupt register (address location= 0x0198) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 unused transmit aps parity error interrupt status receive aps parity error interrupt status r/o r/o r/o r/o r/o r/o rur rur 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7-2 unused r/o 1 transmit aps parity error interrupt status rur transmit aps parity error interrupt status: this reset-upon-read bit-field indicates whether or not the transmit aps module has declared a ?transmit aps parity error? interrupt since the last read of this register. 0 ? the ?transmit aps parity e rror? interrupt has not occurred since the last read of this register. 1 - the ?transmit aps parity error? interrupt has occurred since the last read of this register. 7-0 receive aps parity error interrupt status rur receive aps parity error interrupt status: this reset-upon-read bit-field indicates whether or not the receive aps module has declared a ?receive aps parity error? interrupt since the last read of this register. 0 ? the ?receive aps parity erro r? interrupt has not occurred since the last read of this register. 1 - the ?receive aps parity error? interrupt has occurred since the last read of this register
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 104 table 50: aps interrupt register (address location= 0x019a) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 group overflow interrupt status rur rur rur rur rur rur rur rur 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7-0 group overflow interrupt status rur group overflow interrupt status: this reset-upon-read bit-field indicates whether or not group n (0-7) aps protection channel has declared a ?fifo overflow? interrupt since the last read of this register. 0 ? the ?fifo overflow? interrupt has not occurred since the last read of this register. 1 - the ?fifo overflow? interrupt has occurred since the last read of this register. table 51: aps interrupt register (address location= 0x019b) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 group underflow interrupt status rur rur rur rur rur rur rur rur 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7-0 group underflow interrupt status rur group underflow interrupt status: this reset-upon-read bit-field indicates whether or not group n (0- 7) aps protection channel has declared a ?fifo underflow? interrupt since the last read of this register. 0 ? the ?fifo underflow? interrupt has not occurred since the last read of this register. 1 - the ?fifo underflow? interrupt has occurred since the last read of this register.
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 105 table 52: aps interrupt enable register (address location= 0x019c) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 unused transmit aps parity error interrupt enable receive aps parity error interrupt enable r/o r/o r/o r/o r/o r/o r/w r/w 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7-2 unused r/o 1 transmit aps parity error interrupt enable r/w transmit aps parity error interrupt enable: this read/write bit-field permits the user to enable or disable the ?transmit aps parity error? interrupt in transmit aps module 0 ? disables the ?transmit aps parity error? interrupt 1 ? enables the ?transmit aps parity error? interrupt 7-0 receive aps parity error interrupt enable r/w receive aps parity error interrupt enable: this read/write bit-field permits the user to enable or disable the ?receive aps parity error? interrupt in receive aps module 0 ? disables the ?receive ap s parity error? interrupt 1 ? enables the ?receive aps parity error? interrupt table 53: aps interrupt enable register (address location= 0x019e) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 group overflow interrupt enable r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7-0 group overflow interrupt enable r/w group overflow interrupt enable: this read/write bit-field permits the user to enable or disable the ?fifo overflow? interrupt in group n aps protection channel. 0 ? disables ?fifo overflow? interrupt . 1 ? enables ?fifo overflow? interrupt
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 106 table 54: aps interrupt enable register (address location= 0x019f) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 group underflow interrupt enable r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7-0 group underflow interrupt enable r/w group underflow interrupt enable: this read/write bit-field permits the user to enable or disable the ?fifo underflow? interrupt in group n aps protection channel. 0 ? disables ?fifo underflow? interrupt . 1 ? enables ?fifo underflow? interrupt
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 107 1.3 line interface control block the register map for the line interface control block is presented in the table below. additionally, a detailed description of each of the ?line interface c ontrol? block registers is presented below. the line interface control block registers provide the user with ?command and control? over the following functional blocks. ? the transmit sts-3/stm-1 pecl interface block ? the receive sts-3/stm-1 pecl interface block ? the clock synthesizer block in order to provide some orientation for the reader, an illustration of the functional block diagram for the XRT94L33 device, with each of these ?above-mentioned? functional blocks ?highlighted? is presented below in figure 1. figure 1: illustration of the functi onal block diagram of the XRT94L33 (whenever it has been configured to operate in the 3-channel ds3/sts-1 to sts-3 mapper mode, with the line-interface- related blocks ?high-lighted?. ds3/e3 framer block ds3/e3 framer block rx sts-1 pointer justification block rx sts-1 pointer justification block rx sts-1 poh block rx sts-1 poh block tx sts-1 poh block tx sts-1 poh block tx sts-1 pointer justification block tx sts-1 pointer justification block tx sts-1 toh block tx sts-1 toh block rx sts-1 toh block rx sts-1 toh block ds3/e3 jitter attenuator block ds3/e3 jitter attenuator block ds3/e3 mapper block ds3/e3 mapper block tx sonet poh processor block tx sonet poh processor block tx sts-3 toh processor block tx sts-3 toh processor block sts-3 telecom bus block sts-3 telecom bus block tx/rx line i/f block (primary) tx/rx line i/f block (primary) tx/rx line i/f block (aps) tx/rx line i/f block (aps) clock synthesizer block clock synthesizer block channel 1 to channels 2 ? 3 microprocessor interface microprocessor interface jtag test port jtag test port rx sonet poh processor block rx sonet poh processor block rx sts-3 toh processor block rx sts-3 toh processor block from channels 2 ? 3 rx sts-3 toh processor block (primary) rx sts-3 toh processor block (primary)
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 108 1.3.1 l ine i nterface c ontrol r egister table 55: line interface control register ? address map a ddress l ocation r egister n ame d efault v alues 0x0302 receive line interface control register ? byte 1 0x00 0x0303 receive line interface control register ? byte 0 0x00 0x0304 ? 0x0306 reserved 0x00 0x0307 receive line status register 0x00 0x0308 -0x030a reserved 0x00 0x030b receive line interrupt register 0x00 0x030c ? 0x030e reserved 0x00 0x030f receive line interrupt enable register 0x00 0x0310 ? 0x0382 reserved 0x00 0x0383 transmit line interface control register 0x00
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 109 1.3.2 l ine i nterface c ontrol r egister d escription table 56: receive line interface control regi ster ? byte 1 (address location= 0x0302) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 unused sts-3 loop-timing mode split loop back unused remote serial loop back unused analog local loop back enable digital local loop back enable r/w r/w r/w r/o r/w r/o r/w r/w 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 unused r/o 6 sts-3 loop timing mode r/w sts-3 loop-timing mode: this read/write bit-field permits the user to configure the 94l33 to operate in the loop-timing mode. if the user implements this configuration, then the following transmit sts-3-related functional blocks will use the ?recovered clock? (receive sts-3 timing) as its timing source. ? all three (3) transmit sonet poh processor blocks ? the transmit sts-3c poh processor block (if enabled) ? the transmit sts-3 toh processor block ? the transmit sts-3 pecl interface block ? the transmit sts-3 telecom bus interface block. 0 ? configures all of the transmit sts-3 circuitry to operate in the ?local- timing? mode (e.g., the above-mentione d functional blocks will use the clock synthesizer block as its timing source). 1 ? configures the transmit sts-3 circuitry to operate in the ?loop-timing? mode. 5 split loop back r/w split loop-back enable: this read/write bit-field permits the user to configure the 94l33 to operate in the ?split loop-back? mode. if the user implements this configuration, then two ty pes of loop-backs will exist within the chip simultaneously. a. a local loop-back this loop-back path will originate from the transmit sts-3 toh processor block. it will be routed th rough a portion of the ?transceiver circuitry? (through the ?transmit parallel-to-serial converter? block) and then back to the ?receive serial-to-parallel converter? block, before being routed to the receiv e sts-3 toh processor block. b. a remote loop-back this loop-back path will originate from the receive sts-3/stm-1 pecl interface input. it will be r outed through the cdr (clock & data recovery) block; before being rout ed to the transmit sts-3/stm-1 pecl interface output. 0 ? configures the 94l33 to not operate in the split loop-back mode 1 ? configures the 94l33 to oper ate in the split loop-back mode
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 110 4 unused r/w 3 remote serial loop back remote serial loop-back enable: this read/write bit-field permits the user to configure the 94l33 to operate in the ?remote serial loop-back? mode. in this mode, the incoming (received data) will enter the device via the receive sts- 3/stm-1 pecl interface input. this signal will then be processed via the cdr (clock and data recovery) block. at this point, this input signal will proceed via two paths in parallel. in one path, the signal will proceed onto the ?receive serial-to-parallel? converter and then the receive sts-3 toh processor block (and so on). the other path will not proceed through the ?receive serial-to parallel? converter block. instead this signal will proceed on towards the ?transmit sts-3/stm-1 pecl interface output, thereby completing the loop-back path. 0 ? configures the 94l33 to not operat e in the remote serial loop-back mode. 1 ? configures the 94l33 to operate in the remote serial loop-back mode. 2 unused r/o 1 analog local loop back enable r/w analog local loop back: this read/write bit field permits t he user to configure the 94l33 to operate in the ?analog local loop back? mode. if the user implements this configuration, analog local loop back including data and clock recovery will be enabled. 0 ? analog local loop back is disabled 1 ? analog local loop back is enabled 0 digital local loop back enable r/w digital local loop back: this read/write bit field permits t he user to configure the 94l33 to operate in the ?digital local loop back? mode. if the user implements this configuration, digital local l oop back not including data and clock recovery will be enabled. 0 ? digital local loop back is disabled 1 ? digital local loop back is enabled
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 111 table 57: receive line interface control re gister ? byte 0 address location= 0x0303) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 primary receive sts- 3/stm-1 pecl interface module power down redundant receive sts- 3/stm-1 pecl interface module power down force training mode upon los unused r/w r/w r/w r/o r/o r/o r/o r/w 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 primary receive sts-3/stm-1 pecl interface module power down r/w primary receive sts-3/stm-1 pec l interface module power down: this read/write bit field permits the user to power down the primary receive sts-3/stm-1 pecl interface port as described below. 0 ? powers on primary receive sts-3/stm-1 pecl interface block. 1 ? powers down the primary receive sts-3/stm-1 pecl interface block. in this mode, the user will not be able to receive sts-3/stm-1 data via the primary receive pecl interface port. note: if the user wishes to configure the XRT94L33 device to receive sts-3/stm-1 data via the primary re ceive sts-3/stm-1 pecl interface port, then he/she mustset this bit-field to ?0?. 6 redundant receive sts- 3/stm-1 pecl interface module power down r/w redudant receive sts-3/stm-1 pecl interface module power down: this read/write bit field permits the user to power down the redundant receive sts-3/stm-1 pecl interface port as described below. 0 ? powers on the redundant receive sts-3/stm-1 pecl interface block. 1 ? powers down the redundant receive sts-3/stm-1 pecl interface block. in this mode, the user will not be able to receive sts-3/stm-1 data via the redundant receive pecl interface port. note: if the user wishes to configure the XRT94L33 device to receive sts-3/stm-1 data via the redundant receive sts-3/stm-1 pecl interface port, then he/she must set this bit-field to ?0?. 5 force training mode upon los r/w force training mode upon los: this read/write bit field permits the user to configure the receive sts- 3/stm-1 pecl interface ? cdr (clock and data recovery) phase lock loop to stay in training mode as long as the external los is asserted. if the user implements this feature, then the receive sts-3/stm-1 pecl interface block cdr pll will lock onto a clock signal that is ultimately derived from the refclk input pin and remain locked onto this signal for the duration that the receive sts- 3/stm-1 pecl interface block is declaring the los_detect condition. 0 ? receive line interface pll will not stay in training mode 1 ? receive line interface pll will stay in training mode 4-0 unused r/o
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 112 table 58: receive line interface status register (address location= 0x0307) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 unused clock lock status loss of signal status redundant receiver clock lock status redundant receiver loss of signal status r/w r/o r/o r/o rur rur rur rur 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7-4 unused r/o 3 clock lock status rur clock lock status: this reset-upon-read bit field indicates whether or not the clock lock status is detected by transceiver 0 ? indicates clock lock is not detected by transceiver 1 ? indicates clock lock is detected by transceiver 2 loss of signal status rur loss of signal status: this reset-upon-read bit field indicates whether or not the loss of signal status is detected by transceiver 0 ? indicates loss of signal is not detected by transceiver 1 ? indicates loss of signal is detected by transceiver 1 redundant receiver clock lock status rur redundant receiver clock lock status: this reset-upon-read bit field indicates whether or not the clock lock status is detected by redundant receiver 0 ? indicates clock lock is not detected by redundant receiver 1 ? indicates clock lock is detected by redundant receiver 0 redundant receiver loss of signal status rur redundant receiver loss of signal status: this reset-upon-read bit field indicates whether or not the loss of signal status is detected by redundant receiver 0 ? indicates loss of signal is no t detected by redundant receiver 1 ? indicates loss of signal is detected by redundant receiver
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 113 table 59: receive line interface interrupt register (address location= 0x030b) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 unused clock lock interrupt loss of signal interrupt redundant receiver clock lock interrupt redundant receiver loss of signal interrupt r/w r/o r/o r/o rur rur r/o r/o 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7-4 unused r/o 3 clock lock interrupt rur clock lock interrupt: this reset-upon-read bit field indicates whether or not a clock lock interrupt has occurred. a clock lock interrupt occurs when the signal ?clock lock status? (address location: 0x 0307) makes a ?0? to ?1? or ?1? to ?0? transition. 0 ? indicates clock lock interrupt is not declared. 1 ? indicates clock lock is declared 2 loss of signal interrupt rur loss of signal interrupt: this reset-upon-read bit field indicates whether or not a loss of signal interrupt has occurred. a clock lock interrupt occurs when the signal ?loss of signal status? (address location: 0x0307) makes a ?0? to ?1? or ?1? to ?0? transition. 0 ? indicates a loss of signal interrupt is not declared. 1 ? indicates a loss of signal is declared 1 redundant receiver clock lock interrupt rur redundant receiver clock lock interrupt: this reset-upon-read bit field indicates whether or not a clock lock interrupt has occurred in the redundant receiver block. a clock lock interrupt occurs when the signal ?clock lock status? (address location: 0x0307) makes a ?0? to ?1? or ?1? to ?0? transition. 0 ? indicates clock lock interrupt is not declared. 1 ? indicates clock lock is declared 0 redundant receiver loss of signal interrupt rur redundant receiver loss of signal interrupt: this reset-upon-read bit field indicates whether or not a loss of signal interrupt has occurred in the redundant receiver block. a clock lock interrupt occurs when the signal ?loss of signal status? (address location: 0x0307) makes a ?0? to ?1? or ?1? to ?0? transition. 0 ? indicates a loss of signal interrupt is not declared. 1 ? indicates a loss of signal is declared
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 114 table 60: receive line interface interrupt register (address location= 0x030f) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 unused clock lock interrupt enable loss of signal interrupt enable redundant receiver clock lock interrupt enable redundant receiver loss of signal interrupt enable r/w r/o r/o r/o r/w r/w r/w r/w 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7-4 unused r/o 3 clock lock interrupt enable r/w clock lock interrupt enable: this read/write bit field disables or enables the clock lock interrupt. 0 ? disables clock lock interrupt 1 ? enables clock lock interrupt 2 loss of signal interrupt r/w loss of signal interrupt enable: this read/write bit field disables or enables the loss of signal interrupt. 0 ? disables loss of signal interrupt 1 ? enables loss of signal interrupt 1 redundant receiver clock lock interrupt enable r/w redundant receiver clock lock interrupt enable: this read/write bit field disables or enables the clock lock interrupt for the redundant receiver block. 0 ? disables clock lock interrupt 1 ? enables clock lock interrupt 0 redundant receiver loss of signal interrupt r/w redundant receiver loss of signal interrupt enable: this read/write bit field disables or enables the loss of signal interrupt for the redundant receiver block. 0 ? disables loss of signal interrupt 1 ? enables loss of signal interrupt
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 115 table 61: transmit line interface control register (address location= 0x0383) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 primary transmit sts-3/stm- 1 pecl interface enable transmit clock enable clock synthesizer block as timing source redundant transmit sts-3/stm- 1 pecl interface block enable unused unused refclksel[1:0] r/w r/w r/w r/w r/o r/o r/w r/w 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 primary transmit sts-3/stm-1 pecl interface enable r/w primary transmit sts-3/st m-1 pecl interface enable: this read/write bit field permits the user to enable or disable the transmit sts-3/stm-1 pecl interface out put drivers as described below. 0 ? disables the transmit sts-3/stm-1 pecl interface output drivers. 1 ? enables the transmit sts-3/stm-1 pecl interface output drivers. note: the user must set this bit-field to ?1? in order to transmit any traffic via the transmit sts-3/stm-1 pecl interface output. 6 transmit clock enable r/w transmit clock enable: this read/write bit field permits the user to enable or disable the transmitter clock output. 0 ? disables transmitter clock output 1 ? enables transmitter clock output 5 clock synthesizer as timing source r/w clock synthesizer as timing source: this read/write bit field permits t he user to select either the clock synthesizer block or the signal appli ed at the refttl input as the source of the transmit 19.44mhz clock. 0 ? this setting configures the ?trans mit sonet? circuitry to by-pass the clock synthesizer block and to directly use the 19.44mhz clock signal (that is provided to the refttl input pi n) as its timing source. in this case, the ?clock synthesizer? block is by-passed. 1 ? this setting configures the ?transmit sonet? circuitry to use the output of the clock synthesizer block as its timing source. note: if the user opts to by-pass the clock synthesizer (by setting this register bit to ?0?) then he/she must apply a 19.44mhz clock signal to the refttl input pin. 4 redundant transmit sts- 3/stm-1 pecl interface enable r/w redundant transmit sts-3/stm-1 pecl interface enable: this read/write bit field permits the user to enable or disable the redundant transmit sts-3/stm-1 pecl interface output pads. if the user enables the ?redundant transmit sts-3/stm-1 pecl interface? block, then it will begin to transmit the exact same data as is the ?primary transmit sts-3/stm-1 pecl interface? block. 0 ? disables the redundant transmit sts-3/stm-1 pecl interface block 1 ? enables the redundant transmit sts-3/stm-1 pecl interface block
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 116 note: if the user wishes to use t he ?line aps? features within the XRT94L33 device, then he/she must enable the ?redundant transmit sts-3/stm-1pecl interface block. 3 unused r/w serial loopback: this read/write bit field permits the user to enable or disable serial loopback. 0 ? disables serial loopback 1 ? enables serial loopback 2 unused r/o 1-0 clock synthesizer block frequency select[1:0] r/w clock synthesizer block frequency select[1:0]: this read/write bit field permits the user to select the desired reference clock speed as follows: 00 = 19.44 mhz 01 = 38.88 mhz 10 = 51.85 mhz 11 = 77.76 mhz
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 117 1.4 receive sts-3 toh processor block the register map for the receive sts- 3 toh processor block is presented in the table below. additionally, a detailed description of each of the ?receive sts-3 toh processor? block registers is presented below. in order to provide some orientation for the reader, an illustration of the functional block diagram for the XRT94L33, with the ?receive sts-3 toh processor bl ock ?highlighted? is presented below in figure 2 figure 2: illustration of the functi onal block diagram of the XRT94L33 (whenever it has been configured to operate in the 3-channel ds3/sts-1 to sts-3 mapper mode), with the receive sts-3 toh processor block ?high-lighted?. ds3/e3 framer block ds3/e3 framer block rx sts-1 pointer justification block rx sts-1 pointer justification block rx sts-1 poh block rx sts-1 poh block tx sts-1 poh block tx sts-1 poh block tx sts-1 pointer justification block tx sts-1 pointer justification block tx sts-1 toh block tx sts-1 toh block rx sts-1 toh block rx sts-1 toh block ds3/e3 jitter attenuator block ds3/e3 jitter attenuator block ds3/e3 mapper block ds3/e3 mapper block tx sonet poh processor block tx sonet poh processor block tx sts-3 toh processor block tx sts-3 toh processor block sts-3 telecom bus block sts-3 telecom bus block tx/rx line i/f block (primary) tx/rx line i/f block (primary) tx/rx line i/f block (aps) tx/rx line i/f block (aps) clock synthesizer block clock synthesizer block channel 1 to channels 2 ? 3 microprocessor interface microprocessor interface jtag test port jtag test port rx sonet poh processor block rx sonet poh processor block rx sts-3 toh processor block rx sts-3 toh processor block from channels 2 ? 3 rx sts-3 toh processor block (primary) rx sts-3 toh processor block (primary)
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 118 receive sts-3 toh proc essor block registers table 62: receive sts-3 toh processor block control register ? address map a ddress l ocation r egister n ame d efault v alues 0x1000 ? 0x1102 reserved 0x1103 receive sts-3 transport control register ? byte 0 0x00 0x1104 ? 0x1105 reserved 0x00 0x1106 receive sts-3 transport status register ? byte 1 0x00 0x1107 receive sts-3 transport status register ? byte 0 0x02 0x1108 reserved 0x00 0x1109 receive sts-3 transport interrupt status register ? byte 2 0x00 0x110a receive sts-3 transport interrupt status register ? byte 1 0x00 0x110b receive sts-3 transport interrupt status register ? byte 0 0x00 0x110c reserved 0x00 0x110d receive sts-3 transport interrupt enable register ? byte 2 0x00 0x110e receive sts-3 transport interrupt enable register ? byte 1 0x00 0x110f receive sts-3 transport interrupt enable register ? byte 0 0x00 0x1110 receive sts-3 transport - b1 byte error count register ? byte 3 0x00 0x1111 receive sts-3 transport - b1 byte error count register ? byte 2 0x00 0x1112 receive sts-3 transport - b1 byte error count register ? byte 1 0x00 0x1113 receive sts-3 transport - b1 byte error count register ? byte 0 0x00 0x1114 receive sts-3 transport - b2 byte error count register ? byte 3 0x00 0x1115 receive sts-3 transport - b2 byte error count register ? byte 2 0x00 0x1116 receive sts-3 transport - b2 byte error count register ? byte 1 0x00 0x1117 receive sts-3 transport - b2 byte error count register ? byte 0 0x00 0x1118 receive sts-3 transport - rei-l event count register ? byte 3 0x00 0x1119 receive sts-3 transport - rei-l event count register ? byte 2 0x00 0x111a receive sts-3 transport - rei-l event count register ? byte 1 0x00 0x111b receive sts-3 transport - rei-l event count register ? byte 0 0x00 0x111e reserved 0x00 0x111f receive sts-3 transport k1 byte value register 0x00 0x1120 ? 0x1122 reserved 0x00 0x1123 receive sts-3 transport k2 byte value register 0x00 0x1124 ? 0x1126 reserved 0x00 0x1127 receive sts-3 transport s1 byte value register 0x00
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 119 a ddress l ocation r egister n ame d efault v alues 0x1128 ? 0x112a reserved 0x00 0x112b receive sts-3 transport ? in-sync threshold value register 0x00 0x112c, 0x112d reserved 0x00 0x112e receive sts-3 transport ? los threshold value ? msb 0xff 0x112f receive sts-3 transport ? los threshold value ? lsb 0xff 0x1130 reserved 0x00 0x1131 receive sts-3 transport ? sf set monitor interval ? byte 2 0x00 0x1132 receive sts-3 transport ? sf set monitor interval ? byte 1 0x00 0x1133 receive sts-3 transport ? sf set monitor interval ? byte 0 0x00 0x1134 ? 0x1135 reserved 0x00 0x1136 receive sts-3 transport ? sf set threshold ? byte 1 0x00 0x1137 receive sts-3 transport ? sf set threshold ? byte 0 0x00 0x1138, 0x1139 reserved 0x00 0x113a receive sts-3 transport ? sf clear threshold ? byte 1 0x00 0x113b receive sts-3 transport ? sf clear threshold ? byte 0 0x00 0x113c reserved 0x00 0x113d receive sts-3 transport ? sd set monitor interval ? byte 2 0x00 0x113e receive sts-3 transport ? sd set monitor interval ? byte 1 0x00 0x113f receive sts-3 transport ? sd set monitor interval ? byte 0 0x00 0x1140, 0x1141 reserved 0x00 0x1142 receive sts-3 transport ? sd set threshold ? byte 1 0x00 0x1143 receive sts-3 transport ? sd set threshold ? byte 0 0x00 0x1144, 0x1145 reserved 0x00 0x1146 receive sts-3 transport ? sd clear threshold ? byte 1 0x00 0x1147 receive sts-3 transport ? sd clear threshold ? byte 0 0x00 0x1148 ? 0x114a reserved 0x00 0x114b receive sts-3 transport ? force sef condition 0x00 0x114c, 0x114e reserved 0x00 0x114f receive sts-3 transport ? receive section trace message buffer control register 0x00 0x1150, 0x1151 reserved 0x00 0x1152 receive sts-3 transport ? sd burst error count tolerance ? byte 1 0x00 0x1153 receive sts-3 transport ? sd burst error count tolerance ? byte 0 0x00
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 120 a ddress l ocation r egister n ame d efault v alues 0x1154, 0x1155 reserved 0x00 0x1156 receive sts-3 transport ? sf burst error count tolerance ? byte 1 0x00 0x1157 receive sts-3 transport ? sf burst error count tolerance ? byte 0 0x00 0x1158 reserved 0x00 0x1159 receive sts-3 transport ? receive sd clear monitor interval ? byte 2 0xff 0x115a receive sts-3 transport ? receive sd clear monitor interval ? byte 1 0xff 0x115b receive sts-3 transport ? receive sd clear monitor interval ? byte 0 0xff 0x115c reserved 0x00 0x115d receive sts-3 transport ? receive sf clear monitor interval ? byte 2 0xff 0x115e receive sts-3 transport ? receive sf clear monitor interval ? byte 1 0xff 0x115f receive sts-3 transport ? receive sf clear monitor ? byte 0 0xff 0x1160 ? 0x1162 reserved 0x00 0x1163 receive sts-3 transport ? auto ais control register 0x00 0x1164 ? 0x1166 reserved 0x00 0x1167 receive sts-3 transport ? serial port control register 0x00 0x1168 ? 0x116a reserved 0x00 0x116b receive sts-3 transport ? auto ais (in downstream sts-1s) control register 0x000 0x116c ? 0x1179 reserved 0x117a receive sts-3 transport ? toh capture indirect address 0x00 0x117b receive sts-3 transport ? toh capture indirect address 0x00 0x117c receive sts-3 transport ? toh capture indirect data 0x00 0x117d receive sts-3 transport ? toh capture indirect data 0x00 0x117e receive sts-3 transport ? toh capture indirect data 0x00 0x117f receive sts-3 transport ? toh capture indirect data 0x00 0x1180 ? 0x11ff reserved 0x00
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 121 1.4.1 receive sts-3 toh processo r block register description table 63: receive sts-3 transport control register ? byte 0 (address location= 0x1103) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 sts-n oh extract sf defect condition detect enable sd defect condition detect enable descramble disable sdh/ sonet* rei-l error type b2 error type b1 error type r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 sts-n oh extract r/w sts-n overhead extract (revision c silicon only): this read/write bit-field permits t he user to configure the rxtoh output port to output the toh for all lower-tri butary sts-1s within the incoming sts-3 signal. 0 ? disables this feature. in this mode, the rxtoh output port will only output the toh for the first sts-1 within the incoming sts-3 signal. 1 ? enables this feature. 6 sf defect condition detect enable r/w signal failure (sf) defect condition detect enable: this read/write bit-field permits the user to enable or disable sf defect declaration and clearance by the receive sts-3 toh processor block, as described below. 0 ? configures the receive sts-3 toh processor block to not declare nor clear the sf defect condition per the ?user-specified? sf defect declaration and clearance criteria. 1 ? configures the receive sts-3 toh processor block to declare and clear the sf defect condition per the ?user-specified? sf defect declaration and clearance? criteria. note: the user must set this bit-field to ?1? in order to permit the receive sts-3 toh processor block to declare and clear the sf defect condition. 5 sd defect condition detect enable r/w signal degrade (sd) defect condition detect enable: this read/write bit-field permits the user to enable or disable sd declaration and clearance by the receive sts-3 toh processor block as described below. 0 ? configures the receive sts-3 toh processor blolck to not declare nor clear the sd defect condition per the ?user-specified? sd defect declaration and clearance criteria.. 1 ? configures the receive sts-3 toh processor block to declare and clear the sd defect condition per the ?user-specified sd defect declaration and clearance? critieria. note: the user must set this bit-field to ?1? in order to permit the receive sts-3 toh processor block to declare and clear the sd defect condition. 4 descramble disable r/w de-scramble disable: this read/write bit-field permits the user to either enable or disable de- scrambling by the receive sts-3 toh processor block. 0 ? de-scrambling is enabled.
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 122 1 ? de-scrambling is disabled. 3 sdh/sonet* r/w sdh/sonet select: this read/write bit-field permits the user to configure the XRT94L33 device to operate in either the sonet or sdh mode. 0 ? configures the XRT94L33 device to operate in the sonet mode. 1 ? configures the XRT94L33 devic e to operate in the sdh mode. 2 rei-l error type r/w rei-l (line ? remote erro r indicator) error type: this read/write bit-field permits t he user to specify how the receive sts-3 toh processor block will count (or tally) rei-l events, for performance monitoring purposes. t he user can configure the receive sts-3 toh processor block to increment rei-l events on etiher a ?per-bit? or ?per-frame? basis. if the user configures the receive sts-3 toh processor block to increment rei-l events on a ?per-bit? basis, then it will increment the ?receive sts-3 transpor t rei-l event count? register by the contents within the m1 byte of the incoming sts-3 data-stream. if the user configures the receive sts-3 toh processor block to increment rei-l events on a ?per-frame? basis, then it will increment the ?receive sts-3 transport rei-l event count? register each time it receives an sts-3 frame, in which the m1 byte is set to a ?non-zero? value. 0 ? configures the receive sts-3 toh processor block to count or tally rei-l events on a per-bit basis. 1 ? configures the receive sts-3 toh processor block to count or tally rei-l events on a per-frame basis. 1 b2 error type r/w b2 error type: this read/write bit-field permits t he user to specify how the ?receive sts-3 toh processor block will count (or tally) b2 byte errors, for performance monitoring purposes. t he user can configure the receive sts-3 toh processor block to increment b2 byte errors on either a ?per- bit? or a ?per-frame? basis. if the us er configures the receive sts-3 toh processor block to increment b2 byte errors on a ?per-bit? basis, then it will increment the receive sts-3 transport - b2 byte error count? register by the number of bits (within each of the thr ee b2 byte values) that is in error. if the user configures the receive sts-3 toh processor block to increment b2 byte errors on a ?per-frame? basis, then it will increment the ?receive sts-3 transport - b2 byte error count? register, each time it receives an sts-3 frame that contains at least one erred b2 byte. 0 ? configures the receive sts-3 toh processor block to count b2 byte errors on a ?per-bit? basis. 1 ? configures the receive sts-3 toh processor block to count b2 byte errors on a ?per-frame? basis. 0 b1 error type r/w b1 error type: this read/write bit-field permits t he user to specify how the receive sts-3 toh processor block will count (or tally) b1 byte errors, for performance monitoring purposes. t he user can configure the receive sts-3 toh processor block to increment b1 byte errors on either a ?per- bit? or ?per-frame? basis. if the user configures the receive sts-3 toh processor block to increment b1 byte errors on a ?per-bit? basis, then it will increment the ?receive transport b1 error count? register by the number of bits (within the b1 byte value) that is in error. if the user configures the receive sts-3 toh processor block to increment b1 b y te errors on a ? p e r -frame? basis, then it will increment the
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 123 ?receive sts-3 transport - b1 byte error count? register each time it receives an sts-3 frame that contains an erred b1 byte. 0 ? configures the receive sts-3 toh processor block to count b1 byte errors on a ?per-bit? basis. 1 ? configures the receive sts-3 toh processor block to count b1 byte errors on a ?per-frame? basis.
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 124 table 64: receive sts-3 transport status register ? byte 1 (address location= 0x1106) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 unused section trace message mismatch defect declared section trace message unstable defect declared ais-l defect declared r/o r/o r/o r/o r/o r/o r/o r/o 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 ? 3 unused r/o 2 section trace message mismatch defect declared r/o section trace message mismatch defect declared: this read-only bit-field indicates w hether or not the receive sts-3 toh processor block is currently declaring the section trace mismatch defect condition within the incoming sts-3 data-stream. the receive sts-3 toh processor block will declare the section trace message mismatch defect condition, whenever it accepts a section trace message (via the j0 byte, within the incoming sts-3 data-stream ) that differs from the ?expected section trace message?. 0 ? indicates that the receive sts-3 toh processor block is not currently declaring the section trace message mismatch defect condition. 1 ? indicates that the receive sts-3 toh processor block is currently declaring the section trace message mismatch defect condition. 1 section trace message unstable defect declared r/o section trace message unstable defect declared: this read-only bit-field indicates w hether or not the receive sts-3 toh processor block is currently declaring the section trace message unstable defect condition. the receive sts-3 toh processor block will declare the section trace message unstable defect condition, whenever the ?section trace message unstable? counter reache s the value 8. the receive sts-3 toh processor block will increment the ?section trace message unstable? counter each time that it receives a se ction trace message that differs from the previously received section trace message?. the receive sts-3 toh processor block will clear the ?section trace message unstable? counter to ?0? whenever it has received a given section trace message 3 (or 5) consecutive times. note: the receive sts-3 toh processor block will also clear the ?section trace message unstable? defect condition? once it has received a given section trace message 3 (or 5) consecutive times. 0 ? indicates that the receive sts-3 toh processor block is not currently declaring the section trace message unstable defect condition. 1 ? indicates that the receive sts-3 toh processor block is currently declaring the section trace message unstable defect condition. 0 ais-l defect declared r/o ais-l defect declared: this read-only bit-field indicates w hether or not the receive sts-3 toh processor block is currently declaring the ais-l (line ais) defect condition within the incoming sts-3 data stream. the receive sts-3 toh processor block will declare the ais-l defect condition within the incoming sts-3 data stream if bits 6, 7 and 8 (e .g., the least significant bits, within the k2 b y te ) are set to the value ? [ 1, 1, 1 ] ? for five consecutive sts-3
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 125 frames. 0 ? indicates that the receive sts-3 toh processor block is not currently declaring the ais-l defect condition. 1 ? indicates that the receive sts-3 toh processor block currently declaring the ais-l defect condition.
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 126 table 65: receive sts-3 transport status register ? byte 0 (address location= 0x1107) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 rdi-l defect declared s1 byte unstable defect declared k1, k2 byte unstable defect declared sf defect declared sd defect declared lof defect declared sef defect declared los defect declared r/o r/o r/o r/o r/o r/o r/o r/o 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 rdi-l defect declared r/o rdi-l (line remote defect indicator) defect declared: this read-only bit-field indicates whether or not the receive sts-3 toh processor block is currently declaring the rdi-l defect condition within the incoming sts-3 signal. the receive sts-3 toh processor block will declare the rdi-l defect condition whenever it det ermines that bits 6, 7 and 8 (e.g., the three least significant bits) of the k2 byte contains the ?1, 1, 0? pattern in 5 consecutive incoming sts-3 frames. 0 ? indicates that the receive sts-3 toh processor block is not currently declaring the rdi-l defect condition. 1 ? indicates that the receive sts-3 toh processor block is currently declaring the rdi-l defect condition. 6 s1 byte unstable defect declared r/o s1 byte unstable defect declared: this read-only bit-field indicates whether or not the receive sts-3 toh processor block is currently declaring the ?s1 byte unstable? defect condition. the receive sts-3 toh processor block will declare the ?s1 byte unstable? defect condition whenever the ?s1 byte unstable counter? reaches the value 32. the receive sts-3 toh processor block will increment the ?s1 byte unstable counter? each time that it receives an sts- 3 frame that contains an s1 byte that differs from the previously received s1 byte. the receive sts-3 toh processor block will clear the contents of the ?s1 byte unstable counter? to ?0? whenever it receives the same s1 byte for 8 consecutive sts-3 frames. 0 ? indicates that the receive sts-3 toh processor block is not currently declaring the ?s1 byte unstable defect condition. 1 ? indicates that the receive sts-3 toh processor block is currently declaring ?s1 byte unstable defect condition. 5 k1, k2 byte unstable defect declared r/o k1, k2 byte unstable defect declared: this read-only bit-field indicates whether or not the receive sts-3 toh processor block is currently declaring the ?k1, k2 byte unstable? defect condition. the receive sts-3 toh processor block will declare the ?k1, k2 byte unstable? defect condition whenever it fails to receive the same set of k1, k2 bytes, in 12 consecutive sts-3 fram es. the receive sts-3 toh processor block will clear the ?k1, k2 byte unstab le? defect condition whenever it receives a given set of k1, k2 byte values within three consecutive sts-3 frames. 0 ? indicates that the receive sts-3 toh processor block is not currently declaring the k1, k2 byte unstable defect condition. 1 ? indicates that the receive sts-3 toh processor block is currently declaring the k1, k2 byte unstable defect condition. 4 sf defect declared r/o sf (signal failure) defect declared: this read-only bit-field indicates whether or not the receive sts-3 toh
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 127 processor block is currently declaring the sf defect condition. the receive sts-3 toh processor block will declare t he sf defect condition anytime it has determined that the number of b2 byte errors (measured over a user-selected period of time) exceeds a certain ?user-s pecified b2 byte error? threshold. 0 ? indicates that the receive sts-3 toh processor block is not currently declaring the sf defect condition. this bit is set to ?0? when the number of b2 byte errors (accumulated over a given interval of time) does not exceed t he ?sf defect declaration? threshold. 1 ? indicates that the receive sts-3 toh processor block is currently declaring the sf defect condition. this bit is set to ?1? when the number of b2 byte errors (accumulated over a given interval of time) does exceed the ?sf defect declaration? threshold. 3 sd defect declared r/o sd (signal degrade) defect declared: this read-only bit-field indicates whether or not the receive sts-3 toh processor block is currently declaring the sd defect condition. the receive sts-3 toh processor block will declare the sd defect condition anytime it has determined that the number of b2 byte errors (measured over a user-selected period of time) exceeds a certain ?user-s pecified b2 byte error? threshold. 0 ? indicates that the receive sts-3 toh processor block is not currently declaring the sd defect condition. this bit is set to ?0? when the number of b2 byte errors (accumulated over a given interval of time) does not exceed t he ?sd defect declaration? threshold. 1 ? indicates that the receive sts-3 toh processor block is currently declaring the sd defect condition. this bit is set to ?1? when the number of b2 byte errors (accumulated over a given interval of time) does exceed the ?sd defect declaration? threshold. 2 lof defect declared r/o lof (loss of frame) defect declared: this read-only bit-field indicates whether or not the receive sts-3 toh processor block is currently declaring the lof defect condition. the receive sts-3 toh processor block will declare th e lof defect condition, if it has been declaring the sef (severely errored frame) defect condition for 3ms (or 24 sonet frame periods). 0 ? indicates that the receive sts-3 toh processor block is not currently declaring the lof defect condition. 1 ? indicates that the receive sts-3 toh processor block is currently declaring the lof defect condition. 1 sef defect declared r/o sef (severely errored frame) defect declared: this read-only bit-field indicates whether or not the receive sts-3 toh processor block is currently declaring the sef defect condition. the receive sts-3 toh processor block will declare the sef defect condition if the ?sef declaration criteria?; per the settings of the frpatout[1:0] bits, within the receive sts-3 transport ? in-sync threshold value register (address location= 0x112b) are met. 0 ? indicates that the receive sts-3 toh processor block is not currently declaring the sef defect condition. 1 ? indicates that the receive sts-3 toh processor block is currently declaring the sef defect condition. 0 los defect declared r/o los (loss of signal) defect declared: this read-only bit-field indicates whether or not the receive sts-3 toh processor block is currently declaring the los (loss of signal) defect condition. the receive sts-3 toh processor block wi ll declare the los defect condition if
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 128 it detects ?los_threshold[15:0]? consecut ive ?all zero? bytes in the incoming sts-3 data stream. note: the user can set the ?los_threshold[15:0]? value by writing the appropriate data into the ?receive sts-3 transport ? los threshold value? register (address location= 0x112e and 0x112f). 0 ? indicates that the receive sts-3 toh processor block is not currently declaring the los defect condition. 1 ? indicates that the receive sts-3 toh processor block is currently declaring the los defect condition.
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 129 table 66: receive sts-3 transport interrupt status register ? byte 2 (address location= 0x1109) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 unused change of ais-l defect condition interrupt status change of rdi-l defect condition interrupt status r/o r/o r/o r/o r/o r/o rur rur 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 - 2 unused r/o 1 change of ais-l defect condition interrupt status rur change of ais-l (line ais) defect condition interrupt status: this reset-upon-read bit-field indicates whether or not the ?change of ais-l defect condition? interrupt has occurred since the last read of this register. the receive sts-3 toh processor block will generate this interrupt in response to either of the following occurrences. ? whenever the receive sts-3 toh processor block declares the ais-l defect condition. ? whenever the receive sts-3 toh processor block clears the ais-l defect condition. 0 ? indicates that the ?change of ais- l defect condition? interrupt has not occurred since the last read of this register. 1 ? indicates that the ?change of ai s-l defect condition? interrupt has occurred since the last read of this register. note: the user can determine if the receive sts-3 toh processor block is currently declaring the ais-l defect condition by reading the contents of bit 0 (ais-l defect declared) within the ?receive sts- 3 transport status register ? byte 1? (address location = 0x1106). 0 change of rdi-l defect condition interrupt status rur change of rdi-l (line - remote de fect indicator) defect condition interrupt status: this reset-upon-read bit-field indicates whether or not the ?change of rdi-l defect condition? interrupt has occurred since the last read of this register. the receive sts-3 toh processor block will generate this interrupt in response to either of the following occurrences. ? whenever the receive sts-3 toh processor block declares the rdi-l defect condition. ? whenever the receive sts-3 toh processor block clears the rdi-l defect condition. 0 ? indicate that the ?change of rdi-l defect condition? interrupt has not occurred since the last read of this register. 1 ? indicates that the ?c hange of rdi-l defect condition? interrupt has occurred since the last read of this register. note: the user can determine if the receive sts-3 toh processor block is currently declaring the rdi-l defect condition by reading out the state of bit 7 (rdi-l defect decl ared) within the ?receive sts-3 transport status register ? byte 0? (address location = 0x1107). i
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 130 table 67: receive sts-3 transport interrupt status register ? byte 1 (address location = 0x110a) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 new s1 byte interrupt status change in s1 byte unstable defect condition interrupt status change in section trace message unstable defect condition interrupt status new section trace message interrupt status change in section trace message mismatch defect condition interrupt status receive toh cap done interrupt status change in k1, k2 bytes unstable defect condition interrupt status new k1k2 byte value interrupt status rur rur rur rur rur rur rur rur 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 new s1 byte value interrupt status rur new s1 byte value interrupt status: this reset-upon-read bit-field indicates whether or not the ?new s1 byte value? interrupt has occurred since the last read of this register. the receive sts-3 toh processor block will generate the ?new s1 byte value? interrupt, anytime it has ?accepted? a new s1 byte, from the incoming sts-3 data-stream. 0 ? indicates that the ?new s1 byte value? interrupt has not occurred since the last read of this register. 1 ? indicates that the ?new s1 byte value? interrupt has occurred since the last read of this register. note: the user can obtain the value for th is most recently accepted value of the s1 byte by reading the ?receive sts-3 transport s1 byte value? register (address location= 0x1127). 6 change in s1 byte unstable defect condition interrupt status rur change in s1 byte unstable defect condition interrupt status: this reset-upon-read bit-field indicates whether or not the ?change in s1 byte unstable defect condition? interrupt has occurred since the last read of this register. the receive sts-3 toh processor block will generate this interrupt in response to either of the following events. ? whenever the receive sts-3 toh processor block declares the ?s1 byte unstable? defect condition. ? whenever the receive sts-3 toh processor block clears the ?s1 byte unstable? defect condition. 0 ? indicates that the ?change in s1 byte unstable defect condition? interrupt has not occurred since the last read of this register. 1 ? indicates that the ?change in s1 byte unstable defect condition? interrupt has occurred since the last read of this register. note: the user can determine if the receive sts-3 toh processor block is currently declaring the ?s1 byte unstable? defect condition by reading the contents of bit 6 (s1 byte unstable condition defect declared) within the ?receive st s-3 transport status register ? byte 0? (address location = 0x1107). 5 change in section trace message unstable defect condition int errupt status rur change in section trace message unstable defect condition interrupt status: this reset-upon-read bit-field indicates whether or not the ?change in section trace message unstable? defect condition interrupt has occurred since the last read of this re g ister. the receive sts-3 toh processor
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 131 interrupt status block will generate this interrupt in response to either of the following events. ? whenever the receive sts-3 toh processor block declares the ?section trace message unstable? defect condition. ? whenever the receive sts-3 toh processsor block clears the ?section trace message unstable? defect condition. 0 ? indicates that the ?change in section trace message unstable defect? condition interrupt has not occurred si nce the last read of this register. 1 ? indicates that the ?change in section trace message unstable defect? condition interrupt has occurred sinc e the last read of this register. 4 new section trace message interrupt status rur new section trace message interrupt status: this reset-upon-read bit-field indicates whether or not the ?new section trace message? interrupt has occurred since the last read of this register. the receive sts-3 toh processor block will generate this interrupt anytime it has accepted a new ?section trace? message within the incoming sts-3 data-stream. 0 ? indicates that the ?new secti on trace message interrupt? has not occurred since the last read of this register. 1 ? indicates that the ?new section trace message interrupt? has occurred since the last read of this register. note: the user can read out the contents of the ?receive section trace message buffer?, which is located at address location 0x1300 through 0x133f. 3 change in section trace message mismatch defect condition interrupt status rur change in section trace message mi smatch defect condition interrupt status: this reset-upon-read bit-field indicates whether or not the ?change in section trace message mism atch defect condition? interrupt has occurred since the last read of this register . the receive sts-3 toh processor block will generate this inte rrupt in response to either of the following events. ? whenever the receive sts-3 toh processor block declares the ?section trace message mismatch? defect condition. ? whenever the receive sts-3 toh processor block clears the ?section trace message mismatch? defect condition. 0 ? indicates that the ?change in se ction trace message mismatch defect condition? interrupt has not occurred si nce the last read of this register. 1 ? indicates that the ?change in se ction trace message mismatch defect condition? interrupt has occurred sinc e the last read of this register. note: the user can determine whether the receive sts-3 toh processor block is currently declaring the ?section trace message mismatch? defect condition by read ing the state of bit 2 (section trace message mismatch defect declared) within the ?receive sts-3 transport status register ? byte 1 (address location = 0x1106). 2 receive toh cap done interrupt status rur receive toh capture done ? interrupt status: this reset-upon-read bit-field indicates whether the ?receive toh data capture? interrupt has occurred sinc e the last read of this register. if this interrupt is enabled, then the receive sts-3 toh processor block will generate an interrupt anytime it has captured the last toh byte into the capture buffer. note: once the toh (of a given sts-3 frame) has been captured and loaded into the ?receive toh ca p ture? buffer, it will remain there
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 132 for one sonet frame period. 0 ? indicates that the ?receive toh data capture? interrupt has not occurred since the last read of this register. 1 ? indicates that the ?receive toh data capture? interrupt has occurred since the last read of this register. 1 change in k1, k2 byte unstable defect condition interrupt status rur change of k1, k2 byte unstable defect condition interrupt status: this reset-upon-read bit-field indicates whether or not the ?change in k1, k2 byte unstable defect condition? interrupt has occurred since the last read of this register. the receive sts-3 toh processor block will generate this interrupt in response to either of the following events. ? whenever the receive sts-3 toh processor block declares the ?k1, k2 byte unstable defect? condition. ? whenever the receive sts-3 toh processor block clears the ?k1, k2 byte unstable defect? condition. 0 ? indicates that the ?change of k1, k2 byte unstable defect condition? interrupt has not occurred since the last read of this register. 1 ? indicates that the ?change of k1, k2 byte unstable defect condition? interrupt has occurred since the last read of this register. note: the user can determine if the receive sts-3 toh processor block is currently declaring the ?k1, k2 byte unstable defect condition? by reading out the contents of bit 5 (k1, k2 byte unstable defect declared), within the ?receive st s-3 transport status register ? byte 0? (address location = 0x1107). 0 new k1, k2 byte value interrupt status rur new k1, k2 byte value interrupt status: this reset-upon-read bit-field indicates whether or not the ?new k1, k2 byte value? interrupt has occurred since the last read of this register. the receive sts-3 toh processor block will generate this interrupt whenever it has ?accepted? a new set of k1, k2 byte values from the incoming sts-3 data-stream. 0 ? indicates that the ?new k1, k2 byte value? interrupt has not occurred since the last read of this register. 1 ? indicates that the ?new k1, k2 byte value? interrupt has occurred since the last read of this register. note: the user can obtain the contents of the new k1 byte by reading out the contents of the ?receive st s-3 transport k1 byte value? register (address location= 0x111f). further, the user can also obtain the contents of the new k2 byte by reading out the contents of the ?receive sts-3 transport k2 byte value? register (address location= 0x1123).
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 133 table 68: receive sts-3 transport interrupt status register ? byte 0 (address location= 0x110b) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 change in sf defect condition interrupt status change in sd defect condition interrupt status detection of rei-l event interrupt status detection of b2 byte error interrupt status detection of b1 byte error interrupt status change of lof defect condition interrupt status change of sef defect condition interrupt status change of los defect condition interrupt status rur rur rur rur rur rur rur rur 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 change in sf defect condition interrupt status rur change of signal failure (sf) defect condition interrupt status: this reset-upon-read bit-field indicates whether or not the ?change of sf defect condition interrupt? has occurred since the last read of this register. the receive sts-3 toh processor block will generate this interrupt in response to either of the following events. ? whenever the receive sts-3 toh processor block declares the sf defect condition. ? whenever the receive sts-3 toh processor block clears the sf defect condition. 0 ? indicates that the ?change of sf defect condition interrupt? has not occurred since the last read of this register. 1 ? indicates that the ?change of sf defect condition interrupt? has occurred since the last read of this register. note: the user can determine whether or not the receive sts-3 toh processor block is currently declaring the ?sf? defect condition by reading out the state of bit 4 (sf defect declar ed) within the ?receive sts-3 transport status register ? byte 0 (address location= 0x1107). 6 change of sd defect condition interrupt status rur change of signal degrade (sd) defect condition interrupt status: this reset-upon-read bit-field indicates whether or not the ?change of sd defect condition interrupt? has occurred since the last read of this register. the receive sts-3 toh processor block will generate this interrupt in response to either of the following events. ? whenever the receive sts-3 toh processor block declares the sd defect condition. ? whenever the receive sts-3 toh processor block clears the sd defect condition. 0 - indicates that the ?change of sd defect condition interrupt? has not occurred since the last read of this register. 1 ? indicates that the ?change of sd defect condition interrupt? has occurred since the last read of this register. note: the user can determine whether or not the receive sts-3 toh processor block is declaring the ?sd? defect condition by reading out the state of bit 3 (sd defect declared) within the ?receive sts-3 transport status register ? byte 0 (address location= 0x1107). 5 detection of rei- l event interrupt status rur detection of rei-l (line ? remote error indicator) event interrupt status:
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 134 status this reset-upon-read bit-field indicates whether or not the ?detection of rei-l event? interrupt has occurred since the last read of this register. the receive sts-3 toh processor block will generate this interrupt anytime it detects an rei-l event within the incoming sts-3 data-stream. 0 ? indicates that the ?detection of rei-l event? interrupt has not occurred since the last read of this register. 1 ? indicates that the ?detection of line ? rei-l event? interrupt has occurred since the last read of this register. 4 detection of b2 byte error interrupt status rur detection of b2 byte error interrupt status: this reset-upon-read bit-field indicates whether or not the ?detection of b2 byte error interrupt? has occurred sinc e the last read of this register. the receive sts-3 toh processor block will generate this interrupt anytime it detects a b2 byte error within the incoming sts-3 data-stream. 0 ? indicates that the ?detection of b2 byte error interrupt? has not occurred since the last read of this register. 1 ? indicates that the ?detection of b2 byte error interrupt? has occurred since the last read of this register. 3 detection of b1 byte error interrupt status rur detection of b1 byte error interrupt status: this reset-upon-read bit-field indicates whether or not the ?detection of b1 byte error interrupt? has occurred si nce the last read of this register. the receive sts-3 toh processor block will generate this interrupt anytime it detects a b1 byte error within the incoming sts-3 data-stream. 0 ? indicates that the ?detection of b1 byte error interrupt? has not occurred since the last read of this register. 1 ? indicates that the ?detection of b1 byte error interrupt? has occurred since the last read of this register 2 change of lof defect condition interrupt status rur change of loss of frame (lof) defect condition interrupt status: this reset-upon-read bit-field indicates whether or not the ?change of lof defect condition? interrupt has oc curred since the last read of this register. the receive sts-3 toh processor block will generate this interrupt in response to either of the following events. ? whenever the receive sts-3 toh processor block declares the lof defect condition. ? whenever the receive sts-3 to h processor block clears the lof defect condition. 0 ? indicates that the ?change of lof defect condition? interrupt has not occurred since the last read of this register. 1 ? indicates that the ?change of lo f defect condition? interrupt has occurred since the last read of this register. note: the user can determine whether or not the receive sts-3 toh processor block is currently dec laring the lof defect condition by reading out the state of bit 2 (lof defect declared) within the ?receive sts-3 transport status register ? byte 0 (address location= 0x1107). 1 change of sef defect condition interrupt status rur change of sef defect condition interrupt status: this reset-upon-read bit-field indicates whether or not the ?change of sef? defect condition interrupt has o ccurred since the last read of this register. the receive sts-3 toh processor block will generate this interrupt in response to either of the following events. ? whenever the receive sts-3 toh processor block declares the sef
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 135 defect condition. ? whenever the receive sts-3 toh processor block clears the sef defect condition. 0 ? indicates that the ?change of sef defect condition? interrupt has not occurred since the last read of this register. 1 ? indicates that the ?change of sef defect condition? interrupt has occurred since the last read of this register. note: the user can determine whether or not the receive sts-3 toh processor block is currently declaring the sef defect condition by reading out the state of bit 1 (sef defect declared) within the ?receive sts-3 transport status register ? byte 0 (address location= 0x1107). 0 change of los defect condition interrupt status rur change of loss of signal (los) defect condition interrupt status: this reset-upon-read bit-field indicates whether or not the ?change of los defect condition? interrupt has occurred since the last read of this register. the receive sts-3 toh processor block will generate this interrupt in response to either of the following events. ? whenever the receive sts-3 toh processor block declares the los defect condition. ? whenever the receive sts-3 toh processor block clears the los defect condition. 0 ? indicates that the ?change of lo s defect condition? interrupt has not occurred since the last read of this register. 1 ? indicates that the ?change of lo s defect condition? interrupt has occurred since the last read of this register. note: the user can determine whether or not the receive sts-3 toh processor block is currently dec laring the los defect condition by reading out the contents of bi t 0 (los defect declared) within the receive sts-3 transport status register ? byte 0 (address location= 0x1107).
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 136 table 69: receive sts-3 transport interrupt enable register ? byte 2 (address location= 0x110d) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 unused change of ais-l defect condition interrupt enable change of rdi-l defect condition interrupt enable r/o r/o r/o r/o r/o r/o r/w r/w 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 ? 2 unused r/o 1 change of ais-l defect condition interrupt enable r/w change of ais-l (line ais) defect condition interrupt enable: this read/write bit-field permits the user to either enable or disable the ?change of ais-l defect condition? interrupt. if the user enables this interrupt, then the XRT94L33 will generate an interrupt in response to either of the following conditions. ? whenever the receive sts-3 toh processor block declares the ?ais-l? defect condition. ? whenever the receive sts-3 toh processor block clears the ?ais-l? defect condition. 0 ? disables the ?change of ais-l defect condition? interrupt. 1 ? enables the ?change of ais-l defect condition? interrupt. note: the user can determine if the receive sts-3 toh processor block is currently declaring the ais-l defect condition by reading out the state of bit 0 (ais-l defect declared) within the ?receive sts-3 transport status register ? byte 1? (address location= 0x1106). 0 change of rdi-l defect condition interrupt enable r/w change of rdi-l (line remote defect indicator) defect condition interrupt enable: this read/write bit-field permits the user to either enable or disable the ?change of rdi-l defect condition? in terrupt. if the user enables this interrupt, then the XRT94L33 will generate an interrupt in response to either of the following conditions. ? whenever the receive sts-3 toh processor block declares the ?rdi-l? defect condition. ? whenever the receive sts-3 toh processor block clears the ?rdi-l? defect condition. 0 ? disables the ?change of rdi-l defect condition? interrupt. 1 ? enables the ?change of rdi-l defect condition? interrupt.
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 137 table 70: receive sts-3 transport interrupt enable register ? byte 1 (address location= 0x110e) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 new s1 byte interrupt enable change in s1 byte unstable defect condition interrupt enable change in section trace message unstable state interrupt enable new section trace message interrupt enable change in section trace message mismatch defect condition interrupt enable receive toh cap done interrupt enable change in k1, k2 byte unstable defect condition interrupt enable new k1k2 byte value interrupt enable r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 new s1 byte value interrupt enable r/w new s1 byte value interrupt enable: this read/write bit-field permits the user to enable or disable the ?new s1 byte value? interrupt. if the user enables this interrupt, then the receive sts-3 toh processor block will generate this interrupt anytime it receives and accepts a new s1 byte value. the receive sts-3 toh processor block will accept a new s1 byte after it has received it for 8 consecutive sts-3 frames. 0 ? disables the ?new s1 byte value? interrupt. 1 ? enables the ?new s1 byte value? interrupt. 6 change in s1 unstable defect condition interrupt enable r/w change in s1 byte unstable defect condition interrupt enable: this read/write bit-field permits the user to either enable or disable the ?change in s1 byte unstable defect condition? interr upt. if the user enables this bit-field, then the receive sts-3 toh processor block will generate an interrupt in response to either of the following conditions. ? whenever the receive sts-3 toh processor block declares the ?s1 byte unstable? defect condition. ? whenever the receive sts-3 toh processor block clears the ?s1 byte unstable? defect condition. 0 ? disables the ?change in s1 byte unstable defect condition? interrupt. 1 ? enables the ?change in s1 byte unstable defect condition? interrupt. 5 change in section trace message unstable defect condition interrupt enable r/w change in section trace message unstable defect condition interrupt enable: this read/write bit-field permits the user to either enable or disable the ?change in section trace message unstable defect c ondition? interrupt. if the user enables this interrupt, then the receive sts-3 toh processor block will generate an interrupt in response to either of the following conditions. ? whenever the receive sts-3 toh processor block declares the ?section trace message unstable? defect condition. ? whenever the receive sts-3 toh processor block clears the ?section trace message unstable? defect condition. 0 ? disables the ?change in section trace message unstable defect condition? interrupt. 1 ? enables the ?change in section trace message unstable defect condition? interrupt. 4 new section r/w new section trace message interrupt enable:
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 138 trace message interrupt enable this read/write bit-field permits the us er to enable or disable the ?new section trace message? interrupt. if the user enables this interrupt, then the receive sts-3 toh processor block will generate this inte rrupt anytime it receives and accepts a new section trace message. the receive sts-3 toh processor block will accept a new section trace message after it has receiv ed it 3 (or 5) consecutive times via the j0 byte within the incoming sts-3 data-stream. 0 ? disables the ?new section trace message? interrupt. 1 ? enables the ?new section trace message? interrupt. 3 change in section trace message mismatch defect condition interrupt enable r/w change in ?section trace message mismatch defect condition? interrupt enable: this read/write bit-field permits the user to either enable or disable the ?change in section trace message mism atch defect condition? interrupt. if the user enables this interrupt, then the receive sts-3 toh processor block will generate an interrupt in response to either of the following events. ? whenever the receive sts-3 toh processor block declares the ?section trace message mismatch? defect condition. ? whenever the receive sts-3 toh processor block clears the ?section trace message mismatch? defect condition. note: the user can determine whether or not the receive sts-3 toh processor block is currently declaring the ?section trace message mismatch? defect condition by reading the state of bi t 2 (section trace message mismatch defect declared) within the ?receive sts-3 transport status register ? byte 1 (address location= 0x1106). 2 receive toh cap done interrupt enable r/w receive toh capture done ? interrupt enable: this read/write bit-field permits the user to either enable or disable the ?receive toh data capture? interrupt, within th e receive sts-3 toh processor block. if this interrupt is enabled, then the receive sts-3 toh processor block will generate an interrupt anytim e it has captured the last toh byte into the capture buffer. note: once the toh (of a given sts-3 frame) has been captured and loaded into the ?receive toh capture? buffer, it will remain there for one sonet frame period. 0 ? disables the ?receive toh capture? interrupt. 1 ? enables the ?receive toh capture? interrupt. 1 change in k1, k2 byte unstable defect condition interrupt enable r/w change of k1, k2 byte unstable defect condition interrupt enable: this read/write bit-field permits the user to either enable or disable the ?change of k1, k2 byte unstable defect condition? in terrupt. if the user enables this interrupt, then the receive sts-3 toh processor block will generate an interrupt in response to either of the following events. ? whenever the receive sts-3 toh processo r block declares the ?k1, k2 byte unstable defect? condition. ? whenever the receive sts-3 toh processor block clears the ?k1, k2 byte unstable defect? condition. 0 ? disables the ?change in k1, k2 byte unstable defect condition? interrupt 1 ? enables the ?change in k1, k2 byte unstable defect condition? interrupt 0 new k1k2 byte interrupt enable r/w new k1, k2 byte value interrupt enable: this read/write bit-field permits the user to either enable or disable the ?new k1, k2 byte value? interrupt. if the user en ables this interrupt, then the receive sts-3 toh processor block will generate this inte rrupt anytime it receives and accepts a new k1, k2 b y te value. the receive sts-3 toh processor block will acce p t a new
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 139 k1, k2 byte value, after it has received it within 3 (or 5) consecutive sts-3 frames. 0 ? disables the ?new k1, k2 byte value? interrupt. 1 ? enables the ?new k1, k2 byte value? interrupt.
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 140 table 71: receive sts-3 transport interrupt status register ? byte 0 (address location= 0x110f) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 change of sf defect condition interrupt enable change of sd defect condition interrupt enable detection of rei-l event interrupt enable detection of b2 byte error interrupt enable detection of b1 byte error interrupt enable change of lof defect condition interrupt enable change of sef defect condition interrupt enable change of los defect condition interrupt enable r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 change of sf defect condition interrupt enable r/w change of signal failure (sf) defect condition interrupt enable: this read/write bit-field permits the user to either enable or disable the ?change of signal failure (sf) defect condition? interrupt. if the user enables this interrupt, then the XRT94L33 will generate an interrupt in response to any of the following events. ? whenever the receive sts-3 toh processor block declares the sf defect condition. ? whenever the receive sts-3 toh processor block clears the sf defect condition. 0 ? disables the ?change of sf defect condition interrupt?. 1 ? enables the ?change of sf defect condition interrupt?. 6 change of sd defect condition interrupt enable r/w change of signal degrade (sd) defect condition interrupt enable: this read/write bit-field permits the user to either enable or disable the ?change of signal degrade (sd) defect condition? interrupt. if the user enables this interrupt, then the XRT94L33 will generate an interrupt in response to either of the following events. ? whenever the receive sts-3 toh processor block declares the sd defect condition. ? whenever the receive sts-3 toh processor block clears the sd defect condition. 0 ? disables the ?change of sd defect condition interrupt?. 1 ? enables the ?change of sd defect condition interrupt?. 5 detection of rei-l event interrupt enable r/w detection of rei-l (line ? remote error indicator) event interrupt enable: this read/write bit-field permits the user to either enable or disable the ?detection of rei-l event interrupt. if the user enables this interrupt, then the XRT94L33 will generate an interrupt anytime the receive sts-3 toh processor block detects an ?rei-l? event, within the incoming sts-3 data- stream. 0 ? disables the ?detection of rei-l event? interrupt. 1 ? enables the ?detection of rei-l event? interrupt. 4 detection of b2 byte error interrupt enable r/w detection of b2 byte error interrupt enable: this read/write bit-field permits the user to either enable or disable the ?detection of b2 byte error? interrupt. if the user enables this interrupt, then the XRT94L33 will generate an interrupt anytime the receive sts-3 toh processor block detects a b2 b y te error within the incomin g sts-3 data-
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 141 stream. 0 ? disables the ?detection of b2 byte error interrupt?. 1 ? enables the ?detection of b2 byte error interrupt?. 3 detection of b1 byte error interrupt enable r/w detection of b1 byte error interrupt enable: this read/write bit-field permits the user to either enable or disable the ?detection of b1 byte error? interrupt. if the user enables this interrupt, then the XRT94L33 will generate an interrupt anytime the receive sts-3 toh processor block detects a b1 byte error within the incoming sts-3 data- stream. 0 ? disables the ?detection of b1 byte error interrupt?. 1 ? enables the ?detection of b1 byte error interrupt?. 2 change of lof defect condition interrupt enable r/w change of loss of frame (lof) defect condition interrupt enable: this read/write bit-field permits the user to either enable or disable the ?change of lof defect condition? in terrupt. if the user enables this interrupt, then the XRT94L33 will generate an interrupt in response to either of the following conditions. ? whenever the receive sts-3 toh processor block declares the ?lof? defect condition. ? whenever the receive sts-3 toh processor clears the ?lof? defect condition. 0 ? disables the ?change of lof defect condition interrupt. 1 ? enables the ?change of lof defect condition? interrupt. 1 change of sef defect condition interrupt enable r/w change of sef defect condition interrupt enable: this read/write bit-field permits the user to either enable or disable the ?change of sef defect condition? interrupt. if the user enables this interrupt, then the XRT94L33 will generate an interrupt in response to either of the following conditions. ? whenever the receive sts-3 toh processor block declares the ?sef? defect condition. ? whenever the receive sts-3 toh processor block clears the ?sef? defect condition. 0 ? disables the ?change of sef defect condition interrupt?. 1 ? enables the ?change of sef defect condition interrupt?. 0 change of los defect condition interrupt enable r/w change of loss of signal (los) defect condition interrupt enable: this read/write bit-field permits the user to either enable or disable the ?change of lof defect condition? in terrupt. if the user enables this interrupt, then the XRT94L33 will generate an interrupt in response to either of the following conditions. ? whenever the receive sts-3 toh processor block declares the ?lof? defect condition. ? whenever the receive sts-3 toh processor block clears the ?lof? defect condition. 0 ? disables the ?change of lof defect condition interrupt. 1 ? enables the ?change of lof defect condition? interrupt.
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 142 table 72: receive sts-3 transport ? b1 byte e rror count register ? byte 3 (address location= 0x1110) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 b1 byte error count[31:24] rur rur rur rur rur rur rur rur 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 - 0 b1_byte_error_ count[31:24] rur b1 byte error count ? msb: this reset-upon-read register, along with ?receive sts-3 transport ? b1 byte error count register ? bytes 2 through 0; function as a 32 bit counter, which is incremented anytime the receive sts-3 toh processor block detects a b1 byte error within the sts-3 data-stream. note: 1.if the receive sts-3 toh processor bl ock is configured to count b1 byte errors on a ?per-bit? basis, then it will increment this 32 bit counter by the number of bits, within the b1 byte (of each incoming sts-3 frame) that are in error. 2.if the receive sts-3 toh processor bl ock is configured to count b1 byte errors on a ?per-frame? basis, then it will increment this 32 bit counter each time that it receives an sts-3 frame that contains an erred b1 byte. table 73: receive sts-3 transport ? b1 byte e rror count register ? byte 2 (address location= 0x1111) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 b1_byte_error_count[23:16] rur rur rur rur rur rur rur rur 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 - 0 b1_byte_error_ count [23:16] rur b1 byte error count (bits 23 through 16): this reset-upon-read register, along with ?receive sts-3 transport ? b1 byte error count register ? bytes 3, 1 and 0; function as a 32 bit counter, which is incremented anytime the receive sts-3 toh processor block detects a b1 byte error. note: 1.if the receive sts-3 toh processor bl ock is configured to count b1 byte errors on a ?per-bit? basis, then it will increment this 32 bit counter by the number of bits, within the b1 byte (o f each incoming sts-3 frame) that are in error. 2.if the receive sts-3 toh processor bl ock is configured to count b1 byte errors on a ?per-frame? basis, then it will increment this 32 bit counter each time that it receives an sts-3 frame that contains an erred b1 byte.
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 143 table 74: receive sts-3 transport ? b1 byte e rror count register ? byte 1 (address location= 0x1112) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 b1_byte_error_count[15:8] rur rur rur rur rur rur rur rur 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 - 0 b1_byte_error_ count [15:8] rur b1 byte error count ? (bits 15 through 8) this reset-upon-read register, along with ?receive sts-3 transport ? b1 byte error count register ? bytes 3, 2 and 0; function as a 32 bit counter, which is incremented anytim e the receive sts-3 toh processor block detects a b1 byte error. note: 1.if the receive sts-3 toh processor bl ock is configured to count b1 byte errors on a ?per-bit? basis, then it will increment this 32 bit counter by the number of bits, within the b1 byte (of each incoming sts-3 frame) that are in error. 2.if the receive sts-3 toh processor bl ock is configured to count b1 byte errors on a ?per-frame? basis, then it will increment this 32 bit counter each time that it receives an sts-3 frame that contains an erred b1 byte. table 75: receive sts-3 transport ? b1 byte e rror count register ? byte 0 (address location= 0x1113) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 b1_byte _error_count[7:0] rur rur rur rur rur rur rur rur 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 - 0 b1_byte_error_ count [7:0] rur b1 byte error count ? lsb: this reset-upon-read register, along with ?receive sts-3 transport ? b1 byte error count register ? bytes 3 through 1; function as a 32 bit counter, which is incremented anytim e the receive sts-3 toh processor block detects a b1 byte error. note: 1.if the receive sts-3 toh processor bl ock is configured to count b1 byte errors on a ?per-bit? basis, then it will increment this 32 bit counter by the number of bits, within the b1 byte (of each incoming sts-3 frame) that are in error. 2.if the receive sts-3 toh processor bl ock is configured to count b1 byte errors on a ?per-frame? basis, then it will increment this 32 bit counter each time that it receives an sts-3 frame that contains an erred b1 byte.
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 144 table 76: receive sts-3 transport ? b2 byte e rror count register ? byte 3 (address location= 0x1114) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 b2_byte_error_count[31:24] rur rur rur rur rur rur rur rur 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 - 0 b2_byte_error_ count [31:24] rur b2 byte error count ? msb: this reset-upon-read register, along with ?receive sts-3 transport ? b2 byte error count register ? bytes 2 through 0; function as a 32 bit counter, which is incremented anytim e the receive sts-3 toh processor block detects a b2 byte error within the incoming sts-3 data-stream. note: 1.if the receive sts-3 toh processor bl ock is configured to count b2 byte errors on a ?per-bit? basis, then it will increment this 32 bit counter by the number of bits, within the b2 bytes (of each incoming sts-3 frame) that are in error. 2.if the receive sts-3 toh processor bl ock is configured to count b2 byte errors on a ?per-frame? basis, then it will increment this 32 bit counter each time that it receives an sts-3 fram e that contains at least one erred b2 byte.
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 145 table 77: receive sts-3 transport ? b2 byte e rror count register ? byte 2 address location= 0x1115) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 b2_ byte _ error_count[23:16] rur rur rur rur rur rur rur rur 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 - 0 b2_byte error_count [23:16] rur b2 byte error count (bits 23 through 16): this reset-upon-read register, along with ?receive sts-3 transport ? b2 byte error count register ? bytes 3, 1 and 0; function as a 32 bit counter, which is incremented anytim e the receive sts-3 toh processor block detects a b2 byte error. note: 1.if the receive sts-3 toh processor bloc k is configured to count b2 byte errors on a ?per-bit? basis, then it will increment this 32 bit counter by the number of bits, within the b2 bytes (of each incoming sts-3 frame) that are in error. 2.if the receive sts-3 toh processor bl ock is configured to count b2 byte errors on a ?per-frame? basis, then it will increment this 32 bit counter each time that it receives an sts-3 fram e that contains at least one erred b2 byte.
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 146 table 78: receive sts-3 transport ? b2 byte e rror count register ? byte 1 (address location= 0x1116) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 b2_byte_error_count[15:8] rur rur rur rur rur rur rur rur 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 - 0 b2_byte error_count [15:8] rur b2 byte error count ? (bits 15 through 8) this reset-upon-read register, along with ?receive sts-3 transport ? b2 byte error count register ? bytes 3, 2 and 0; function as a 32 bit counter, which is incremented anytim e the receive sts-3 toh processor block detects a b2 byte error within the incoming sts-3 data-stream. note: 1. if the receive sts-3 toh processor block is configured to count b2 byte errors on a ?per-bit? basis, then it will increment this 32 bit counter by the number of bits, within the b2 bytes (of each incoming sts-3 frame) that are in error. 2. if the receive sts-3 toh processor block is configured to count b2 byte errors on a ?per-frame? basis, then it will increment this 32 bit counter each time that it receives an sts-3 fram e that contains at least one erred b2 byte.
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 147 table 79: receive sts-3 transport ? b2 byte e rror count register ? byte 0 (address location= 0x1117) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 b2_byte_error_count[7:0] rur rur rur rur rur rur rur rur 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 - 0 b2_byte error_count[7:0] rur b2 byte error count ? lsb: this reset-upon-read register, along with ?receive sts-3 transport ? b2 byte error count register ? bytes 3 through 1; function as a 32 bit counter, which is incremented anytime the receive sts-3 toh processor block detects a b2 byte error. note: 1. if the receive sts-3 toh processor block is configured to count b2 byte errors on a ?per-bit? basis, then it will increment this 32 bit counter by the number of bits, within the b2 bytes (of each incoming sts-3 frame) that are in error. 2. if the receive sts-3 toh processor block is configured to count b2 byte errors on a ?per-frame? basis, then it will increment this 32 bit counter each time that is receives an sts-3 frame that contains at least one erred b2 byte.
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 148 table 80: receive sts-3 transport ? rei-l event count register ? byte 3 (address location= 0x1118) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 rei-l_event_count[31:24] rur rur rur rur rur rur rur rur 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 - 0 rei-l_event_count [31:24] rur rei-l event count ? msb: this reset-upon-read register, along with ?receive sts-3 transport ? rei-l event count register ? bytes 2 through 0; function as a 32 bit counter, which is incremented anytime the receive sts-3 toh processor block detects a line - remote error indicator event within the incoming sts-3 data-stream. note: 1. if the receive sts-3 toh processor block is configured to count rei-l events on a ?per-bit? basis, then it will increment this 32 bit counter by the value within the rei-l fields of the m1 byte within each incoming sts-3 frame. 2. if the receive sts-3 toh processor block is configured to count rei-l events on a ?per-frame? basis, then it will increment this 32 bit counter each time that it receives an sts-3 frame that contains a ?non-zero? m1 byte value.
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 149 table 81: receive sts-3 transport ? rei-l event count register ? byte 2 (address location= 0x1119) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 rei-l_event_count[23:16] rur rur rur rur rur rur rur rur 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 - 0 rei-l_event_count [23:16] rur rei-l event count (bits 23 through 16): this reset-upon-read register, along with ?receive sts-3 transport ? rei-l event count re gister ? bytes 3, 1 and 0; function as a 32 bit counter, which is incremented anytime the receive sts-3 toh processor block detects a line ? remote error indicator event within the incoming sts-3 data-stream. note: 1. if the receive sts-3 toh processor block is configured to count rei-l events on a ?per-bit? basis, then it will increment this 32 bit counter by the value within the rei-l fields of the m1 byte within each incoming sts-3 frame. 2. if the receive sts-3 toh processor block is configured to count rei-l events on a ?per-frame ? baiss, then it will increment this 32 bit counter each time that it receives an sts-3 frame that contains a non-zero m1 byte value.
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 150 table 82: receive sts-3 transport ? rei-l event count register ? byte 1 (address location= 0x111a) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 rei-l_event_count[15:8] rur rur rur rur rur rur rur rur 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 - 0 rei-l_event_count[15:8] rur rei-l event count ? (bits 15 through 8) this reset-upon-read register, along with ?receive sts-3 transport ? rei-l event count re gister ? bytes 3, 2 and 0; function as a 32 bit counter, which is incremented anytime the receive sts-3 toh processor block detects a line ?remote error indicator event within the incoming sts-3 data-stream. note: 1. if the receive sts-3 toh processor block is configured to count rei-l events on a ?per-bit? basis, then it will increment this 32 bit counter by the value within the rei-l fields of the m1 byte within each incoming sts-3 frame. 2. if the receive sts-3 toh processor block is configured to count rei-l events on a ?per-bit? basis, then it will increment this 32 bit counter each that it receives an sts-3 frame that contains a non-zero m1 byte.
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 151 table 83: receive sts-3 transport ? rei-l event count register ? byte 0 (address location= 0x111b) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 rei-l_event_count[7:0] rur rur rur rur rur rur rur rur 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 - 0 rei- l_event_count[7:0] rur rei-l event count ? lsb: this reset-upon-read register, along with ?receive sts-3 transport ? rei-l event count regist er ? bytes 3 through 1; function as a 32 bit counter, which is incremented anytime the receive sts-3 toh processor block detects a line ? remote error indicator event within the incoming sts-3 data-stream. note: 1. if the receive sts-3 toh processor block is configured to count rei-l events on a ?per-bit? basis, t hen it will increment this 32 bit counter by the value within the rei-l fields of the m1 byte within each incoming sts-3 frame. 2. if the receive sts-3 toh processor block is configured to count rei-l events on a ?per-frame? baiss, then it will increment this 32 bit counter each time that it receives an sts-3 frame that contains a ?non-zero? m1 byte value.
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 152 table 84: receive sts-3 transport ? received k1 byte value register (address location= 0x111f) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 filtered_k1_byte_value[7:0] r/o r/o r/o r/o r/o r/o r/o r/o 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 ? 0 filtered_k1_byte value[7:0] r/o filtered/accepted k1 byte value: these read-only bit-fields contain the value of the most recently ?filtered? k1 byte value that the receive sts-3 toh processor block has received. the receive sts-3 toh processor block will ?accept? a given k1 byte, once it has received this particular k1 byte value within 3 consecutive sts-3 frames. this register should be polled by software in order to determine various aps codes. table 85: receive sts-3 transport ? receive k2 byte value register (address location= 0x1123) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 filtered_k2_byte_value[7:0] r/o r/o r/o r/o r/o r/o r/o r/o 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 ? 0 filtered_k2_byte_value[7:0] r/o filtered/accepted k2 byte value: these read-only bit-fields contain the value of the most recently ?filtered? k2 byte value that the receive sts-3 toh processor block has received. the receive sts-3 toh processor block will ?accept? a given k2 byte, once it has received this particular k2 byte value within 3 consecutive sts-3 frames. this register should be polled by software in order to determine various aps codes.
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 153 table 86: receive sts-3 transport ? received s1 byte value register (address location= 0x1127) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 filtered_s1_byte_value[7:0] r/o r/o r/o r/o r/o r/o r/o r/o 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 ? 0 filtered_s1_byte_value[7:0] r/o filtered/accepted s1 byte value: these read-only bit-fields contain the value of the most recently ?filtered? s1 byte va lue that the receive sts-3 toh processor block has received. the receive sts-3 toh processor block will ?accept? a given s1 byte, once it has received this particular s1 byte value within 8 consecutive sts-3 frames. table 87: receive sts-3 transport ? in-sync threshold value (address location=0x112b) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 unused frpatout[1:0] frpatin[1:0] unused r/o r/o r/o r/w r/w r/w r/w r/o 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 ? 5 unused r/o 4 ? 3 frpatout [1:0] r/w framing pattern ? sef declaration criteria: these two read/write bit-fields permi t the user to define the sef defect declaration criteria for the receive sts- 3 toh processor block. the relationship between the state of these bit-fields and the corresponding sef defect declaration criteria are presented below. frpatout[1:0] sef defect declaration criteria 00 01 the receive sts-3 toh processor block will declare the sef defect condition if either of the following conditions are true for four consecutive sonet frame periods. ? if the last (of the 3) a1 bytes, in the sts-3 data stream is erred, or ? if the first (of the 3) a2 bytes, in the sts-3 data stream, is erred. hence, for this selection, a to tal of 16 bits are evaluated for sef defect declaration. 10 the receive sts-3 toh processor block will declare the sef defect condition if either of the following conditions are true for four consecutive sonet frame periods. ? if the last two (of the 3) a1 bytes, in the sts-3 data stream, are erred, or ? if the first two (of the 3) a2 bytes, in the sts-3 data stream, are erred. hence, for this selection, a to tal of 32 bits are evaluated for sef defect declaration.
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 154 11 the receive sts-3 toh processor block will declare the sef defect condition if either of the following conditions are true for four consecutive sonet frame periods. ? if the last three (of the 3) a1 bytes, in the sts-3 data stream, are erred, or ? if the first three (of the 3) a2 bytes, in the sts-3 data stream, are erred. hence, for this selection, a to tal of 48 bits are evaluated for sef defect declaration. 2 - 1 frpatin [1:0] r/w framing pattern ? sef defect clearance criteria: these two read/write bit-fields permit the user to define the ?sef defect clearance? criteria for the receive sts-3 toh processor block. the relationship between the state of these bit-fields and the corresponding sef defect clearance criteria are presented below. frpatin[1:0] sef defect clearance criteria 00 01 the receive sts-3 toh processor block will clear the sef defect condition if both of the following conditions are true for two consecutive sonet frame periods. ? if the last (of the 3) a1 bytes, in the sts-3 data stream is un-erred, and ? if the first (of the 3) a2 bytes, in the sts-3 data stream, is un-erred. hence, for this selection, a total of 16 bits/frame are evaluated for sef defect clearance. 10 the receive sts-3 toh processor block will clear the sef defect condition if both of the following conditions are true for two consecutive sonet frame periods. ? if the last two (of the 3) a1 bytes, in the sts-3 data stream, are un-erred, and ? if the first two (of the 3) a2 bytes, in the sts-3 data stream, are un-erred. hence, for this selection, a total of 32 bits/frame are evaluated for sef defect clearance. 11 the receive sts-3 toh processor block will clear the sef defect condition if both of the following conditions are true for two consecutive sonet frame periods. ? if the last three (of the 3) a1 bytes, in the sts-3 data- stream, are un-erred, and ? if the first three (of the 3) a2 bytes, in the sts-3 data stream, are un-erred. hence, for this selection, a total of 48 bits/frame are evaluated for sef defect declaration. 0 unused r/o
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 155 table 88: receive sts-3 transport ? los threshold value - msb (address location= 0x112e) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 los_threshold[15:8] r/w r/w r/w r/w r/w r/w r/w r/w 1 1 1 1 1 1 1 1 b it n umber n ame t ype d escription 7 - 0 los_threshold[15:8] r/w los threshold value ? msb: these read/write bits, along the contents of the ?receive sts-3 transport ? los threshold value ? lsb? register specify the number of consecutive (all zero) bytes that the receive sts-3 toh processor block must detect befor e it can declare the los defect condition. table 89: receive sts-3 transport ? los threshold value - lsb (address location= 0x112f) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 los_threshold[7:0] r/w r/w r/w r/w r/w r/w r/w r/w 1 1 1 1 1 1 1 1 b it n umber n ame t ype d escription 7 - 0 los_threshold[7:0] r/w los threshold value ? lsb: these read/write bits, along the contents of the ?receive sts-3 transport ? los threshold value ? m sb? register specify the number of consecutive (all zero) bytes that the receive sts-3 toh processor block must detect before it can declare the los defect condition.
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 156 table 90: receive sts-3 transport ? receive sf set monitor interval ? byte 2 (address location= 0x1131) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 sf_set_monitor_window[23:16] r/w r/w r/w r/w r/w r/w r/w r/w 1 1 1 1 1 1 1 1 b it n umber n ame t ype d escription 7 - 0 sf_set_monitor_ window [23:16] r/w sf_set_monitor_interval ? msb: these read/write bits, along the contents of the ?receive sts-3 transport ? sf set monitor interval ? byte 1 and byte 0? registers permit the user to specify the length of the ?monitoring period? (in terms of ms) for sf (signal failure) defect declaration. when the receive sts-3 toh processor block is checking the incoming sts-3 signal in order to determine if it should declare the sf defect condition, it will accumulate b2 byte errors throughout the user-specified ?sf defect declarat ion monitoring period?. if, during this ?sf defect declaration monitoring period?, the receive sts-3 toh processor block accumulates more b2 byte errors than that specified within the ?receive sts-3 transport sf set threshold? register, then the receive sts-3 toh processor block will declare the sf defect condition. notes: o the value that the user wr ites into these three (3) ?sf set monitor window? registers specifies the duration of the ?sf defect declaration monitoring period?, in terms of ms. o this particular register byte contains the ?msb? (most significant byte) value of the three registers that specify the ?sf defect declaration monitoring period?.
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 157 table 91: receive sts-3 transport ? receive sf set monitor interval ? byte 1 (address location= 0x1132) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 sf_set_monitor_window[15:8] r/w r/w r/w r/w r/w r/w r/w r/w 1 1 1 1 1 1 1 1 b it n umber n ame t ype d escription 7 - 0 sf_set_monitor_window [15:8] r/w sf_set_monitor_interval (bits 15 through 8): these read/write bits, along the contents of the ?receive sts-3 transport ? sf set monitor interval ? byte 2 and byte 0? registers permit the user to specify the length of the ?monitoring period? (in terms of ms) for sf (signal failure) defect declaration when the receive sts-3 toh processor block is checking the incoming sts-3 signal in order to determine if it should declare the sf defect condition, it will accumulate b2 byte errors throughout the user specified ?s f defect declaration monitoring period?. if, during this ?sf defect declaration monitoring period? the receive sts-3 toh processor block accumulates more b2 byte errors than that specified within the ?receive sts-3 transport sf set threshold? register, then the receive sts-3 toh processor block will declare the sf defect condition. note: the value that the user writ es into these three (3) ?sf set monitor window? registers s pecifes the duration of the ?sf defect declaration? monitori ng period, in terms of ms.
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 158 table 92: receive sts-3 transport ? receive sf set monitor interval ? byte 0 (address location= 0x1133) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 sf_set_monitor_window[7:0] r/w r/w r/w r/w r/w r/w r/w r/w 1 1 1 1 1 1 1 1 b it n umber n ame t ype d escription 7 - 0 sf_set_monitor_window[7:0] r/w sf_set_monitor_interval ? lsb: these read/write bits, along the contents of the ?receive sts-3 transport ? sf set monitor interval ? byte 2 and byte 1? registers permit the user to specify the length of the ?monitoring period? (in terms of ms) for sf (signal failure) defect declaration. when the receive sts-3 toh processor block is checking the incoming sts-3 signal in order to determine if it should declare the sf defect condition, it will accumulate b2 byte errors throughout the user- specified ?sf defect declaration monitoring period?. if, during this ?sf defect declaration monitoring period?, the receive sts-3 toh processor block accumulates more b2 byte errors than that specified within the ?receive sts-3 transport sf set threshold? register, then the receive sts-3 toh processor block will declare the sf defect condition. notes: 1. the value that the user writes into these three (3) ?sf set monitor window? registers, specifies t he duration of the ?sf defect declaration? monitoring period, in terms of ms. 2. this particular register byte contains the ?lsb? (least significant byte) value of the three registers that sp ecify the ?sf defect declaration monitoring period?.
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 159 table 93: receive sts-3 transport ? receive sf set threshold ? byte 1 (address location= 0x1136) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 sf_set_threshold[15:8] r/w r/w r/w r/w r/w r/w r/w r/w 1 1 1 1 1 1 1 1 b it n umber n ame t ype d escription 7 - 0 sf_set_threshold[15:8] r/w sf_set_threshold ? msb: these read/write bits, along the contents of the ?receive sts-3 transport ? sf set threshold ? byte 0? registers permit the user to specify the number of b2 byte errors that will cause the receive sts-3 toh processor block to declare the sf (signal failure) defect condition. when the receive sts-3 toh processor block is checking the incoming sts-3 signal in order to determine if it should declare the sf defect condition, it will accumulate b2 byte errors throughout the ?sf defect declaration monitoring period?. if the number of accumulated b2 byte errors exceeds that value, which is programmed into this and the ?receive sts-3 transport sf set threshold ? byte 0? register, then the receive sts-3 toh processor block will declare the sf defect condition. note: this particular register functions as the msb (most signficant byte) of the ?16-bit? expression for the ?sf defect declaration b2 byte error? threshold.
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 160 table 94: receive sts-3 transport ? receive sf set threshold ? byte 0 address location= 0x1137) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 sf_set_threshold[7:0] r/w r/w r/w r/w r/w r/w r/w r/w 1 1 1 1 1 1 1 1 b it n umber n ame t ype d escription 7 - 0 sf_set_threshold[7: 0] r/w sf_set_threshold ? lsb: these read/write bits, along the contents of the ?receive sts- 3 transport ? sf set threshold ? byte 1? registers permit the user to specify the number of b2 byte er rors that will cause the receive sts-3 toh processor block to declare the sf (signal failure) defect condition. when the receive sts-3 toh processor block is checking the incoming sts-3 signal in order to determine if it should declare the sf defect condition, it will accumulate b2 byte errors throughout the ?sf defect monitoring period?. if the number of accumulated b2 byte errors exceeds that which has been programmed into this and the ?receive sts-3 transport sf set threshold ? byte 1? register, then the receive sts-3 toh processor block will declare the sf defect condition. note: this particular register functions as the lsb (least signficant byte) of the ?16-bit? expression for the ?sf defect declaration b2 byte error? threshold.
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 161 table 95: receive sts-3 transport ? receive sf clear threshold ? byte 1 (address location= 0x113a) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 sf_clear_threshold[15:8] r/w r/w r/w r/w r/w r/w r/w r/w 1 1 1 1 1 1 1 1 b it n umber n ame t ype d escription 7 - 0 sf_clear_threshold [15:8] r/w sf_clear_threshold ? msb: these read/write bits, along the contents of the ?receive sts-3 transport ? sf clear threshold ? byte 0? registers permit the user to specify the upp er limit for the number of b2 byte errors that will cause the receive sts-3 toh processor block to clear the sf (signal failure) defect condition. when the receive sts-3 toh processor block is checking the incoming sts-3 signal in order to determine if it should clear the sf defect condition, it will accumulate b2 byte errors throughout the ?sf defect clearance monitoring period?. if the number of accumulated b2 byte errors is less than that programmed into this and the ?receive sts-3 transport sf clear threshold ? byte 0? register, then the receive sts-3 toh processor block will clear the sf defect condition. note: this particular register functions as the msb (most significant byte) of the ?16-bit? expression for the ?sf defect clearance b2 byte error? threshold.
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 162 table 96: receive sts-3 transport ? receive sf clear threshold ? byte 0 (address location= 0x113b) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 sf_clear_threshold[7:0] r/w r/w r/w r/w r/w r/w r/w r/w 1 1 1 1 1 1 1 1 b it n umber n ame t ype d escription 7 - 0 sf_clear_threshold [7:0] r/w sf_clear_threshold ? lsb: these read/write bits, along the contents of the ?receive sts-3 transport ? sf clear threshold ? byte 1? registers permit the user to specify the upp er limit for the number of b2 bit errors that will cause the receive sts-3 toh processor block to clear the sf (signal failure) defect condition. when the receive sts-3 toh processor block is checking the incoming sts-3 signal in order to determine if it should clear the sf defect condtiion, it will accumulate b2 byte errors throughout the ?sf defect clearance monitoring period?. if the number of accumulated b2 byte errors is less than that programmed into this and the ?receive sts-3 transport sf clear threshold ? byte 1? register, then the receive sts-3 toh processor block will clear the sf defect condition. note: this particular register functions as the lsb (least significant byte) of the ?16-bit? expression for the ?sf defect clearance b2 byte error? threshold.
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 163 table 97: receive sts-3 transport ? receive sd se t monitor interval ? byte 2 (address location= 0x113d) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 sd_set_monitor_window[23:16] r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7-0 sd_set_monitor_window [23:16] r/w sd_set_monitor_interval ? msb: these read/write bits, along the contents of the ?receive sts-3 transport ? sd set monitor interval ? byte 1 and byte 0? registers permit the user to specify the length of the ?monitoring period? (in terms of ms) for sd (signal degrade) defect declaration. when the receive sts-3 toh processor block is checking the incoming sts-3 signal, in order to determine if it should declare the sd defect condition, it will accumulate b2 byte errors throughout the user- specified ?sd defect declaration monitoring period?. if, during this ?sd defect declaration monitoring period?, the receive sts-3 toh processor block accumulates more b2 byte errors than that specified within the ?receive sts-3 transport sd set threshold? register, then the receive sts-3 toh processor block will declare the sd defect condition. notes: 1. the value that the user writes into these three (3) ?sd set monitor window? registers, specifies the duration of the ?sd defect declaration monitoring period?, in terms of ms. 2. this particular register byte contains the ?msb? (most significant byte) value of the three registers that specify the ?sd defect declaration monitoring period?.
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 164 table 98: receive sts-3 transport ? receive sd se t monitor interval ? byte 1 (address location= 0x113e) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 sd_set_monitor_window[15:8] r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7-0 sd_set_monitor_window[15:8] r/w sd_set_monitor_interval ? bits 15 through 8: these read/write bits, along the contents of the ?receive sts-3 transport ? sd set monitor interval ? byte 2 and byte 0? registers permit the user to specify the length of the ?monitoring period? (in terms of ms) for sd (signal degrade) defect declaration. when the receive sts-3 toh processor block is checking the incoming sts-3 signal in order to determine it it should declare the sd defect condition, it will accumulate b2 byte errors throughout the user- specified ?sd defect declaration monitoring period?. if, during this ?sd defect de claration moni toring period? the receive sts-3 toh processor block accumulates more b2 byte errors than that specified within the ?receive sts-3 transport sd set threshold? register, then the receive sts-3 toh processor block will declare the sd defect condition. note: the value that the user writes into these three (3) ?sd set monitor window? registers, specifies the duration of the ?sd defect declaration? monitoring period, in terms of ms.
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 165 table 99: receive sts-3 transport ? receive sd se t monitor interval ? byte 0 (address location= 0x113f) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 sd_set_monitor_window[7:0] r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7-0 sd_set_monitor_window[ 7:0] r/w sd_set_monitor_interval ? lsb: these read/write bits, along the contents of the ?receive sts-3 transport ? sd set monitor interval ? byte 2 and byte 1? registers permit the user to specify the length of the ?monitoring period? (in terms of ms) for sd (signal degrade) defect declaration. when the receive sts-3 toh processor block is checking the incoming sts-3 signal in order to determine if it should declare the sd defect condition, it will accumulate b2 byte errors throughout the user-specified ?sd defect declarat ion monitoring period?. if, during this ?sd defect declaration monitoring period?, the receive sts-3 toh processor block a ccumulates more b2 byte errors than that specified within the ?receive sts-3 transport sd set threshold? register, then the receive sts-3 toh processor block will declare the sd defect condition. notes: 1. the value that the us er writes into these three (3) ?sd set monitor window? registers, specifies the duration of the ?sd defect declaration? monitoring period, in terms of ms. 2. this particular register byte contains the ?lsb? (least significant byte) value of the three registers that specify the ?sd defect declaration monitoring period?.
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 166 table 100: receive sts-3 transport ? receive sd set threshold ? byte 1 (address location= 0x1142) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 sd_set_threshold[15:8] r/w r/w r/w r/w r/w r/w r/w r/w 1 1 1 1 1 1 1 1 b it n umber n ame t ype d escription 7 - 0 sd_set_threshold[15:8] r/w sd_set_threshold ? msb: these read/write bits, along the contents of the ?receive sts-3 transport ? sd set threshold ? byte 0? registers permit the user to specify the number of b2 byte errors that will cause the receive sts-3 toh processor block to declare the sd (signal degrade) defect condition. when the receive sts-3 toh processor block is checking the incoming sts-3 signal in order to determine if it should declare the sd defect condition, it will accumulate b2 byte errors throughout the ?sd defect declaration monitoring period?. if the number of accumulated b2 byte errors exceeds that value, which is programmed into this and the ?receive sts-3 transport sd set threshold ? byte 0? register, then the receive sts-3 toh processor block will declare the sd defect condition. table 101: receive sts-3 transport ? receive sd set threshold ? byte 0 (address location= 0x1143) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 sd_set_threshold[7:0] r/w r/w r/w r/w r/w r/w r/w r/w 1 1 1 1 1 1 1 1 b it n umber n ame t ype d escription 7 - 0 sd_set_threshold[7:0] r/w sd_set_threshold ? lsb: these read/write bits, along the contents of the ?receive sts-3 transport ? sd set threshold ? byte 1? registers permit the user to specify the number of b2 byte errors that will cause the receive sts-3 toh processor block to declare the sd (signal degrade) defect condition. when the receive sts-3 toh processor block is checking the incoming sts-3 signal in order to determine if it should declare the sd defect condition, it will accumulate b2 byte errors throughout the ?sd defect monitoring period?. if the number of accumulated b2 byte errors exceeds that which has been programmed into this and the ?receive sts-3 transport sd set threshold ? byte 1? register, then the receive sts-3 toh processor block will declare the sd defect condition.
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 167 table 102: receive sts-3 transport ? receive sd clear threshold ? byte 1 (address location= 0x1146) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 sd_clear_threshold[15:8] r/w r/w r/w r/w r/w r/w r/w r/w 1 1 1 1 1 1 1 1 b it n umber n ame t ype d escription 7 - 0 sd_clear_threshold[15:8] r/w sd_clear_threshold ? msb: these read/write bits, along the contents of the ?receive sts-3 transport ? sd clear threshold ? byte 0? registers permit the user to specify the upper limit for the number of b2 byte errors that will cause the receive sts-3 toh processor block to clear the sd (signal degrade) defect condition. when the receive sts-3 toh processor block is checking the incoming sts-3 signal in order to determine if it should clear the sd defect condition, it will accumulate b2 byte errors throughout the ?sd defect clearance monitoring period?. if the number of accumulated b2 byte errors is less than that programmed into th is and the ?receive sts-3 transport sd clear threshold ? byte 0? register, then the receive sts-3 toh processor block will clear the sd defect condition.
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 168 table 103: receive sts-3 transport ? receive sd clear threshold ? byte 1 (address location= 0x1147) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 sd_clear_threshold[7:0] r/w r/w r/w r/w r/w r/w r/w r/w 1 1 1 1 1 1 1 1 b it n umber n ame t ype d escription 7 - 0 sd_clear_threshold[7:0] r/w sd_clear_threshold ? lsb: these read/write bits, along the contents of the ?receive sts-3 transport ? sd clear threshold ? byte 1? registers permit the user to specify the upp er limit for the number of b2 byte errors that will cause the receive sts-3 toh processor block to clear the sd (signal degrade) defect condition. when the receive sts-3 toh processor block is checking the incoming sts-3 signal in order to determine if it should clear the sd defect condition, it will accumulate b2 byte errors, throughout the ?sd defect clearance monitoring period?. if the number of accumulated b2 byte errors is less than that programmed into this and the ?receive sts-3 transport sd clear threshold ? byte 1? register, then the receive sts-3 toh processor block will clear the sd defect condition.
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 169 table 104: receive sts-3 transport ? force sef condition register (address location= 0x114b) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 unused sef force r/o r/o r/o r/o r/o r/o r/o r/w 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 ? 1 unused r/o 0 sef force r/w sef force: this read/write bit-field permits the user to force the receive sts-3 toh processor block to declare the sef defect condition. the receive sts-3 toh processor block will then attempt to reacquire framing. writing a ?1? into this bit-field conf igures the receive sts-3 toh processor block to declare the sef defect condition. the receive sts-3 toh processor block will automatically set this bit-field to ?0? once it has reacquired framing (e.g., has detected two consecutive sts-3 frames with the correct a1 and a2 bytes).
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 170 table 105: receive sts-3 transport ? receive section trace message buffer control register (address location= 0x114f) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 unused receive section trace message buffer read select receive section trace message accept threshold section trace message alignment type receive section trace message length[1:0] r/o r/o r/o r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 ? 5 unused r/o 4 receive section trace message buffer read select r/w receive section trace message buffer read selection: this read/write bit-field permits the user to specify which of the following receive section trace message buffer segments that the microprocessor will read out, whenever it reads out the co ntents of the receive section trace message buffer address space. a. the ?actual? receive section tr ace message buffer. the ?actual? receive section trace message buffer contains the contents of the most recently received (and accepted) section trace message via the incoming sts-3 data-stream. b. the ?expected? receive section trace message buffer. the ?expected? receive section trace message buffer contains the contents of the section trace messa ge that the user ?expects? to receive. the contents of this parti cular buffer is usually specified by the user. 0 ? executing a read operation to the receive section trace message buffer address space will return contents within the ?actual? receive section trace message? buffer. 1 ? executing a read operation to the receive section trace message buffer address space will return contents within the ?expected? receive section trace message buffer?. note: in the case of the receive sts-3 toh processor block, the ?receive section trace message buffer? is located at address location 0x1300 through 0x133f. 3 receive section trace message accept threshold r/w receive section trace message accept threshold: this read/write bit-field permits a user to select the number of consecutive times that the receive sts-3 toh processor block must receive a given section trace message, before it is accepted, as described below. once a given ?section trace message? has been accepted then it can be read out of the ?actual receive section trace message? buffer. 0 ? configures the receive sts-3 to h processor block to accept the incoming section trace message after it has received it the third time in succession. 1 ? configures the receive sts-3 to h processor block to accept the incoming section trace message after it has received it the fifth time in succession.
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 171 2 section trace message alignment type r/w section trace message alignment type: this read/write bit-field permits a user to specify how the receive sts-3 toh processor block will locate the boundary of the incoming section trace message within the incoming sts-3 data-stream, as indicated below. 0 ? configures the receive sts-3 toh processor block to expect the section trace message boundary to be denoted by a ?line feed? character. 1 ? configures the receive sts-3 toh processor block to expect the section trace message boundary to be denoted by the presence of a ?1? in the msb (most significant bit) of the very firs t byte (within the incoming section trace message). in this case, all of the remaining bytes (within the incoming section trace message) will each have a ?0? within their msbs. 1 - 0 receive section trace message length[1:0] r/w receive section trace message length[1:0]: these read/write bit-fields permit the user to specify the length of the section trace message that the receiv e sts-3 toh processor block will accept and load into the ?actual? re ceive section trace message buffer. the relationship between the content of thes e bit-fields and the corresponding receive section trace message length is presented below. receive section trace message length[1:0] resulting section trace message length (in terms of bytes) 00 1 byte 01 16 bytes 10/11 64 bytes
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 172 table 106: receive sts-3 transport ? receive sd burst error tolerance ? byte 1 (address location= 0x1152) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 sd_burst_tolerance[15:8] r/w r/w r/w r/w r/w r/w r/w r/w 1 1 1 1 1 1 1 1 b it n umber n ame t ype d escription 7 - 0 sd_burst_tolerance [15:8] r/w sd_burst_tolerance ? msb: these read/write bits, along with the contents of the ?receive sts-3 transport ? sd burst tolerance ? byte 0? registers permit the user to s pecify the maximum number of b2 bit errors that the receive sts-3 toh processor block can accumulate during a single sub-interval period (e.g., an sts-3 frame period), when determining whether or not to declare the sd (signal degrade) defect condition. note: the purpose of this feature is to permit the user to provide some level of b2 by te error burst filtering, when the receive sts-3 toh processor block is accumulating b2 byte errors in order to declare the sd defect condition. the user can implement this feature in order to configure the receive sts-3 toh processor block to detect b2 bit errors in multiple ?sub-interval? periods before it will declare the sd defect condition.
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 173 table 107: receive sts-3 transport ? receive sd burst error tolerance ? byte 0 (address location= 0x1153) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 sd_burst_tolerance[7:0] r/w r/w r/w r/w r/w r/w r/w r/w 1 1 1 1 1 1 1 1 b it n umber n ame t ype d escription 7 - 0 sd_burst_tolerance [7:0] r/w sd_burst_tolerance ? lsb: these read/write bits, along with the contents of the ?receive sts-3 transport ? sd burst tolerance ? byte 1? registers permit the user to s pecify the maximum number of b2 bit errors that the receive sts-3 toh processor block can accumulate during a single sub-interval period (e.g., an sts-3 frame period), when determining whether or not to declare the sd (signal degrade) defect condition. note: the purpose of this feature is to permit the user to provide some level of b2 byte error burst filtering, when the receive sts-3 toh processor block is accumulating b2 byte errors in order to declare the sd defect condition. the user can implement this feature in order to configure the receive sts-3 toh processor block to detect b2 bit errors in multiple ?sub- interval? periods before it will declare the sd defect condition.
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 174 table 108: receive sts-3 transport ? receive sf burst error tolerance ? byte 1 (address location= 0x1156) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 sf_burst_tolerance[15:8] r/w r/w r/w r/w r/w r/w r/w r/w 1 1 1 1 1 1 1 1 b it n umber n ame t ype d escription 7 - 0 sf_burst_tolerance[15:8] r/w sf_burst_tolerance ? msb: these read/write bits, along with the contents of the ?receive sts-3 transport ? sf burst tolerance ? byte 0? registers permit the user to specify the maximum number of b2 bit errors that the receive sts-3 toh processor block can accumulate during a single sub-interval period (e.g., an sts-3 frame period), when dete rmining whether or not to declare the sf (signal failure) defect condition. note: the purpose of this feature is to permit the user to provide some level of b2 byte error burst filtering, when the receive sts-3 toh processor block is accumulating b2 byte errors in order to declare the sf defect condition. the user can implement this feature in order to configure the receive sts- 3 toh processor block to detect b2 bit errors in multiple ?sub-interval? periods before it will declare the sf defect condition.
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 175 table 109: receive sts-3 transport ? receive sf burst error tolerance ? byte 0 (address location= 0x1157) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 sf_burst_tolerance[7:0] r/w r/w r/w r/w r/w r/w r/w r/w 1 1 1 1 1 1 1 1 b it n umber n ame t ype d escription 7 - 0 sf_burst_tolerance[7:0] r/w sf_burst_tolerance ? lsb: these read/write bits, along with the contents of the ?receive sts-3 transport ? sf burst tolerance ? byte 1? registers permit the user to specify the maximum number of b2 bit errors that the receive sts-3 toh processor block can accumulate during a single sub-interval period (e.g., an sts-3 frame period), when determining whether or not to declare the sf (signal failure) defect condition. note: the purpose of this feature is to permit the user to provide some level of b2 by te error burst filtering, when the receive sts-3 toh processor block is accumulating b2 byte errors in order to declare the sf defect condition. the user can implement this feature in order to confi gure the receive sts-3 toh processor block to detect b2 bit errors in multiple ?sub-interval? periods before it will declare the sf defect condition.
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 176 table 110: receive sts-3 transport ? receive sd cl ear monitor interval ? byte 2 (address location= 0x1159) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 sd_clear_monitor_window[23:16] r/w r/w r/w r/w r/w r/w r/w r/w 1 1 1 1 1 1 1 1 b it n umber n ame t ype d escription 7 - 0 sd_clear_monitor_ window[23:16] r/w sd_clear_monitor_interval ? msb: these read/write bits, along with the contents of the ?receive sts-3 transport ? sd clear monitor interval ? byte 1 and byte 0? registers permit the user to specify the length of the ?monitoring period? (in terms of ms) for sd (signal degrade) defect clearance. when the receive sts-3 toh processor block is checking the incoming sts-3 signal in order to determine if it should clear the sd defect condition, it will accumulate b2 byte errors throughout the user-specified ?sd defect clearance? monitoring period. if, during this ?sd defect clearance monitoring? period, the receive sts-3 toh processor block accumulates less b2 byte errors than that programmed into the ?receive sts-3 transport sd clear threshold? register, then the receive sts-3 toh processor block will clear the sd defect condition. notes: 1. the value that the user wr ites into these three (3) ?sd clear monitor window? registers, specifies the duration of the ?sd defect clearance monitoring period?, in terms of ms. 2. this particular register by te contains the ?msb? (most significant byte) value of the three registers that specify the ?sd defect clearance monitoring? period.
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 177 table 111: receive sts-3 transport ? receive sd cl ear monitor interval ? byte 1 (address location= 0x115a) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 sd_clear_monitor_window[15:8] r/w r/w r/w r/w r/w r/w r/w r/w 1 1 1 1 1 1 1 1 b it n umber n ame t ype d escription 7 - 0 sd_clear_monitor_window[15:8] r/w sd_clear_monitor_interval ? bits 15 through 8: these read/write bits, along with the contents of the ?receive sts-3 transport ? sd clear monitor interval ? byte 2 and byte 0? registers permit the user to specify the length of the ?monitoring period? (in terms of ms) for sd (signal degrade) defect clearance. when the receive sts-3 toh processor block is checking the incoming sts-3 signal in order to determine if it should clear the sd defect condition, it will accumulate b2 byte errors throughout the user- specified ?sd defect clearance? monitoring period. if, during this ?sd defect clearance mo nitoring period? the receive sts-3 toh processor block accumulates less b2 byte errors than that programmed into the ?receive sts-3 transport sd clear threshold? register, then the receive sts-3 toh processor block will clear the sd defect condition. note: the value that the us er writes into these three (3) ?sd clear monitor window? registers, specifies the duration of the ?sd defect clearance monitoring period?, in terms of ms.
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 178 table 112: receive sts-3 transport ? receive sd cl ear monitor interval ? byte 0 (address location= 0x115b) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 sd_clear_monitor_window[7:0] r/w r/w r/w r/w r/w r/w r/w r/w 1 1 1 1 1 1 1 1 b it n umber n ame t ype d escription 7 - 0 sd_clear_monitor_window[ 7:0] r/w sd_clear_monitor_interval ? lsb: these read/write bits, along with the contents of the ?receive sts-3 transport ? sd clear monitor interval ? byte 2 and byte 1? registers permit the user to specify the length of the ?monitoring period? (in terms of ms) for sd (signal degrade) defect clearance. when the receive sts-3 toh processor block is checking the incoming sts-3 signal in order to determine if it should clear the sd defect condition, it will accumulate b2 byte errors throughout the user-specified ?sd defect clearance? monitori ng period. if, during this ?sd defect clearance monitoring? period, the receive sts-3 toh processor block accumulates less b2 byte errors than that programmed into the ?receive sts-3 transport sd clear threshold? register, then the receive sts-3 toh processor block will clear the sd defect condition. notes: 1. the value that the user writes into these three (3) ?sd clear monitor window? registers, specifies the duration of the ?sd defect clearance monitoring period?, in terms of ms. 2. this particular register byte contains the ?lsb? (least significant byte) value of the three registers that specify the ?sd defect clearance monitoring? period.
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 179 table 113: receive sts-3 transport ? receive sf cl ear monitor interval ? byte 2 (address location= 0x115d) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 sf_clear_monitor_window[23:16] r/w r/w r/w r/w r/w r/w r/w r/w 1 1 1 1 1 1 1 1 b it n umber n ame t ype d escription 7 - 0 sf_clear_monitor_windo w [23:16] r/w sf_clear_monitor_interval ? msb: these read/write bits, along with the contents of the ?receive sts-3 transport ? sf clear monitor interval ? byte 1 and byte 0? registers permit the user to specify the length of the ?monitoring period? (in terms of ms) for sf (signal failure) defect clearance. when the receive sts-3 toh processor block is checking the incoming sts-3 signal in order to determine if it should clear the sf defect condition, it will accumulate b2 byte errors throughout the user-specified ?sf defect clearance? monitoring period. if, during this ?sf defect clearance? monitoring period, the receive sts-3 toh processor block accumulates less b2 byte errors than that programmed into the ?receive sts-3 transport sf clear threshold? register, then the receive sts-3 toh processor block will clear the sf defect condition. notes: 1. the value that the user writes into these three (3) ?sf clear monitor window registers?, specifies the duration of the ?sf defect clearance monitoring period?, in terms of ms. 2. this particular register byte contains the ?msb? (most significant byte) value fo the three registers that specify the ?sf defect clearance monitoring? period.
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 180 table 114: receive sts-3 transport ? receive sf cl ear monitor interval ? byte 1 (address location= 0x115e) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 sf_clear_monitor_window[15:8] r/w r/w r/w r/w r/w r/w r/w r/w 1 1 1 1 1 1 1 1 b it n umber n ame t ype d escription 7 - 0 sf_clear_monitor_window [15:8] r/w sf_clear_monitor_interval ? bits 15 through 8: these read/write bits, along with the contents of the ?receive sts-3 transport ? sf clear monitor interval ? byte 2 and byte 0? registers permit the user to specify the length of the ?monitoring period? (in terms of ms) for sf (signal failure) defect clearance. when the receive sts-3 toh processor block is checking the incoming sts-3 signal in order to determine if it should clear the sf defect condition, it will accumulate b2 byte errors throughout the user- specified ?sf defect clearance? monitoring period. if, during this ?sf defect clearance? monitoring period, the receive sts-3 toh processor block accumulates less b2 byte errors than that programmed into the ?receive sts-3 transport sf clear threshold? register, then the receive sts-3 toh processor block will clear the sf defect condition. notes: the value that the user writes into these three (3) ?sf clear monitor window? registers, specifies the duration of the ?sf defect clearance monitoring period?, in terms of ms.
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 181 table 115: receive sts-3 transport ? receive sf cl ear monitor interval ? byte 0 (address location= 0x115f) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 sf_clear_monitor_window[7:0] r/w r/w r/w r/w r/w r/w r/w r/w 1 1 1 1 1 1 1 1 b it n umber n ame t ype d escription 7 - 0 sf_clear_monitor_window [7:0] r/w sf_clear_monitor_interval ? lsb: these read/write bits, along with the contents of the ?receive sts-3 transport ? sf clear monitor interval ? byte 2 and byte 1? registers permit the user to specify the length of the ?monitoring period? (in terms of ms) for sf (signal failure) defect clearance. when the receive sts-3 toh processor block is checking the incoming sts-3 signal in order to determine if it should clear the sf defect condition, it will accumulate b2 byte errors throughout the user- specified ?sf defect clearance? monitoring period. if, during this ?sf defect clearance monitoring? period, the receive sts-3 toh processor block accumulates less b2 byte errors than that programmed into the ?receive sts-3 transport sf clear threshold? register, then the receive sts-3 toh processor block will clear the sf defect condition. notes: 1. the value that the user writes into these three (3) ?sf clear monitor window? registers, specifies the duration of the ?sf defect clearance monitoring? period, in terms of ms. 2. this particular register byte contains the ?lsb? (least significant byte) value of the three registers that specify the ?sf defect clearance monitoring? period.
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 182 table 116: receive sts-3 transport ? auto ais control register (address location= 0x1163) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 transmit ais-p (down- stream) upon section trace message unstable transmit ais-p (down- stream) upon section trace message mismatch transmit ais-p (down- stream) upon sf transmit ais-p (down- stream) upon sd transmit ais-p (down- stream) upon loss of optical carrier ais transmit ais-p (down- stream) upon lof transmit ais-p (down- stream) upon los transmit ais-p (down- stream) enable r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 transmit ais-p (down-stream) upon section trace message unstable r/w transmit path ais upon declarati on of the section trace message unstable defect condition: this read/write bit-field permits the user to configure the receive sts-3 toh processor block to automatically transmit the path ais (ais- p) indicator via the ?downstream? tra ffic (e.g., towards each of the three receive sonet poh processor blocks), anytime (and for the duration that) it declares the section trace message unstable defect condition within the ?incoming? sts-3 data-stream. 0 ? does not configure the receive sts-3 toh processor block to automatically transmit the ais-p indica tor (via the ?downstream? traffic) whenever (and for the duration that) it declares the ?section trace message unstable? defect condition. 1 ? configures the receive sts-3 toh processor block to automatically transmit the ais-p indi cator (via the ?downstream? traffic towards each of the three receive sonet poh processor blocks) whenever (and for the duration that) it declares the ?section trace message unstable? defect condition. note: the user must also set bit 0 (transmit ais-p enable) to ?1? to configure the receive sts-3 toh processor block to automatically transmit the ais-p indicator, in response to this defect condition. 6 transmit ais-p (down-stream) upon section trace message mismatch r/w transmit path ais (ais-p) upon declaration of the section trace message mismatch defect condition: this read/write bit-field permits the user to configure the receive sts-3 toh processor block to automatically transmit the path ais (ais- p) indicator via the ?downstream? tra ffic (e.g., towards each of the three receive sonet poh processor blo cks), anytime it declares the section trace message mismatch defect condition within the ?incoming? sts-3 data stream. 0 ? does not configure the receive sts-3 toh processor block to automatically transmit the ais-p indica tor (via the ?downstream? traffic) whenever (and for the duration that) it declares the ?section trace message mismatch? defect condition. 1 ? configures the receive sts-3 toh processor block to automatically transmit the ais-p indi cator (via the ?downstream? traffic towards each of the three receive sonet poh processor blocks) whenever (and for the duration that) it declares the ?section trace message mismatch? defect condition.
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 183 note: the user must also set bit 0 (transmit ais-p enable) to ?1? to configure the receive sts-3 toh processor block to automatically transmit the ais-p indicator, in response to this defect condition. 5 transmit ais-p (down-stream) upon sf r/w transmit path ais upon declaration of the signal failure (sf) defect condition: this read/write bit-field permits the user to configure the receive sts-3 toh processor block to automatically transmit the path ais (ais- p) indicator via the ?downstream? tra ffic (e.g., towards each of the three receive sonet poh processor blocks) , anytime it declares the sf defect condition. 0 ? does not configure the receive sts-3 toh processor block to automatically transmit the ais-p indica tor (via the ?downstream? traffic) whenever (and for the duration that) it declares the sf defect condition. 1 ? configures the receive sts-3 toh processor block to automatically transmit the ais-p indi cator (via the ?downstream? traffic towards each of the three receive sonet poh processor blocks) whenever (and for the duration that) it declares the sf defect condition. note: the user must also set bit 0 (transmit ais-p enable) to ?1? to configure the receive sts-3 toh processor block to automatically transmit the ais-p indicator, in response to this defect condition. 4 transmit ais-p (down-stream) upon sd r/w transmit path ais upon declaration of the signal degrade (sd) defect condition: this read/write bit-field permits the user to configure the receive sts-3 toh processor block to automatically transmit the path ais (ais- p) indicator via the ?downstream? tra ffic (e.g., towards each of the three receive sonet poh processor blocks) , anytime it declares the sd defect condition. 0 ? does not configure the receive sts-3 toh processor block to automatically transmit the ais-p indica tor (via the ?downstream? traffic) whenever (and for the duration that) it declares the sd defect condition. 1 ? configures the receive sts-3 toh processor block to automatically transmit the ais-p indi cator (via the ?downstream? traffic towards each of the three receive sonet poh processor blocks) whenever (and for the duration that) it declares the sd defect condition. note: the user must also set bit 0 (transmit ais-p enable) to ?1? to configure the receive sts-3 toh processor block to automatically transmit the ais-p indicator, in response to this defect condition. 3 transmit ais-p (down-stream) upon loss of optical carrier r/w transmit path ais upon loss of optical carrier condition: this read/write bit-field permits the user to configure the receive sts-3 toh processor block to automatically transmit the path ais (ais- p) indicator via the ?downstream? tra ffic (e.g., towards each of the three receive sonet poh processor blocks), anytime it detects the ?loss of optical carrier? defect condition. 0 ? does not configure the receive sts-3 toh processor block to automatically transmit the ais-p indica tor (via the ?downstream? traffic) whenever (and for the duration that) it declares the ?loss of optical carrier? defect condition. 1 ? configures the receive sts-3 toh processor block to automatically transmit the ais-p indi cator (via the ?downstream? traffic towards each of the three receive sonet poh processor blocks) whenever ( and for the duration that ) it declares the ?loss of o p tical
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 184 carrier? defect condition. note: the user must also set bit 0 (transmit ais-p enable) to ?1? to configure the receive sts-3 toh processor block to automatically transmit the ais-p indicator, in response to this defect condition. 2 transmit ais-p (down-stream) upon lof r/w transmit path ais upon declaration of the loss of frame (lof) defect condition: this read/write bit-field permits the user to configure the receive sts-3 toh processor block to automatically transmit the path ais (ais- p) indicator via the ?downstream? tra ffic (e.g., towards each of the three receive sonet poh processor block) , anytime it declares the lof defect condition. 0 ? does not configure the receive sts-3 toh processor block to automatically transmit the ais-p indica tor (via the ?downstream? traffic) whenever (and for the duration that) it declares the lof defect condition. 1 ? configures the receive sts-3 toh processor block to automatically transmit the ais-p indi cator (via the ?downstream? traffic towards each of the three receive sonet poh processor blocks) whenever (and for the duration that) it declares the lof defect condition. note: the user must also set bit 0 (transmit ais-p enable) to ?1? to configure the receive sts-3 toh processor block to automatically transmit the ais-p indicator, in response to this defect condition. 1 transmit ais-p (down-stream) upon los r/w transmit path ais upon loss of signal (los): this read/write bit-field permits the user to configure the receive sts-3 toh processor block to automatically transmit the path ais (ais- p) indicator via the ?downstream? tra ffic (e.g., towards each of the three receive sonet poh processor blo ck), anytime it declares the los defect condition. 0 ? does not configure the receive sts-3 toh processor block to automatically transmit the ais-p indica tor (via the ?downstream? traffic) whenever (and for the duration that) it declares the los defect condition. 1 ? configures the receive sts-3 toh processor block to automatically transmit the ais-p indi cator (via the ?downstream? traffic towards each of the three receive sonet poh processor blocks) whenever (and for the duration that) it declares the los defect condition. note: the user must also set bit 0 (transmit ais-p enable) to ?1? to configure the receive sts-3 toh processor block to automatically transmit the ais-p indicator, in response to this defect condition. 0 transmit ais-p (down-stream) enable r/w automatic transmission of ais-p enable: this read/write bit-field serves two purposes. it permits the user to configure the receive sts-3 toh processor block to automatically transmit the path ai s (ais-p) indicator, via the down- stream traffic (e.g., towards each of the three receive sonet poh processor blocks), upon declaration of either the sf, sd, section trace message mismatch, section trace message unstable, lof, los or loss of optical carrier defect conditions. it also permits the user to configure the receive sts-3 toh processor block to automaticall y transmit a path ais ( ais-p ) indicator via the
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 185 ?downstream? traffic (e.g ., towards each of the three receive sonet poh processor blocks) anytime (and for the duration t hat) it declares the ais-l defect condition within the ?incoming ? sts-3 data-stream. 0 ? configures the receive sts-3 toh processor block to not automatically transmit the ais-p indica tor (via the ?downstream? traffic) whenever the receive sts-3 toh processor block declares the ais-l or any other of the ?above-me ntioned? defect conditions. 1 ? configures the receive sts-3 toh processor block to automatically transmit the ais-p indi cator (via the ?downstream? traffic towards each of the three receive sonet poh processor blocks) whenever (and for the duration that ) the receive sts-3 toh processor block declares the ais-l, sd, sf, lof, los, section trace message mismatch, section trace message unstable or loss of optical carrier defect condition). note: the user must also set the corresponding bit-fields (within this register) to ?1? in order to configure the receive sts-3 toh processor block to automatically transmit the ais-p indicator upon detection of a giv en alarm/defect condition.
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 186 table 117: receive sts-3 transport ? serial port control register (address location= 0x1167) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 unused rxtoh_clock_speed[3:0] r/o r/o r/o r/o r/w r/w r/w r/w 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 - 4 unused r/o 3 - 0 rxtoh_clock_speed[7:0] r/w rxtohclk output clock signal speed: these read/write bit-fields permit the user to specify the frequency of the ?rxtohclk output clock signal. the formula that relates the contents of these register bits to the ?rxtohclk? frequency is presented below. freq = 19.44 /[2 * (rxtoh_clock_speed + 1) note: for sts-3/stm-1 applications, the frequency of the rxtohclk output signal mu st be in the range of 0.6075mhz to 9.72mhz
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 187 table 118: receive sts-3 transport ? auto ais (in downstream sts-1s) control register (address location= 0x116b) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 unused unused transmit ais-p/ais (via downstream sts-1s/ ds3s) upon los transmit ais-p/ais (via downstream sts-1s/ ds3s) upon lof transmit ais-p/ais (via downstream sts-1s/ ds3s) upon sd transmit ais-p/ais (via downstream sts-1s/ ds3s) upon sf ais-l output enable transmit ais-p/ais (via downstream sts-1s/ ds3s) enable r/o r/o r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 - 6 unused r/o 5 transmit ais-p/ais (via downstream sts- 1s/ds3s) upon los r/w transmit ais-p (via downstream sts-1s) upon declaration of the los (loss of signal) defect condition/transmit ds3 ais (via downstream ds3s) upon declaration of the los defect condition: the exact function of this bit-field depends upon whether the XRT94L33 device has been configured to handle sts-1 or ds3 signals, on the ?low- speed? side of the chip, as described below. for those channels that are configured to operate in the sts-1 mode: this read/write bit-field permits the user to configure all of the active transmit sts-1 poh processor blocks (within the XRT94L33 device) to automatically transmit the ais-p (path ais) indicator via the ?downstream? sts-1 signals, anytim e (and for the duration that) the receive sts-3 toh processor block declares the los defect condition. 0 ? does not configure all ?activ ated? transmit sts-1 poh processor blocks to automatically transmit the ais-p indicator via the ?downstream? sts-1 signals, anytime the receive sts-3 toh processor block declares the los defect condition. 1 ? configures all ?act ivated? transmit sts-1poh processor blocks to automatically transmit the ais-p indicator via the ?downstream? sts-1 signals, anytime (and for the duration that) the receive sts-3 toh processor block declares the los defect condition. note: 1. in the ?long-run? the function of this bit-field is exactly the same as that of bit 1 (transmit ais-p down-stream ? upon los), within the receive sts-3 transport ? auto ais control register (address location= 0x1163). the only difference is that this register bit will cause each of the ?downstream? transmit st s-1 poh processor blocks to immediately begin to transmit the ais-p condition whenever the receive sts-3 toh processor block declares the los defect. this will permit the user to easily comply with the telcordia gr-253-core requirements of an ne transmitting the ais-p indicator downstream within 125us of the ne declaring the los defect. 2. in the case of bit 1 (trans mit ais-p downstream ? upon los), several sonet frame p eriods are re q uired ( after the receive sts - 3
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 188 toh processor block has declared the los defect), bef ore the transmit sts-1 poh processor blocks will begin the process of transmitting the ais-p indicators. 3. in addition to setting this bit-field to ?1?, the user must also set bit 0 (transmit ais-p via downstream sts-1s enable) within this register, in order enable this feature. for those channels that are configured to operate in the ds3 mode: this read/write bit-field permits the user to configure all of the active ds3/e3 framer blocks (within the XRT94L33 device) to automatically transmit the ds3 ais indicator vi a their ?downstream? (or egress direction) ds3 signals, anytime (and for the duration that) the receive sts-3 toh processor block declares the los defect condition. 0 ? does not configure all ?act ive? ds3/e3 framer blocks to automatically transmit the ds3 ais indicator via their ?downstream? ds3 signals, anytime the receive sts-3 toh processor block declares the los defect condition. 1 ? configures all ?act ive? ds3/e3 framer blocks to automatically transmit the ds3 ais indicator via their ?downstream? ds3 signals, anytime (and for the duration that) the receive sts-3 toh processor block declares the los defect condition. note: in addition to setting this bit-fiel d to ?1?, the user must also set bit 0 (transmit ais-p/ais via downstream sts-1s/ds3s enable) within this register, in order to enable this feature. 4 transmit ais-p/ais (via downstream sts- 1s/ds3s) upon lof r/w transmit ais-p (via downstream sts-1s) upon declaration of the lof (loss of frame) defect condition/transmit ds3 ais (via downstream ds3s) upon declaration of the lof defect condition: the exact function of this bit-field depends upon whether the XRT94L33 device has been configured to handle sts-1 or ds3 signals, on the ?low- speed? side of the chip, as described below. for those channels that are configured to operate in the sts-1 mode: this read/write bit-field permits the user to configure all of the active transmit sts-1 poh processor blocks (within the XRT94L33 device) to automatically transmit the ais-p (path ais) indicator via the ?downstream? sts-1 signals, anytim e (and for the duration that) the receive sts-3 toh processor block declares the lof defect condition. 0 ? does not configures all ?activ ated? transmit sts-1 poh processor blocks to automatically transmit the ais-p indicator via the ?downstream? sts-1 signals, anytime the receive sts-3 toh processor block declares the lof defect condition. 1 ? configures all ?act ivated? transmit sts-1poh processor blocks to automatically transmit the ais-p indicator via the ?downstream? sts-1 signals, anytime (and for the duration that) the receive sts-3 toh processor block declares the lof defect condition. note: 1. in the ?long-run? the function of this bit-field is exactly the same as that of bit 2 (transmit ais-p down-stream ? upon lof), within the receive sts-3 transport ? auto ais control register (address location= 0x1163). the only difference is that this register bit will cause each of the ?downstream? transmit st s-1 poh processor blocks to immediately begin to transmit the ais-p condition whenever the receive sts-3 toh processor block de clares the lof defect. this will permit the user to easily comply with the telcordia gr-253-core re q uirements of an ne transmittin g the ais - p indicator downstream
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 189 within 125us of the ne declaring the lof defect. 2. in the case of bit 2 (transmit ais-p downstream ? upon lof), several sonet frame periods are required (after the receive sts-3 toh processor block has declared the los defect), bef ore the transmit sts-1 poh processor blocks will begin the process of transmitting the ais-p indicators. 3. in addition to setting this bit-field to ?1?, the user must also set bit 0 (transmit ais-p via downstream sts-1s enable) within this register, in order enable this feature. for those channels that are configured to operate in the ds3 mode: this read/write bit-field permits the user to configure all of the active ds3/e3 framer blocks (within the XRT94L33 device) to automatically transmit the ds3 ais indicator via the ?downstream? (or egress direction) ds3 signals, anytime (and for the duration that) the receive sts-3 toh processor block declares the lof defect condition. 0 ? does not configure all ?act ive? ds3/e3 framer blocks to automatically transmit the ds3 ais indicator via the ?downstream? ds3 signals, anytime the receive sts-3 toh processor block declares the lof defect condition. 1 ? configures all ?act ive? ds3/e3 framer blocks to automatically transmit the ds3 ais indicator via the ?downstream? ds3 signals, anytime (and for the duration that) the receive sts-3 toh processor block declares the lof defect condition. note: in addition to setting this bit-fiel d to ?1?, the user must also set bit 0 (transmit ais-p/ais via downstream sts-1s/ds3s enable) within this register, in order to enable this feature. 3 transmit ais-p/ais (via downstream sts- 1s/ds3s) upon sd r/w transmit ais-p (via downstream sts-1s) upon declaration of the sd (signal degrade) defect condition/transmit ds3 ais (via downstream ds3s) upon declaration of the sd defect condition: the exact function of this bit-field depends upon whether the XRT94L33 device has been configured to handle sts-1 or ds3 signals, on the ?low- speed? side of the chip, as described below. for those channels that are configured to operate in the sts-1 modes: this read/write bit-field permits the user to configure all of the active transmit sts-1 poh processor blocks (within the XRT94L33 device) to automatically transmit the ais-p (path ais) indicator via the ?downstream? sts-1 signals, anytim e (and for the duration that) the receive sts-3 toh processor block declares the sd defect condition. 0 ? does not configures all ?activ ated? transmit sts-1 poh processor blocks to automatically transmit the ais-p indicator via the ?downstream? sts-1 signals, anytime the receive sts-3 toh processor block declares the sd defect condition. 1 ? configures all ?act ivated? transmit sts-1poh processor blocks to automatically transmit the ais-p indicator via the ?downstream? sts-1 signals, anytime (and for the duration that) the receive sts-3 toh processor block declares the sd defect condition. note: 1. in the ?long-run? the function of this bit-field is exactly the same as that of bit 4 (transmit ais-p down-strea m ? upon sd), within the receive sts-3 transport ? auto ais control register (address location= 0x1163). the only difference is that this register bit will cause each of the ?downstream? transmit sts - 1 po h processor blocks to
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 190 immediately begin to transmit the ais-p condition whenever the receive sts-3 toh processor block declares the sd defect. this will permit the user to easily comply with the telcordia gr-253-core requirements of an ne transmitting the ais-p indicator downstream within 125us of the ne declaring the los defect. 2. in the case of bit 1 (transmit ais-p downstream ? upon lof), several sonet frame periods are required (after the receive sts-3 toh processor block has declared the sd defect), before the transmit sts-1 poh processor blocks will begin the process of transmitting the ais-p indicators. 3. in addition to setting this bit-field to ?1?, the user must also set bit 0 (transmit ais-p via downstream sts-1s enable) within this register, in order enable this feature. for those channels that are configured to operate in the ds3 mode: this read/write bit-field permits the user to configure all of the active ds3/e3 framer blocks (within the XRT94L33 device) to automatically transmit the ds3 ais indicator via the ?downstream? (or egress direction) ds3 signals, anytime (and for the duration that) the receive sts-3 toh processor block declares the sd defect condition. 0 ? does not configure all ?active? ds3/e3 framer block s to automatically transmit the ds3 ais indicator via the ?downstream? ds3 signals, anytime the receive sts-3 toh processor block declares the sd defect condition. 1 ? configures all ?act ive? ds3/e3 framer blocks to automatically transmit the ds3 ais indicator via the ?downstream? ds3 signals, anytime (and for the duration that) the receive sts-3 toh processor block declares the sd defect condition. note: in addition to setting this bit-field to ?1? the user must also set bit 0 (transmit ais-p/ais via downstream sts-1s/ds3s enable) within this register, in order to enable this feature. 2 transmit ais-p/ais (via downstream sts- 1s/ds3s) upon sf r/w transmit ais-p (via downstream sts-1s) upon declaration of the signal failure (sf) defect condition/transmit ds3 ais (via downstream ds3s) upon declaration of the sf defect condition: the exact function of this bit-field depends upon whether the XRT94L33 device has been configured to handle sts-1 or ds3 signals, on the ?low- speed? side of the chip, as described below. for those channels that are configured to operate in the sts-1 mode: this read/write bit-field permits the user to configure all of the active transmit sts-1 poh processor blocks (within the XRT94L33 device) to automatically transmit the ais-p (path ais) indicator via the ?downstream? sts-1 signals, anytim e (and for the duration that) the receive sts-3 toh processor block declares the sf defect condition. 0 ? does not configures all ?activ ated? transmit sts-1 poh processor blocks to automatically transmit the ais-p indicator via the ?downstream? sts-1 signals, anytime the receive sts-3 toh processor block declares the sf defect condition. 1 ? configures all ?act ivated? transmit sts-1poh processor blocks to automatically transmit the ais-p indicator via the ?downstream? sts-1 signals, anytime (and for the duration that) the receive sts-3 toh processor block declares the sf defect condition. notes: 1. in the ?lon g -run? the function of this bi t - field is exactl y the same as that
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 191 of bit 5 (transmit ais-p down-strea m ? upon sf), within the receive sts-3 transport ? auto ais control register (address location= 0x1163). the only difference is that this register bit will cause each of the ?downstream? transmit st s-1 poh processor blocks to immediately begin transmit the ais- p condition whenever the receive sts-3 toh processor block declares the sf defect. this will permit the user to easily comply with the telcordia gr-253-core requirements of an ne transmitting the ais-p indicator downstream within 125us of the ne declaring the sf defect. 2. in the case of bit 5 (transmit ai s-p downstream ? upon sf), several sonet frame periods are requir ed (after the receive sts-3 toh processor block has declared the sf defect), before the transmit sts-1 poh processor blocks will begin the process of transmitting the ais-p indicators. 3. in addition to setting this bit-field to ?1?, the user must also set bit 0 (transmit ais-p via downstream sts-1s enable) within this register, in order enable this feature. for those channels that are configured to operate in the ds3 mode: this read/write bit-field permits the user to configure all of the active ds3/e3 framer blocks (within the XRT94L33 device) to automatically transmit the ds3 ais indicator via the ?downstream? (or egress direction) ds3 signals, anytime (and for the duration that) the receive sts-3 toh processor block declares the sf defect condition. 0 ? does not configure all ?act ive? ds3/e3 framer blocks to automatically transmit the ds3 ais indicator via the ?downstream? ds3 signals, anytime the receive sts-3 toh processor block declares the sf defect condition. 1 ? configures all ?act ive? ds3/e3 framer blocks to automatically transmit the ds3 ais indicator via the ?downstream? ds3 signals, anytime (and for the duration that) the receive sts-3 toh processor block declares the sf defect condition. note: in addition to setting this bit-field to ?1?, the user must also set bit 0 (transmit ais-p/ais via downstream sts-1s/ds3s enable) within this register, in order to enable this feature. 1 ais-l output enable r/w ais-l output enable: this read/write bit-field, along with bits 7 (8khz or stuff out enable) within the ?operation output control register ? byte 1? (address location= 0x0150) permit the user to configure the ?ais-l? indicator to be output via the ?lof? output pin (pin ad11). if bit 7 (within the ?operation output control register ? byte 1?) is set to ?0?, then setting this bit-field to ?1? configures pin ad11 to function as the ais-l output indicator. if bit 7 (within the ?operation output control register ? byte 1?) is set to ?0?, then setting this bit-field to ?0? configures pin ad11 to function as the lof output indicator. if bit 7 (within the ?operation output c ontrol register ? byte 1) is set to ?1?, then this register bit is ignored. 0 transmit ais-p/ais (via downstream sts-1s/ ds3s) enable r/w automatic transmission of ais-p/ais (via the downstream sts-1s or ds3s) enable: the exact function of this bit-field depends upon whether the XRT94L33 device has been configured to handle sts-1 or ds3 signals, on the ?low- speed? side of the chip, as described below. for those channels that are confi g ured to o p erate in the sts-1
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 192 mode: this read/write bit-field permits the user to configure all ?activated? transmit sts-1 poh processor blocks to automatically transmit the ais- p indicator, via its ?outbound? sts-1 signals, upon detection of an sf, sd, los, lof and ais-l defect conditions. 0 ? does not configure the ?activ ated? transmit sts-1 poh processor blocks to automatically transmit the ais-p indicator, whenever (and for the duration that) the receive st s-3 toh processor block declares either the los, lof, sd, sf or ais defect condition. 1 ? configures the ?act ivated? transmit sts-1 poh processor blocks to automatically transmit the ais-p indicator (via their downstream signal paths), whenever (and for the durat ion that) the receive sts-3 toh processor block declares either the los, lof, sd, sf or ais-l defect conditions. notes: 1. the user must also set the corresponding bit-fields (within this register) to ?1? in order to configure all ?active? transmit sts-1 toh processor blocks to automatically transmit the ais-p indicator (downstream) whenever (and for the duration that) the receive sts-3 toh processor block declares the los, lof, sd or sf defect conditions. 2. setting this particular bit-field to ?1? will also configure all ?active? transmit sts-1 toh proc essor blocks to automatically transmit the ais-p indicator (d ownstream) whenever (and for the duration that) the receiv e sts-3 toh processor block declares the ais-l defect condition. for those channels that are configured to operate in the ds3 mode: this read/write bit-field permits the user to configure all of the active ds3/e3 framer blocks (within the XRT94L33 device) to automatically transmit the ds3 ais indicator via the ?downstream? (or egress direction) ds3 signals, anytime (and for the duration that) the receive sts-3 toh processor block declares the los, lof, sd, sf or ais-l defect conditions. 0 ? does not configure all ?act ive? ds3/e3 framer blocks to automatically transmit the ds3 ais indicator via their ?downstream? ds3 signals, anytime the receive sts-3 toh processor block declares either the los, lof, sd, sf or ais-l defect conditions. 1 ? configures all ?act ive? ds3/e3 framer blocks to automatically transmit the ds3 ais indicator via their ?downstream? ds3 signals, anytime (and for the duration that) the receive sts-3 toh processor block declares either the los, lof, sd, sf or ais-l defect conditions. notes: 1. the user must also set the corresponding bit-fields (within this register) to ?1? in order to conf igure all ?active? ds3/e3 framer blocks to automatically trans mit the ds3 ais indicator (downstream) whenever (and for the duration that) the receive sts-3 toh processor block declares the los, lof, sd or sf defect conditions. 2. setting this particular bit-field to ?1? will also configure all ?active? ds3/e3 framer blocks to automatically transmit the ds3 ais indicator (downstream) whenever (and for the duration that) the receive sts-3 toh processor block declares the ais- l defect condition.
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 193 1.5 receive sts-3c poh processor block the register map for the receive sts-3c poh processor block is presented in the table below. additionally, a detailed description of each of the ?receive sts-3c poh processor? block registers is presented below. in order to provide some orientation for the reader, an illustration of the functional block diagram for the XRT94L33, with the ?receive sts-3c poh processor block ?highlighted? is pr esented below in figure 2. it should be noted that for mapper aggregation applic ations, the receive sts-3c poh processor block is only active if the user has configured the XRT94L33 device to handle sts-3c data via sts-1 telecom bus interface # 1. the receive sts-3c poh processor block is also active if the user configures the XRT94L33 device to operate in the ?atm uni? or ?ppp packet ov er sts-3c? mode. for deta ils on XRT94L33 device operate in the atm or ppp mode, the user should co nsult the ?XRT94L33 regist er map/description for atm/ppp applications? document. figure 2: illustration of the function al block diagram of the xrt94l 33, with the receive sts-3c poh processor block ?high-lighted?. receive sts-1 toh processor block receive sts-1 toh processor block receive sts-1 poh processor block receive sts-1 poh processor block transmit sts-1 poh processor block transmit sts-1 poh processor block transmit sts-1 toh processor block transmit sts-1 toh processor block receive sonet poh processor block receive sonet poh processor block transmit sonet poh processor block transmit sonet poh processor block transmit sts-3 toh processor block transmit sts-3 toh processor block receive sts-3 toh processor block receive sts-3 toh processor block transmit sts-1 telecom bus interface block transmit sts-1 telecom bus interface block receive sts-1 telecom bus interface block receive sts-1 telecom bus interface block receive sts-3 telecom bus interface block receive sts-3 telecom bus interface block transmit sts-3 telecom bus interface block transmit sts-3 telecom bus interface block clock synthesizer block clock synthesizer block clock & data recovery block clock & data recovery block transmit sts-3 pecl interface block transmit sts-3 pecl interface block receive sts-3 pecl interface block receive sts-3 pecl interface block to channels 1 & 2 from channels 1 & 2 channel 0 ds3/e3 framer block ds3/e3 framer block ds3/e3 jitter attenuator block ds3/e3 jitter attenuator block ds3/e3 mapper block ds3/e3 mapper block
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 194 1.5.1 receive sts-3 c poh processor block register table 119: receive sts-3c poh processor block register - address map a ddress l ocation r egister n ame d efault v alues 0x1000 ? 0x1181 reserved 0x00 0x1182 receive sts-3c path ? control register ? byte 1 0x00 0x1183 receive sts-3c path ? control register ? byte 0 0x00 0x1184, 0x1185 reserved 0x00 0x1186 receive sts-3c path ? status register ? byte 1 0x00 0x1187 receive sts-3c path ? status register ? byte 0 0x00 0x1188 reserved 0x00 0x1189 receive sts-3c path ? interrupt status register ? byte 2 0x00 0x118a receive sts-3c path ? interrupt status register ? byte 1 0x00 0x118b receive sts-3c path ? interrupt status register ? byte 0 0x00 0x118c reserved 0x00 0x118d receive sts-3c path ? interrupt enable register ? byte 2 0x00 0x118e receive sts-3c path ? interrupt enable register ? byte 1 0x00 0x118f receive sts-3c path ? interrupt enable register ? byte 0 0x00 0x1190 ? 0x1192 reserved 0x00 0x1193 receive sts-3c path ? sonet receive rdi-p register 0x00 0x1194, 0x1195 reserved 0x00 0x1196 receive sts-3c path ? received path label byte (c2) register 0x00 0x1197 receive sts-3c path ? expected path label byte (c2) register 0x00 0x1198 receive sts-3c path ? b3 error count register ? byte 3 0x00 0x1199 receive sts-3c path ? b3 error count register ? byte 2 0x00 0x119a receive sts-3c path ? b3 error count register ? byte 1 0x00 0x119b receive sts-3c path ? b3 error count register ? byte 0 0x00 0x119c receive sts-3c path ? rei-p error count register ? byte 3 0x00 0x119d receive sts-3c path ? rei-p error count register ? byte 2 0x00 0x119e receive sts-3c path ? rei-p error count register ? byte 1 0x00 0x119f receive sts-3c path ? rei-p error count register ? byte 0 0x00 0x11a0 ? 0x11a2 reserved 0x00 0x11a3 receive sts-3c path ? receive j1 byte control register 0x00
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 195 a ddress l ocation r egister n ame d efault v alues 0x11a4, 0x11a5 reserved 0x00 0x11a6 receive sts-3c path ? pointer value register ? byte 1 0x00 0x11a7 receive sts-3c path ? pointer value register ? byte 0 0x00 0x11a8 ? 0x11aa reserved 0x00 0x11ab receive sts-3c path ? loss of pointe r ? concatenation status register 0x00 0x11ac ? 0x11b2 reserved 0x00 0x11b3 receive sts-3c path ? ais - c oncatenation status register 0x00 0x11b4 ? 0x11ba reserved 0x00 0x11bb receive sts-3c path ? auto ais control register 0x00 0x11bc ? 0x11be reserved 0x00 0x11bf receive sts-3c path ? serial port control register 0x00 0x11c0 ? 0x11c2 reserved 0x00 0x11c3 receive sts-3c path ? sonet receive auto alarm register ? byte 0 0x00 0x11c4 ? 0x11d2 reserved 0x00 0x11d3 receive sts-3c path ? receive j1 byte capture register 0x00 0x11d4 ? 0x11d6 reserved 0x00 0x11d7 receive sts-3c path ? receive b3 byte capture register 0x00 0x11d8 ? 0x11da reserved 0x00 0x11db receive sts-3c path ? receive c2 byte capture register 0x00 0x11dc ? 0x11de reserved 0x00 0x11df receive sts-3c path ? receive g1 byte capture register 0x00 0x11e0 ? 0x11e2 reserved 0x00 0x11e3 receive sts-3c path ? receive f2 byte capture register 0x00 0x11e4 ? 0x11e6 reserved 0x00 0x11e7 receive sts-3c path ? receive h4 byte capture register 0x00 0x11e8 ? 0x11ea reserved 0x00 0x11eb receive sts-3c path ? receive z3 byte capture register 0x00 0x11ec ? 0x11ee reserved 0x00 0x11ef receive sts-3c path ? receive z4 (k3) byte capture register 0x00 0x11f0 ? 0x11f2 reserved 0x00 0x11f3 receive sts-3c path ? receive z5 byte capture register 0x00
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 196 a ddress l ocation r egister n ame d efault v alues 0x11f4 ? 0x11ff reserved
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 197 1.5.2 receive sts-3 c poh processor block register description table 120: receive sts-3c path ? control register ? byte 0 (address location= 0x1183) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 unused check stuff rdi-p type rei-p error type b3 error type r/o r/o r/o r/o r/w r/w r/w r/w 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 ? 4 unused r/o 3 check stuff r/w check (pointer adjustment) stuff select: this read/write bit-field permits the user to enable/disable the sonet standard recommendation that a pointer increment or decrement operation, detected within 3 sonet frames of a previous pointer adjustment operation (e.g., negative stuff, pos itive stuff) is ignored. 0 ? disables this sonet standard impl ementation. in this mode, all pointer-adjustment operations that are detected will be accepted. 1 ? enables this ?sonet standard? im plementation. in this mode, all pointer-adjustment operations that are detected within 3 sonet frame periods of a previous pointer-adj ustment operation will be ignored. 2 rdi-p type r/w path ? remote defect indicator type select: this read/write bit-field permits the user to configure the receive sts- 3c poh processor block to support either the ?single-bit? or the ?enhanced? rdi-p form of signaling, as described below. 0 ? configures the receive sts-3c poh processor block to support the single-bit rdi-p. in this mode, the receive sts-3c poh processor block will only monitor bit 5, within the g1 byte (of incoming spe data), in order to declare and clear the rdi-p defect condition. 1 ? configures the receive sts-3c poh processor block to support the enhanced rdi-p (erdi-p). in th is mode, the receive sts-3c poh processor block will monitor bits 5, 6 and 7, within the g1 byte, in order to declare and clear the rdi-p defect condition. 1 rei-p error type r/w rei-p error type: this read/write bit-field permits the user to specify how the ?receive sts-3c poh processor block will count (or tally) rei-p events, for performance monitoring purposes. the user can configure the receive sts-3c poh processor block to incr ement rei-p events on either a ?per- bit? or ?per-frame? basis. if the user configures the receive sts-3c poh processor block to increment rei-p events on a ?per-bit? basis, then it will increment the receive sts-3c path rei-p error count? register by the value of the lower nibble within the g1 byte of the incoming sts-3c data- stream. if the user configure the receive sts-3c poh processor block to increment rei-p events on a ?per-frame ? basis, then it will increment the ?receive sts-3c path ? rei-p error coun t? register each time it receives an sts-3c spe, in which the lower-nibbl e of the g1 byte (bits 1 through 4) are set to a ?non-zero? value. 0 ? configures the receive sts-3c poh processor block to count or tally rei-p events on a per-bit basis.
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 198 1 ? configures the receive sts-3c poh processor block to count or tally rei-p events on a ?per-frame? basis. 0 b3 error type r/w b3 error type: this read/write bit-field permits the user to specify how the ?receive sts-3c poh processor block will coun t (or tally) b3 byte errors, for performance monitoring purposes. the user can configure the receive sts-3c poh processor block to increment b3 byte errors on either a ?per- bit? or ?per-frame? basis. if the user configures the receive sts-3c poh processor block to increment b3 byte errors on a ?per-bit? basis, then it will increment the ?receive sts-3c path - b3 byte error count? register by the number of bits (within the b3 byte value of the incoming sts-3c data- stream) that is in error. if the user configures the receive sts-3c poh processor block to increment b3 byte errors on a ?per-frame? basis, then it will increment the ?receive sts-3c path ? b3 byte erro r count? register each time that it receives an sts-3c spe that contains an erred b3 byte. 0 ? configures the receive sts-3c po h processor block to count b3 byte errors on a ?per-bit? basis. 1 ? configures the receive sts-3c po h processor block to count b3 byte errors on a ?per-frame? basis.
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 199 table 121: receive sts-3c path ? receive status register ? byte 1 (address location= 0x1186) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 unused path trace message unstable defect declared r/o r/o r/o r/o r/o r/o r/o r/o 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 ? 1 unused r/o 0 path trace message unstable defect declared r/o path trace message unstable defect declared: this read-only bit-field indicates wh ether or not the receive sts-3c poh processor block is currently declaring the path trace message unstable defect condition. the receive sts-3c poh processor block will declare the path trace message unstable defect condition, whenever the ?path trace message unstable? counter reaches the value ?8?. the ?path trace message unstable? counter will be incremented for each time th at it receives a path trace message that differs from the previously re ceived message. the ?path trace message unstable? counter is cleared to ?0? whenever the receive sts-3c poh processor block has received a given path trace message 3 (or 5) consecutive times. note: receiving a given path trace message 3 (or 5) consecutive times also sets this bit-field to ?0?. 0 ? indicates that the receive sts-3c poh processor block is not currently declaring the path trace mess age unstable defect condition. 1 ? indicates that the receive sts-3c poh processor block is currently declaring the path trace mess age unstable defect condition.
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 200 table 122: receive sts-3c path ? sonet receive status register ? byte 0 (address location= 0x1187) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 tim-p defect declared c2 byte unstable defect declared uneq-p defect declared plm-p defect declared rdi-p defect declared rdi-p unstable condition lop-p defect declared ais-p defect declared r/o r/o r/o r/o r/o r/o r/o r/o 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 tim-p defect declared r/o trace identification mismatch (tim-p) defect indicator: this read-only bit-field indicates wh ether or not the receive sts-3c poh processor block is currently declaring the ?path trace ident ification mismatch? (tim-p) defect condition. the receive sts-3c poh processor bl ock will declare the ?tim-p? defect condition, when none of the received 64 -byte string (received via the j1 byte, within the incoming sts-3c data-stream ) matches the expected 1, 16 or 64- byte message. the receive sts-3c poh processor block will clear the ?tim-p? defect condition, when 80% of the received 1, 16 or 64-byte string (received via the j1 byte) matches the expected 1, 16 or 64-byte message. 0 ? indicates that the receive sts-3c poh processor block is not currently declaring the tim-p defect condition. 1 ? indicates that the receive sts-3c poh processor block is currently declaring the tim-p defect condition. 6 c2 byte unstable defect declared r/o c2 byte (path signal label byte) unstable defect declared: this read-only bit-field indicates wh ether or not the receive sts-3c poh processor block is currently declaring the ?path signal label byte? unstable defect condition. the receive sts-3c poh processor block will declare the c2 (path signal label byte) unstable defect conditio n, whenever the ?c2 byte unstable? counter reaches the value ?5?. the ?c2 byte unstable? counter will be incremented for each time that it re ceives an sts-3c spe with a c2 byte value that differs from the previously received c2 byte value. the ?c2 byte unstable? counter is cleared to ?0? whenever the receive sts-3c poh processor block has received 3 (or 5) consecutive sts-3c spes that each contain the same c2 byte value. note: receiving a given c2 byte value in 3 (or 5) consecutive spes also sets this bit-field to ?0?. 0 ? indicates that the receive sts-3c poh processor block is currently not declaring the c2 (path signal label byte) unstable defect condition. 1 ? indicates that the receive sts-3c poh processor block is currently declaring the c2 (path signal label byte) unstable defect condition. 5 uneq-p defect declared r/o path ? unequipped indicator (uneq-p) defect declared: this read-only bit-field indicates wh ether or not the receive sts-3c poh processor block is currently declari ng the uneq-p defect condition. the receive sts-3c poh processor bloc k will declare the uneq-p defect condition anytime that it re ceives at least five (5) consecutive sts-3c frames, in which the c2 b y te was set to 0x00 ( which indicates that the sts-3c spe is
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 201 ?unequipped?). the receive sts-3c poh processor block will clear the uneq-p defect condition, if it receives at least five (5) consecutive sts-3c frames, in which the c2 byte was set to a value other than 0x00. 0 ? indicates that the receive sts-3c poh processor block is currently not declaring the uneq-p defect condition. 1 ? indicates that the receive sts-3c poh processor block is currently declaring the uneq-p defect condition. note: 1. the receive sts-3c poh processo r block will not declare the uneq-p defect condition if it configured to expe ct to receive sts-3c frames with c2 bytes being set to ?0x00? (e.g., if the ?receive sts-3c path ? expected path label value? register is set to ?0x00?). 2. the address locations of the ?r eceive sts-3c path ? expected path label value? register is 0x1197 4 plm-p defect declared r/o path payload mismatch indicator (plm-p) defect declared: this read-only bit-field indicates wh ether or not the receive sts-3c poh processor block is currently decl aring the plm-p defect condition. the receive sts-3c poh processor block will declare the plm-p defect condition, if it receives at least five (5) consecutive sts-3c frames, in which the c2 byte was set to a value other than t hat which it is expecting to receive. whenever the receive sts-3c poh proc essor block is determining whether or not it should declare the plm-p defect, it will check the contents of the following two registers. ? the ?receive sts-3c path ? received path label value? register (address location = 0x1196) ? the ?receive sts-3c path ? expected path label value? register (address location = 0x1197) the ?receive sts-3c path ? expected path label value? register contains the value of the c2 byte s, that the receive sts- 3c poh processor blocks expects to receive. the ?receive sts-3c path ? received path label value? register contains the value of the c2 byte, that the re ceive sts-3c poh processor block has most received ?validated? (by receiving this same c2 byte in five consecutive sonet frames). the receive sts-3c poh processor block will declare the plm-p defect condition if the contents of these two register do not match. the receive sts-3c poh processor block will clear the plm-p defect condition if whenever the contents of t hese two registers do match. 0 ? indicates that the receive sts-3c poh processor block is currently not declaring the plm-p defect condition. 1 ? indicates that the receive sts-3c poh processor block is currently declaring the plm-p defect condition. note: the receive sts-3c poh processor block will clear the plm-p defect, upon declaring the un eq-p defect condition. 3 rdi-p defect declared r/o path remote defect indicator (rdi-p) defect declared: this read-only bit-field indicates wh ether or not the receive sts-3c poh processor block is currently declaring the rdi-p defect condition. if the receive sts-3c poh processor block is configured to support the ?single-bit rdi-p? function, then it will de clare the rdi-p defect condition if bit 5 ( within the g1 b y te of the incomin g sts-3c frame ) is set to ?1? for ?rdi-
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 202 p_thrd? number of incoming consecutive sts-3c spes. if the receive sts-3c poh processor block is configured to support the enhanced rdi-p? (erdi-p) function, t hen it will declare the rdi-p defect condition if bits 5, 6 and 7 (within the g1 byte of the incoming sts-3c frame) are set to [0, 1, 0], [1, 0, 1] or [1, 1, 0] for ?rdi-p_thrd? number of consecutive sts-3c spes. 0 ? indicates that the receive sts-3c poh processor block is not currently declaring the rdi-p defect condition. 1 ? indicates that the receive sts-3c poh processor block is currently declaring the rdi-p defect condition. note: 1. the user can specify the value for ?rdi-p_thrd? by writing the appropriate data into bits 3 through 0 (rdi-p thrd) within the ?receive sts- 3c path ? sonet receive rdi-p register. 2. the address location of the ?rec eive sts-3c path ? sonet receive rdi-p registers is 0x1193 2 rdi-p unstable defect declared r/o rdi-p (path ? remote defect indicator) unstable defect declared: this read-only bit-field indicates wh ether or not the receive sts-3c poh processor block is currently declaring t he ?rdi-p unstable? defect condition. the receive sts-3c poh processor block will declare a ?rdi-p unstable? defect condition whenever the ?rdi-p unstable counter? reaches the value ?rdi-p thrd?. the ?rdi-p unstable? counter is incremented for each time that the receive sts-3c poh processor block receives an rdi-p value that differs from that of the previous sts-3c frame. the ?rdi-p unstable? counter is cleared to ?0? whenever the same rdi-p value is received in ?rdi- p_thrd? consecutive sts-3c frames. note: receiving a given rdi-p value, in ?rdi-p_thrd? consecutive sts- 3c frames also clears this bit-field to ?0?. 0 ? indicates that the receive sts-3c poh processor block is not currently declaring the ?rdi-p unstable? defect condition. 1 ? indicates that the receive sts-3c poh processor block is currently declaring the ?rdi-p unstable? defect condition. note: 1. the user can specify the value for ?rdi-p_thrd? by writing the appropriate data into bits 3 through 0 (rdi-p thrd) within the ?receive sts- 3c path ? sonet receive rdi-p register. 2. the address location of the rece ive sts-3c path ? sonet receive rdi- p registers is 0x1193 1 lop-p defect declared r/o loss of pointer indicator (lop-p) defect declared: this read-only bit-field indicates wh ether or not the receive sts-3c poh processor block is currently declaring the lop-p (loss of pointer) defect condition. the receive sts-3c poh processor bl ock will declare the lop-p defect condition, if it c annot detect a valid pointer (h1 and h2 bytes, within the toh) within 8 to 10 consecutive sonet fram es. further, the receive sts-3c poh processor block will declare the lop-p defe ct condition, if it detects 8 to 10 consecutive ndf events. the receive sts-3c poh processor block will clear the lop-p defect condition, whenever the receive sts-3c poh processor detects valid pointer bytes (e.g., the h1 and h2 bytes, within the toh) and normal ndf value for three consecutive incoming sts-3c frames. 0 ? indicates that the receive sts-3c poh processor block is not currentl y
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 203 declaring the lop-p defect condition. 1 ? indicates that the receive sts-3c poh processor block is currently declaring the lop-p defect condition. 0 ais-p defect declared r/o path ais (ais-p) defect declared: this read-only bit-field indicates wh ether or not the receive sts-3c poh processor block is currently declaring the ais-p defect condition. the receive sts-3c poh processor block wi ll declare the ais-p defect condition if it detects all of the fo llowing conditions within three consecutive incoming sts-3c frames. a. the h1, h2 and h3 bytes are set to an ?all ones? pattern. b. the entire spe is set to an ?all ones? pattern. the receive sts-3c poh processor block will clear the ais-p defect condition when it detects a valid sts-3c pointer (h1 and h2 bytes) and a ?set? or ?normal? ndf for three consecutive sts-3c frames. 0 ? indicates that the receive sts-3c poh processor block is not currently declaring the ais-p defect condition. 1 ? indicates that the receive sts-3c poh processor block is currently declaring the ais-p defect condition. note: the receive sts-3c poh processor block will not declare the lop-p defect condition if it detects an ?all ones? pa ttern in the h1, h2 and h3 bytes. it will, instead, declare the ais-p defect condition.
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 204 table 123: receive sts-3c path ? sonet receive path interrupt status ? byte 2 (address location= 0x1189) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 unused change in ais-c defect condition interrupt status change in lop-c defect condition interrupt status detection of ais pointer interrupt status detection of pointer change interrupt status poh capture interrupt status change in tim-p defect condition interrupt status change in path trace message unstable defect condition interrupt status r/o rur rur rur rur rur rur rur 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 unused r/o 6 change in ais-c defect condition interrupt status rur change in ais-c (ais concatenation) defect condition interrupt status: this reset-upon-read bit-field permits indicates whether or not the ?change in ais-c defect condition? interrupt has occurred since the last read of this register. if this interrupt is enabled, then an interrupt will be generated in response to either of the following events. a. whenever the receive sts-3c poh processor block declares the ais-c defect c ondition with one of the sts-1 time-slots?; within the incoming sts-3c signal. b. whenever the receive sts-3c poh processor block clears the ais-c defect condition with one of the ?sts-1 time-slots?; within the incoming sts-3c signal. 0 ? indicates that the ?change in ais-c defect condition? interrupt has not occurred since the last read of this register. 1 ? indicates that the ?change in ais-c defect condition? interrupt has occurred since the last read of this register. note: the user can determine the cu rrent state of ais-c by reading out the contents of the ?receive sts-3c path ? ais-c status? register (address locations: 0x11b3). 5 change in lop-c defect condition interrupt status rur change in lop-c (loss of pointer - concatenation) defect condition interrupt status: this reset-upon-read bit-field permits indicates whether or not the ?change in lop-c defect condition? interrupt has occurred since the last read of this register. if this interrupt is enabled, then an interrupt will be generated in response to either of the following events. a. whenever the receive sts-3c poh processor block declares the lop-c defect condition with one of the ?sts-1 time-slots?; within the incoming sts-3c signal. b. whenever the receive sts-3c poh processor block clears the lop-c defect condition with one of the ?sts-1 timeslots?; within the incoming sts-3c signal.
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 205 0 ? indicates that the ?change in lop-c defect condition? interrupt has not occurred since the last read of this register. 1 ? indicates that the ?change in lop-c defect condition? interrupt has occurred since the last read of this register. note: the user can determine the cu rrent state of the lop-c defect by reading out the contents of the ?receive sts-3c path ? lop-c status? register (address locations: 0x11ab). 4 detection of ais pointer interrupt status rur detection of ais pointer interrupt status: this reset-upon-read bit-field indicates whether or not the ?detection of ais pointer? interr upt has occurred since the last read of this register. if this interrupt is enabled, then the receive sts-3c poh processor block will generate this interrupt anytime it detects an ?ais pointer? in the incoming sts-3c data stream. note: an ?ais pointer? is defined as a condition in which both the h1 and h2 bytes (within the toh) are each set to an ?all ones? pattern. 0 ? indicates that the ?detecti on of ais pointer? interrupt has not occurred since the last read of this register. 1 ? indicates that the ?detecti on of ais pointer? interrupt has occurred since the last read of this register. 3 detection of pointer change interrupt status rur detection of pointer change interrupt status: this reset-upon-read bit-field indicates whether or not the ?detection of pointer change? interrupt has occurred since the last read of this register. if this interrupt is enabled, then the receive sts-3c poh processor block will generate an interrupt anytime it accepts a new pointer value (e.g., h1 and h2 bytes, in the toh bytes). 0 ? indicates that the ?detection of pointer change? interrupt has not occurred since the last read of this register. 1 ? indicates that the ?detection of pointer change? interrupt has occurred since the last read of this register. 2 poh capture interrupt status rur path overhead data capture interrupt status: this reset-upon-read bit-field indicates whether or not the ?poh capture? interrupt has occu rred since the last read of this register. if this interrupt is enabled, then the receive sts-3c poh processor block will generate an interrupt once the z5 byte (e.g., the last poh byte) has been loaded into the poh capture buffer. the contents of the poh capture buffer will remain intact for one sonet frame peri od. afterwards, the poh data, for the next spe will be loaded in to the ?poh capture? buffer. 0 ? indicates that the ?poh capture? interrupt has not occurred since the last read of this register. 1 ? indicates that the ?poh capture? interrupt has occurred since the last read of this register. note: the user can obtain the contents of the poh, within the most recently received spe by reading out the contents of address locations ?0xn0d3? through ?0xn0f3?).
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 206 1 change in tim-p defect condition interrupt status rur change in tim-p (trace identification mismatch) defect condition interrupt. this reset-upon-read bit-field indicates whether or not the ?change in tim-p? defect condition interrupt has occurred since the last read of this register. if this interrupt is enabled, then the receive sts-3c poh processor block will generate an inte rrupt in response to either of the following events. ? whenever the receive sts-3c poh processor block declares thetim-p defect condition. ? whenever the receive sts-3c poh processor block clears the tim-p defect condition. 0 ? indicates that the ?change in tim-p defect condition? interrupt has not occurred since the last read of this register. 1 ? indicates that the ?change in tim-p defect condition? interrupt has occurred since the last read of this register. 0 change in path trace message unstable defect condition interrupt status rur change in path trace identification message unstable defect condition? interrupt status: this reset-upon-read bit-field indicates whether or not the ?change in path trace message unstable defect condition? interrupt has occurred since the last read of this register. if this interrupt is enabled, then the receive sts-3c poh processor block will generate this interrupt in response to either of the following events. ? whenever the receive sts-3c poh processor block declare the ?path trace message unst able? defect condition. ? whenever the receive sts-3c poh processor block clears the ?path trace message unst able? defect condition. 0 ? indicates that the ?change in path trace message unstable defect condition? interrupt has not occurred since the last read of this register. 1 ? indicates that the ?change in path trace message unstable defect condition? interrupt has occurred since the last read of this register.
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 207 table 124: receive sts-3c path ? sonet receive path interrupt status ? byte 1 (address location= 0x118a) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 new path trace message interrupt status detection of rei-p event interrupt status change in uneq-p defect condition interrupt status change in plm-p defect condition interrupt status new c2 byte interrupt status change in c2 byte unstable defect condition interrupt status change in rdi-p unstable defect condition interrupt status new rdi-p value interrupt status rur rur rur rur rur rur rur rur 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 new path trace message interrupt status rur new path trace message interrupt status: this reset-upon-read bit-field indicates whether or not the ?new path trace message? interrupt has occurred si nce the last read of this register. if this interrupt is enabled, then the receive sts-3c poh processor block will generate an interrupt anytime it has accepted (or validated) and new path trace message. 0 ? indicates that the ?new path trace message? interrupt has not occurred since the last read of this register. 1 ? indicates that the ?new path trace message? interrupt has occurred since the last read of this register. 6 detection of rei-p event interrupt status rur detection of rei-p event interrupt status: this reset-upon-read bit-field indicates whether or not the ?detection of rei-p event? interrupt has occurred si nce the last read of this register. if this interrupt is enabled, then the receive sts-3c poh processor block will generate an interrupt anytime it detects an rei-p event within the incoming sts-3c data-stream. 0 ? indicates that the ?detection of rei-p event? interrupt has not occurred since the last read of this register. 1 ? indicates that the ?detection of rei-p event? interrupt has occurred since the last read of this register. 5 change in uneq- p defecft condition interrupt status rur change in uneq-p (path ? unequipped) defect condition interrupt status: this reset-upon-read bit-field indicates whether or not the ?change in uneq-p defect condition? interrupt has occurred since the last read of this register. if this interrupt is enabled, then the receive sts-3c poh processor block will generate an interrupt in response to either of the following conditions. ? whenever the receive sts-3c poh processor block declares the uneq-p defect condition. ? whenever the receive sts-3c poh processor block clears the uneq- p defect condition. 0 ? indicates that the ?change in uneq-p defecft condition? interrupt has not occurred since the last read of this register. 1 ? indicates that the ?chan g e in uneq-p defect condition? interru p t has
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 208 occurred since the last read of this register. note: 1. the user can determine the current state of the uneq-p defect condition by reading out the state of bit 5 (uneq-p defect declared) within the ?receive sts-3c path ? sonet receive poh status ? byte 0? register. 2. the address location of the receive sts-3c path ? sonet receive poh status ? byte 0? registers is 0x1187 4 change in plm-p defect condition interrupt status rur change in plm-p (path ? payload mismatch) defect condition interrupt status: this reset-upon-read bit indicates whether or not the ?change in plm- p defect condition? interrupt has occurred since the last read of this register. if this interrupt is enabled, then the receive sts-3c poh processor block will generate an interrupt in response to either of the following conditions. ? when the receive sts-3c poh processor block declares the ?plm-p? defect condition. ? when the receive sts-3c poh processor block clears the ?plm-p? defect condition. 0 ? indicates that the ?change in pl m-p defect condition? interrupt has not occurred since the last read of this register. 1 ? indicates that the ?change in pl m-p defect condition? interrupt has occurred since the last read of this register. 3 new c2 byte interrupt status rur new c2 byte interrupt status: this reset-upon-read bit-field indicates whether or not the ?new c2 byte? interrupt has occurred since the last read of this register. if this interrupt is enabled, then the receive sts-3c poh processor block will generate an interrupt anytime it has accepted a new c2 byte. 0 ? indicates that the ?new c2 byte? interrupt has not occurred since the last read of this register. 1 ? indicates that the ?new c2 byte? interrupt has occurred since the last read of this register. 2 change in c2 byte unstable defect condition interrupt status rur change in c2 byte unstable defect condition interrupt status: this reset-upon-read bit-field indicates whether or not the ?change in c2 byte unstable defect condition? interrupt has occurred since the last read of this register. if this interrupt is enabled, then the receive sts-3c poh processor block will generate an interrupt in response to either of the following events. ? when the receive sts-3c poh processor block declares the ?c2 byte unstable? defect condition. ? when the receive sts-3c poh processor block clears the ?c2 byte unstable? defect condition. 0 ? indicates that the ?change in c2 byte unstable defect condition? interrupt has not occurred since the last read of this register. 1 ? indicates that the ?change in c2 byte unstable defect condition? interrupt has occurred since the last read of this register. note: 1. the user can determine the current state of ?c2 byte unstable defect condition? b y readin g out the state of bit 6 ( c2 b y te unstable defect
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 209 declared) within the ?receive sts-3c path ? sonet receive poh status ? byte 0? register. 2. the address location of the receive sts-3c path ? sonet receive poh status ? byte 0? register is 0x1187 1 change in rdi-p unstable defect condition interrupt status rur change in rdi-p unstable defect condition interrupt status: this reset-upon-read bit-field indicates whether or not the ?change in rdi-p unstable condition? interrupt has occurred since the last read of this register. if this interrupt is enabled, then the receive sts-3c poh processor block will generate an interrupt in response to either of the following conditions. ? when the receive sts-3c poh processor block declares an ?rdi-p unstable? defect condition. ? when the receive sts-3c poh processor block clears the ?rdi-p unstable? defect condition. 0 ? indicates that the ?change in rdi-p unstable defect condition? interrupt has not occurred since the last read of this register. 1 ? indicates that the ?change in rdi-p unstable defect condition? interrupt has occurred since the last read of this register. note: 1. the user can determine the curr ent state of ?rdi-p unstable defectg condition? by reading out the stat e of bit 2 (rdi-p unstable defect declared) within the ?receive sts-3c path ? sonet receive poh status ? byte 0? register. 2. the address location of the receive sts-3c path ? sonet receive poh status ? byte 0? register is 0x1187 0 new rdi-p value interrupt status rur new rdi-p value interrupt status: this reset-upon-read bit-field indica tes whether or not the ?new rdi-p value? interrupt has occurred since the last read of this register. if this interrupt is enabled, then the receive sts-3c poh processor block will generate this interrupt anytime it receives and ?validates? a new rdi-p value. 0 ? indicates that the ?new rdi-p value? interrupt has not occurred since the last read of this register. 1 ? indicates that the ?new rdi-p va lue? interrupt has occurred since the last read of this register. note: 1. the user can obtain the ?new rdi-p value? by reading out the contents of the ?rdi-p accept[2:0]? bit-fields. these bit-fields are located in bits 6 through 4, within the ?receive sts-3c path ? sonet receive rdi-p register?. 2. the address location of the receive sts-3c path ? sonet receive poh status ? byte 0? register is 0x1193
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 210 table 125: receive sts-3c path ? sonet receive path interrupt status ? byte 0 (address location= 0x118b) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 detection of b3 byte error interrupt status detection of new pointer interrupt status detection of unknown pointer interrupt status detection of pointer decrement interrupt status detection of pointer increment interrupt status detection of ndf pointer interrupt status change of lop-p defect condition interrupt status change of ais-p defect condition interrupt status rur rur rur rur rur rur rur rur 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 detection of b3 byte error interrupt status rur detection of b3 byte error interrupt status: this reset-upon-read bit-field indicates whether or not the ?detection of b3 byte error? interrupt has occurred since the last read of this register. if this interrupt is enabled, then the receive sts-3c poh processor block will generate an interrupt anytime it detects a b3 byte error in the incoming sts-3c data stream. 0 ? indicates that the ?detection of b3 byte error? interrupt has not occurred since the last read of this interrupt. 1 ? indicates that the ?detection of b3 byte error? interrupt has occurred since the last read of this interrupt. 6 detection of new pointer interrupt status rur detection of new pointer interrupt status: this reset-upon-read indicates whether the ?detection of new pointer? interrupt has occurred since the last read of this register. if the user enables this interrupt, then the receive sts-3c poh processor block will generate an interrupt anytime it detects a new pointer value in the incoming sts-3c frame. note: pointer adjustments with ndf will not generate this interrupt. 0 ? indicates that the ?detection of new pointer? interrupt has not occurred since the last read of this register. 1 ? indicates that the ?detection of new pointer? interrupt has occurred since the last read of this register. 5 detection of unknown pointer interrupt status rur detection of unknown pointer interrupt status: this reset-upon-read bit-field indicates whether or not the ?detection of unknown pointer? interrupt has occu rred since the last read of this register. if the user enables this interrupt, then the receive sts-3c poh processor block will generate an interrupt anytime that it detects a ?pointer? that does not fit into any of the following categories. ? an increment pointer ? a decrement pointer ? an ndf pointer ? an ais (e.g., all ones) pointer ? new pointer 0 ? indicates that the ?detection of unknown pointer? interru p t has not
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 211 occurred since the last read of this register. 1 ? indicates that the ?detection of unknown pointer? interrupt has occurred since the last read of this register. 4 detection of pointer decrement interrupt status rur detection of pointer decrement interrupt status: this reset-upon-read bit-field indicates whether or not the ?detection of pointer decrement? interrupt has o ccurred since the last read of this register. if this interrupt is enabled, then the receive sts-3c poh processor block will generate an interrupt anytime it detects a ?pointer decrement? event. 0 ? indicates that the ?detection of pointer decrement? interrupt has not occurred since the last read of this register. 1 ? indicates that the ?detection of pointer decrement? interrupt has occurred since the last read of this register. 3 detection of pointer increment interrupt status rur detection of pointer increment interrupt status: this reset-upon-read bit-field indicates whether or not the ?detection of pointer increment? interrupt has occurred since the last read of this register. if this interrupt is enabled, then the receive sts-3c poh processor block will generate an interrupt anytime it detects a ?pointer increment? event. 0 ? indicates that the ?detection of pointer increment? interrupt has not occurred since the last read of this register. 1 ? indicates that the ?detection of pointer increment? interrupt has occurred since the last read of this register. 2 detection of ndf pointer interrupt status rur detection of ndf pointer interrupt status: this reset-upon-read bit-field indicates whether or not the ?detection of ndf pointer? interrupt has occurred since the last read of this register. if the user enables this interrupt, then the receive sts-3c poh processor block will generate an interrupt anytime it detects an ndf pointer event. 0 ? indicates that the ?detection of ndf pointer? interrupt has not occurred since the last read of this register. 1 ? indicates that the ?detection of ndf pointer? interrupt has occurred since the last read of this register. 1 change of lop- p defect condition interrupt status rur change of lop-p defect condition interrupt status: this reset-upon-read bit-field indicates whether or not the ?change in lop-p defect condition? interrupt has occurred since the last read of this register. if the user enables this interrupt, then the receive sts-3c poh processor block will generate an interrupt in response to either of the following events. a. whenever the receive sts-3c poh processor block declares the ?lop-p? defect condition. b. whenever the receive ?sts-3c poh processor? block clears the lop-p defect condition. 0 ? indicates that the ?change in lop-p defect condition? interrupt has not occurred since the last read of this register. 1 ? indicates that the ?change in lop-p defect condition? interrupt has occurred since the last read of this register.
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 212 note: 1. the user can determine if the receive sts-3c poh processor block is currently declaring the lop-p defect cond ition by reading out the state of bit 1 (lop-p defect declared) within the ?receive sts-3c path ? sonet receive poh status ? byte 0? register. 2. the address location of the ?rec eive sts-3c path ? sonet receive poh status ? byte 0? register is 0x1187 0 change of ais- p defect condition interrupt status rur change of ais-p defect condition interrupt status: this reset-upon-read bit-field indicates whether or not the ?change of ais-p defect condition? interrupt has occurred since the last read of this register. if this interrupt is enabled, then the receive sts-3c poh processor block will generate an interrupt in response to either of the following events. ? whenever the receive sts-3c poh processor block declares the ais- p defect condition. ? whenever the receive sts-3c poh processor block clears the ais-p defect condition. 0 ? indicates that the ?change of ai s-p defect condition? interrupt has not occurred since the last read of this register. 1 ? indicates that the ?change of ai s-p defect condition? interrupt has occurred since the last read of this register. note: 1. the user can determine if the receive sts-3c poh processor block is currently declaring the ais-p defect c ondition by reading out the state of bit 0 (ais-p defect declared) within the ?receive sts-3c path ? sonet receive poh status ? byte 0? register. 2. the address location of the receive sts-3c path ? sonet receive poh status ? byte 0? registers is 0x1187
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 213 table 126: receive sts-3c path ? sonet receive path interrupt enable ? byte 2 (address location= 0x118d) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 new k3 byte interrupt enable change in ais-c defect condition interrupt enable change in lop-c defect condition interrupt enable detection of ais pointer interrupt enable detection of pointer change interrupt enable poh capture interrupt enable change in tim-p defect condition interrupt enable change in path trace message unstable defect condition interrupt enable r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 new k3 byte interrupt enable r/w new k3 byte interrupt enable: this read/write bit-field permits the user to either enable or disable the ?new k3 byte? interrupt. if this interrupt is enabled, then the receive sts-3c poh processor block will generate an interrupt anytime it has accepted (or validated) and new k3 byte. 0 ? disables the ?new k3 byte? interrupt. 1 ? enables the ?new k3 byte? interrupt. 6 change in ais-c defect condition interrupt enable r/w change in ais-c (ais concatenation) defect condition interrupt enable: this read/write bit-field permits the user to either enable or disable the ?change in ais-c defect condition? interrupt. if this interrupt is enabled, then an interrupt will generated in response to either of the following events. a. whenever the receive sts-3c poh processor block declares the ais-c defect condition within one of the sts-1 time-slots; within the incoming sts-3c signal. b. whenever the receive sts-3c poh processor block clears the ais-c defect condition with one of the sts-1 time-slots; within the incoming sts-3c signal. 0 ? disables the ?change in ais-c defect condition? interrupt. 1 ? enables the ?change in ais-c defect condition? interrupt note: this bit-field is only valid if the XRT94L33 is receiving an sts-3c signal. this bit-field is only valid for the following address locations: ?0x118d? (for sts-3c ) 5 change in lop-c condition interrupt enable r/w change in lop-c (loss of pointer - concatenation) condition interrupt enable: this read/write bit-field permits the user to either enable or disable the ?change in lop-c defect condition? interrupt. if this interrupt is enabled, then an interrupt will generated in response to either of the following events.
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 214 a. whenever the receive sts-3c poh processor block declares the lop-c defect condit ion with one of the sts-1 timeslots; within the incoming sts-3c signal. b. whenever the receive sts-3c poh processor block clears the lop-c defect condition with one of the sts-1 timeslots; within the incoming sts-3c signal. 0 ? disables the ?change in lop-c defect condition? interrupt. 1 ? enables the ?change in lop-c defect condition? interrupt note: this bit-field is only valid if the XRT94L33 is receiving an sts-3c signal. this bit-field is only valid for the following address locations: ?0x118d? (for sts-3c) 4 detection of ais pointer interrupt enable r/w detection of ais pointer interrupt enable: this read/write bit-field permits the user to either enable or disable the ?detection of ais pointer? interrupt. if the user enables this interrupt, then the receive sts-3c poh processor block will generate an interrupt anytime it detects an ?ais pointer?, in the incoming sts-3c data stream. note: an ?ais pointer? is defined as a condition in which both the h1 and h2 bytes (within the toh) are each set to an ?all ones? pattern. 0 ? disables the ?detection of ais pointer? interrupt. 1 ? enables the ?detection of ais pointer? interrupt. 3 detection of pointer change interrupt enable r/w detection of pointer change interrupt enable: this read/write bit-field permits the user to either enable or disable the ?detection of pointer change? interrupt. if this interrupt is enabled, then the receive sts-3c poh processor block will generate an interrupt anytime it has accepted a new pointer value. 0 ? disables the ?detection of pointer chan ge? interrupt. 1 ? enables the ?detection of pointer change? interrupt. 2 poh capture interrupt enable r/w path overhead data capture interrupt enable: this read/write bit-field permits the user to either enable or disable the ?poh capture? interrupt. if this interrupt is enabled, then the receive sts-3c poh processor block will generate an interrupt once the z5 byte (e.g., the last poh byte) has been loaded into the poh capture buffer. the contents of the poh capture buffer will remain intact for one sonet frame period. afterwards, the poh data for the next spe will be loaded into the ?poh capture? buffer. 0 ? disables the ?poh capture? interrupt 1 ? enables the ?poh capture? interrupt. 1 change in tim-p defect condition interrupt enable r/w change in tim-p (trace identification mismatch) defect condition interrupt: this read/write bit-field permits the user to either enable or disable the ?change in tim-p condition? interrupt. if this interru p t is enabled, then the receive sts-3c poh processor
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 215 block will generate an interrupt in response to either of the following events. ? whenever the receive sts-3c poh processor block declares the tim-p defect condition. ? whenever the receive sts-3c poh processor block clears the tim-p defect condition. 0 ? disables the ?change in tim-p condition? interrupt. 1 ? enables the ?change in tim-p condition? interrupt. 0 change in path trace message unstable defect condition interrupt enable r/w change in ?path trace message unstable defect condition? interrupt status: this read/write bit-field permits the user to either enable or disable the ?change in path trace message unstable defect condition? interrupt. if this interrupt is enabled, then the receive sts-3c poh processor block will generate an interrupt in response to either of the following events. ? whenever the receive sts-3c poh processor block declares the ?path trace message unst able? defect condition. ? whenever the receive sts-3c poh processor block clears the ?path trace message unst able? defect condition. 0 ? disables the ?change in path trace message unstable defect condition? interrupt. 1 ? enables the ?change in path trace message unstable defect condition? interrupt.
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 216 table 127: receive sts-3c path ? sonet receive path interrupt enable ? byte 1 (address location= 0x118e) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 new path trace message interrupt enable detection of rei-p event interrupt enable change in uneq-p defect condition interrupt enable change in plm-p defect condition interrupt enable new c2 byte interrupt enable change in c2 byte unstable defect condition interrupt enable change in rdi-p unstable defect condition interrupt enable new rdi-p value interrupt enable r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 new path trace message interrupt enable r/w new path trace message interrupt enable: this read/write bit-field permits the user to either enable or disable the ?new path trace message? interrupt. if this interrupt is enabled, then the receive sts-3c poh processor block will generate an interrupt anytime it has accepted (or validated) and new path trace message. 0 ? disables the ?new path trace message? interrupt. 1 ? enables the ?new path trace message? interrupt. 6 detection of rei-p event interrupt enable r/w detection of rei-p event interrupt enable: this read/write bit-field permits the user to either enable or disable the ?detection of rei-p event? interrupt. if this interrupt is enabled, then he receive sts-3c poh processor block will generate an interrupt anytime it detects an rei-p event within the coming sts-3c data-stream. 0 ? disables the ?detection of rei-p event? interrupt. 1 ? enables the ?detection of rei-p event? interrupt. 5 change in uneq-p defect condition interrupt enable r/w change in uneq-p (path ? unequipped) defect condition interrupt enable: this read/write bit-field permits the user to either enable or disable the ?change in uneq-p defect condition? interrupt. if this interrupt is enabled, then the receive sts-3c poh processor block will generate an interrupt in response to either of the following conditions. ? whenever the receive sts-3c poh processor block declares the uneq-p defect condition. ? whenever the receive sts-3c poh processor block clears the uneq- p defect condition. 0 ? disables the ?change in uneq-p defect condition? interrupt. 1 ? enables the ?change in uneq-p defect condition? interrupt. 4 change in plm- p defect condition interrupt enable r/w change in plm-p (path ? payload label mismatch) defect condition interrupt enable: this read/write bit permits the user to either enable or disable the ?change in plm-p defect condition? interrupt. if this interru p t is enabled, then the receive sts-3c poh processor block
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 217 will generate an interrupt in response to either of the following conditions. ? whenever the receive sts-3c poh processor block declares the ?plm-p? defect condition. ? whenever the receive sts-3c poh processor block clears the ?plm- p? defect condition. 0 ? disables the ?change in plm-p defect condition? interrupt. 1 ? enables the ?change in plm-p defect condition? interrupt. 3 new c2 byte interrupt enable r/w new c2 byte interrupt enable: this read/write bit-field permits the user to either enable or disable the ?new c2 byte? interrupt. if this interrupt is enabled, then the receive sts-3c poh processor block will generate an interrupt anytime it has accepted a new c2 byte. 0 ? disables the ?new c2 byte? interrupt. 1 ? enables the ?new c2 byte? interrupt. note: 1. the user can obtain the value of this ?new c2? byte by reading the contents of the ?receive sts-3c pa th ? received path label value? register. 2. the address location of the re ceive sts-3c path ? received path label value? register is 0x1196 2 change in c2 byte unstable defect condition interrupt enable r/w change in c2 byte unstable defect condition interrupt enable: this read/write bit-field permits the user to either enable or disable the ?change in c2 byte unstable defect condition? interrupt. if this interrupt is enabled, then the receive sts-3c poh processor block will generate an interrupt in response to either of the following events. ? whenever the receive sts-3c poh processor block declares the ?c2 byte unstable? defect condition. ? whenever the receive sts-3c poh processor block clears the ?c2 byte unstable? defect condition. 0 ? disables the ?change in c2 byte unstable condition? interrupt. 1 ? enables the ?change in c2 byte unstable condition? interrupt. 1 change in rdi- p unstable defect condition interrupt enable r/w change in rdi-p unstable defect condition interrupt enable: this read/write bit-field permits the user to either enable or disable the ?change in rdi-p unstable defect condition? interrupt. if this interrupt is enabled, then the receive sts-3c poh processor block will generate an interrupt in response to either of the following conditions. ? whenever the receive sts-3c poh processor block declares an ?rdi- p unstable defect? condition. ? whenever the receive sts-3c poh processor block clears the ?rdi-p unstable defect? condition. 0 ? disables the ?change in rdi-p unstable defect condition? interrupt. 1 ? enables the ?change in rdi-p unstable defect condition? interrupt. 0 new rdi-p value interrupt enable r/w new rdi-p value interrupt enable : this read/write bit-field permits the user to either enable or disable the ?new rdi-p value? interrupt. if this interru p t is enabled, then the receive sts-3c poh processor block
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 218 will generate this interrupt anytime it receives and ?validates? a new rdi-p value. 0 ? disables the ?new rdi-p value? interrupt. 1 ? enable the ?new rdi-p value? interrupt.
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 219 table 128: receive sts-3c path ? sonet receive path interrupt enable ? byte 0 (address location= 0x118f) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 detection of b3 byte error interrupt enable detection of new pointer interrupt enable detection of unknown pointer interrupt enable detection of pointer decrement interrupt enable detection of pointer increment interrupt enable detection of ndf pointer interrupt enable change of lop-p defect condition interrupt enable change of ais-p defect condition interrupt enable r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 detection of b3 byte error interrupt enable r/w detection of b3 byte error interrupt enable: this read/write bit-field permits the user to either enable or disable the ?detection of b3 byte error? interrupt. if the user enables this interrupt, then the receive sts-3c po h processor block will generate an interrupt anytime it detects a b3-byt e error in the incoming sts-3c data- stream. 0 ? disables the ?detection of b3 byte e rror? interrupt. 1 ? enables the ?detection of b3 byte error? interrupt. 6 detection of new pointer interrupt enable r/w detection of new pointer interrupt enable: this read/write bit-field permits the user to either enable or disable the ?detection of new pointer? interrupt. if the user enables this interrupt, then the receive sts-3c poh processor block will generate an interrupt anytime it detects a new pointer va lue in the incoming sts-3c frame. note: pointer adjustments with ndf will not generate this interrupt. 0 ? disables the ?detection of new pointer? interrupt. 1 ? enables the ?detection of new pointer? interrupt. 5 detection of unknown pointer interrupt enable r/w detection of unknown pointer interrupt enable: this read/write bit-field permits the user to either enable or disable the ?detection of unknown pointer? interrupt. if the user enables this interrupt, then the receive sts-3c po h processor block will generate an interrupt anytime it detec ts a ?pointer adjustment? that does not fit into any of the following categories. ? an increment pointer. ? a decrement pointer ? an ndf pointer ? ais pointer ? new pointer. 0 ? disables the ?detection of unknown pointer? interrupt. 1 ? enables the ?detection of unknown pointer? interrupt. 4 detection of pointer decrement interrupt enable r/w detection of pointer decrement interrupt enable: this read/write bit-field permits the user to enable or disable the ?detection of pointer decrement? in terrupt. if the user enables this interru p t, then the receive sts-3c poh processor block will g enerate an
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 220 interrupt anytime it detects a ?pointer-decrement? event. 0 ? disables the ?detection of pointer decrement? interrupt. 1 ? enables the ?detection of pointer decrement? interrupt. 3 detection of pointer increment interrupt enable r/w detection of pointer increment interrupt enable: this read/write bit-field permits the user to either enable or disable the ?detection of pointer increment? interrupt. if the user enables this interrupt, then the receive sts-3c po h processor block will generate an interrupt anytime it detects a ?pointer increment? event. 0 ? disables the ?detection of pointer increment? interrupt. 1 ? enables the ?detection of pointer increment? interrupt. 2 detection of ndf pointer interrupt enable r/w detection of ndf pointer interrupt enable: this read/write bit-field permits the user to either enable or disable the ?detection of ndf pointer? interrup t. if the user enables this interrupt, then the receive sts-3c poh processor block will generate an interrupt anytime it detects an ndf pointer event. 0 ? disables the ?detection of ndf pointer? interrupt. 1 ? enables the ?detection of ndf pointer? interrupt. 1 change of lop- p defect condition interrupt enable r/w change of lop-p defect condition interrupt enable: this read/write bit-field permits the user to either enable or disable the ?change in lop (loss of pointer)? defect condition interrupt. if the user enables this interrupt, then the receive sts-3c poh processor will generate an interrupt in response to either of the following events. a. whenever the receive sts-3c poh processor block declares the lop-p defect condition. b. whenever the receive sts-3c poh processor block clears the lop-p defect condition. 0 ? disable the ?change of lop-p defect condition? interrupt. 1 ? enables the ?change of lop-p defect condition? interrupt. note: 1. the user can determine if the receive sts-3c poh processor block is currently declaring the lop-p defect condition by reading out the contents of bit 1 (lop-p defect declared) within the ?receive sts-3c path ? sonet receive poh status ? byte 0?. 2. the address location of the receive sts-3c path ? sonet receive poh status byte 0? register is 0x1187 0 change of ais-p defect condition interrupt enable r/w change of ais-p defect condition interrupt enable: this read/write bit-field permits the user to either enable or disable the ?change of ais-p (path ais) defect condition? interrupt. if the user enables this interrupt, then the receive sts-3c poh processor block will generate an interrupt in response to either of the following events. a. whenever the receive sts-3c poh processor block declares the ?ais-p? defect condition. b. whenever the receive sts-3c poh processor block clears the ?ais-p? defect condition. 0 ? disables the ?change of ais-p defect condition? interrupt. 1 ? enables the ?change of ais-p defect condition? interrupt. note:
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 221 1. the user can determine if the receive sts-3c poh processor block is currently declaring the ais-p defect cond ition by reading out the contents of bit 0 (ais-p defect declared) within the ?receive sts-3c path ? sonet receive poh status ? byte 0? register. 2. the address location of the re ceive sts-3c path ? sonet receive poh status ? byte 0? register is 0x1187
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 222 table 129: receive sts-3c path ? sonet receive rdi-p register (address location= 0x1193) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 unused rdi-p_accept[2:0] rdi-p threshold[3:0] r/o r/o r/o r/o r/w r/w r/w r/w 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 unused r/o 6 ? 4 rdi- p_accept[2:0] r/o accepted rdi-p value: these read-only bit-fields contain the value of the most recently ?accepted? rdi-p (e.g., bits 5, 6 and 7 within the g1 byte ) value that has been accepted by the receive sts-3c poh processor block. note: a given rdi-p value will be ?acc epted? by the receive sts-3c poh processor block, if this rdi -p value has been consistently received in ?rdi-p threshold[3:0]? number of sonet frames. 3 ? 0 rdi-p threshold[3:0] r/w rdi-p threshold[3:0]: these read/write bit-fields permit the user to defined the ?rdi-p acceptance threshold? for the rece ive sts-3c poh processor block. the ?rdi-p acceptance threshold? is the number of consecutive sonet frames, in which the receive sts-3c poh processor block must receive a given rdi-p value, before it ?accepts? or ?validates? it. the most recently ?accepted? rdi-p value is written into the ?rdi-p accept[2:0]? bit-fields, within this register.
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 223 table 130: receive sts-3c path ? received path label value (address location= 0x1196) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 received_c2_byte_value[7:0] r/o r/o r/o r/o r/o r/o r/o r/o 1 1 1 1 1 1 1 1 b it n umber n ame t ype d escription 7 ? 0 received c2 byte value[7:0] r/o received ?filtered? c2 byte value: these read-only bit-fields contain the value of the most recently ?accepted? c2 byte, via the receive sts-3c poh processor block. the receive sts-3c poh processor block will ?accept? a c2 byte value (and load it into these bit-fields) if it has received a consistent c2 byte, in five (5) consecutive sonet frames. note: 1. the receive sts-3c poh processor block uses this register, along the ?receive sts-3c path ? expected path label value? register, when declaring or clearing the uneq-p and plm-p defect conditions. 2. the address location of the re ceive sts-3c path ? expected path label value? register is 0x1197 table 131: receive sts-3c path ? expected path label value (address location= 0x1197) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 expected_c2_byte_value[7:0] r/w r/w r/w r/w r/w r/w r/w r/w 1 1 1 1 1 1 1 1 b it n umber n ame t ype d escription 7 ? 0 expected c2 byte value[7:0] r/w expected c2 byte value: these read/write bit-fields permits the user to specify the c2 (path label byte) value, that the receive sts-3c poh processor block should expect when declaring or clearing the uneq-p and plm-p defect conditions. if the contents of the ?receive d c2 byte value[7:0]? (see ?receive sts-3c path ? received path label value? register) matches the contents in these register, then the receive sts- 3c poh will not declare any defect conditions. note: the receive sts-3c poh processor block uses this register, along with the ?receive sts-3c path ? receive path label value? register (address location = 0x1196), when declaring or clearing the uneq-p and plm-p defect conditions.
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 224 table 132: receive sts-3c path ? b3 byte error count register ? byte 3 (address location= 0x1198) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 b3_byte_error_count[31:24] rur rur rur rur rur rur rur rur 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 ? 0 b3_byte_error_count[31:24] rur b3 byte error count ? msb: this reset-upon-read register, along with ?receive sts-3c path ? b3 byte error count register ? bytes 2 through 0; function as a 32 bit counter, which is incremented anytime the receive sts-3c poh processor block detects a b3 byte error. note: 1. if the receive sts-3c poh processor block is configured to count b3 byte errors on a ?per-bit? basis, then it will increment this 32 bit counter by the number of bits, within the b3 byte (of each incoming sts-3c spe) that are in error. 2. if the receive sts-3c poh processor block is configured to count b3 byte errors on a ?per-f rame? basis, then it will increment this 32 bit counter each time that it receives an sts-3c spe that contains an erred b3 byte. table 133: receive sts-3c path ? b3 byte error count register ? byte 2 (address location= 0x1199) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 b3_byte_error_count[23:16] rur rur rur rur rur rur rur rur 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 ? 0 b3_byte_error_count[23:16] rur b3 byte error count (bits 23 through 16): this reset-upon-read register, along with ?receive sts-3c path ? b3 byte error count register ? bytes 3, 1 and 0; function as a 32 bit counter, which is incremented anytime the receive sts-3c poh processor block detects a b3 byte error. note: 1. if the receive sts-3c poh processor block is configured to count b3 byte errors on a ?per-bit? basis, then it will increment this 32 bit counter by the number of bits, within the b3 byte (of each incoming sts-3c spe) that are in error. 2. if the receive sts-3c poh processor block is configured to count b3 byte errors on a ?per-f rame? basis, then it will increment this 32-bit counter each time that it receives an sts-3c spe that contains an erred b3 byte.
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 225 table 134: receive sts-3c path ? b3 byte error count register ? byte 1 (address location= 0x119a) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 b3_byte_error_count[15:8] rur rur rur rur rur rur rur rur 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 ? 0 b3_byte_ error_count[15:8] rur b3 byte error count ? (bits 15 through 8): this reset-upon-read register, along with ?receive sts-3c path ? b3 byte error count register ? bytes 3, 2 and 0; function as a 32 bit counter, which is incremented anytime the receive sts-3c poh processor block detects a b3 byte error. note: 1. if the receive sts-3c poh processor block is configured to count b3 byte errors on a ?per-bit? basis, then it will increment this 32-bit counter by the number of bi ts, within the b3 byte (of each incoming sts-3c spe) that are in error. 2. if the receive sts-3c poh processor block is configured to count b3 byte errors on a ?per-f rame? basis, then it will increment this 32-bit counter each time that it receives an sts-3c spe that contains an erred b3 byte. table 135: receive sts-3c path ? b3 byte error count register ? byte 0 (address location= 0x119b) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 b3_byte_error_count[7:0] rur rur rur rur rur rur rur rur 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 ? 0 b3_byte_error_count[7:0] rur b3 byte error count ? lsb: this reset-upon-read register, along with ?receive sts-3c path ? b3 byte error count register ? bytes 3 through 1; function as a 32 bit counter, which is incremented anytime the receive sts-3c poh processor block detects a b3 byte error. note: 1. if the receive sts-3c poh processor block is configured to count b3 byte errors on a ?per-bit? basis, then it will increment this 32-bit counter by the number of bits, within the b3 byte (or each incoming sts-3c spe) that are in error. 2. if the receive sts-3c poh processor block is configured to count b3 byte errors on a ?per-f rame? basis, then it will increment this 32-bit counter each time that it receives an sts-3c spe that contains an erred b3 byte.
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 226 table 136: receive sts-3c path ? rei-p event count register ? byte 3 (address location= 0x119c) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 rei-p_event_count[31:24] rur rur rur rur rur rur rur rur 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 ? 0 rei-p_event_count[31:24] rur rei-p event count ? msb: this reset-upon-read register, along with ?receive sts-3c path ? rei-p event count register ? bytes 2 through 0; function as a 32 bit counter, which is incremented anytime the receive sts-3c poh processor block detects a path ? remote error indicator event within the in coming sts-3c spe data-stream. note: 1. if the receive sts-3c poh processor block is configured to count rei-p events on a ?per-bit? bas is, then it will increment this 32-bit counter by the nibble-value within the rei-p field of the incoming g1 byte within each incoming sts-3c spe. 2. if the receive sts-3c poh processor block is configured to count rei-p events on a ?per-frame ? basis, then it will increment this 32-bit counter each time that it receives an sts-3c spe that contains a ?non-zero? rei-p value. table 137: receive sts-3c path ? rei-p event e rror count register ? byte 2 (address location= 0x119d) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 rei-p_event_count[23:16] rur rur rur rur rur rur rur rur 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 ? 0 rei-p_event_count[23:16] rur rei-p event count (bits 23 through 16): this reset-upon-read register, along with ?receive sts-3c path ? rei-p event count register ? bytes 3, 1 and 0; function as a 32 bit counter, which is incremented anytime the receive sts- 3c poh processor block detects a path ? remote error indicator event within the incoming sts-3c spe data-stream. note: 1. if the receive sts-3c poh processor block is configured to count rei-p events on a ?per-bit? bas is, then it will increment this 32-bit counter by the nibble-value within the rei-p field of the incoming g1 byte within each incoming sts-3c frame. 2. if the receive sts-3c poh processor block is configured to count rei-p events on a ?per-frame ? basis, then it will increment this 32-bit counter each time that it receives an sts-3c spe that contains a ?non-zero? rei-p value.
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 227 table 138: receive sts-3c path ? rei-p event count register ? byte 1 (address location=0x119e) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 rei-p_event_count[15:8] rur rur rur rur rur rur rur rur 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 ? 0 rei-p_event_count[15:8] rur rei-p event count ? (bits 15 through 8) this reset-upon-read register, along with ?receive sts-3c path ? rei-p event count register ? bytes 3, 2 and 0; function as a 32 bit counter, which is incremented anytime the receive sts- 3c poh processor block detects a path ?remote error indicator event within the incoming sts-3c spe data-stream. note: 1. if the receive sts-3c poh processor block is configured to count rei-p events on a ?per-bit? bas is, then it will increment this 32-bit counter by the nibble-value within the rei-p field of the incoming g1 byte within the incoming sts-3c spe. 2. if the receive sts-3c poh processor block is configured to count rei-p events on a ?per-frame ? basis, then it will increment this 32-bit counter each time that it receives an sts-3c spe that contains a non-zero rei-p value.
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 228 table 139: receive sts-3c path ? rei-p event count register ? byte 0 (address location= 0x119f) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 rei-p_event_count[7:0] rur rur rur rur rur rur rur rur 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 ? 0 rei-p_event_count[7:0] rur rei-p event count ? lsb: this reset-upon-read register, along with ?receive sts-3c path ? rei-p event count register ? bytes 3 through 1; function as a 32 bit counter, which is incremented anytime the receive sts-3c poh processor block detects a path ? remote error indicator event within the in coming sts-3c spe data-stream. note: 1. if the receive sts-3c poh processor block is configured to count rei-p events on a ?per-bit? bas is, then it will increment this 32-bit counter by the nibble-value within the rei-p field of the incoming g1 byte. 2. if the receive sts-3c poh processor block is configured to count rei-p events on a ?per-frame ? basis, then it will increment this 32-bit counter each time that it receives an sts-3c spe that contains a ?non-zero? rei-p value.
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 229 table 140: receive sts-3c path ? receive path trace message buffer control register (address location=0x11a3) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 unused new message ready receive path trace message buffer read select receive path trace message accept threshold path trace message alignment message type receive path trace message length[1:0] r/o r/o r/o r/w r/w r/w r/o r/o 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 ? 5 unused r/o 5 new message ready r/o new message ready: this read/write bit-field indicates whether or not the receive sts-3c poh processor block has (1) accepted a new receive path trace message, and (2) has loaded this new message into the receive path trace message buffer, since the last read of this register. 0 ? indicates that the receive sts- 3c poh processor block has (1) not accepted a new path trace message, nor (2) has the receive sts-3c poh processor block loaded any new messages into the receive path trace message buffer, since the last read of this register. 1 ? indicates that the receive sts-3c poh processor block has (1) accepted a new path trace message, and (2) has loaded this new message into the receive path trace message buffer, sinc e the last read of this register. 4 received path trace message buffer read select r/w receive path trace message buffer read selection: this read/write bit-field permits a user to specify which of the following receive path trace message buffer s egments that the microprocessor will read out, whenever it reads out the contents of the receive path trace message buffer. a. the ?actual? receive path trace message buffer. the ?actual? receive path trace message buffer contains the contents of the most recently received (and accepted) path trace message via the incoming sts-3c data-stream. b. the ?expected? receive path trace message buffer. the ?expected? receive path trace message buffer contains the contents of the path trace message that the user ?expects? to receive. the contents of this par ticular buffer are usually specified by the user. 0 ? executing a read to the receive path trace message buffer, will return contents within the ?actual? receive path trace message? buffer. 1 ? executing a read to the receive path trace message buffer will return contents within the ?expected? re ceive path trace message buffer?. note: in the case of the receive sts-3c poh processor block, the ?receive path trace message buffer? is located at address location = 0x1500 through 0x153f 3 path trace message accept threshold r/w path trace message accept threshold: this read/write bit-field permits a user to select the number of consecutive times that the receive sts-3c poh pr ocessor block must receive a given receive path trace messa g e, before it is acce p ted and loaded into the
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 230 ?actual? receive path trace message buffer, as described below. 0 ? configures the receive sts-3c poh processor block to accept the incoming path trace message after it has received it the third time in succession. 1 ? configures the receive sts-3c poh processor block to accept the incoming path trace message after it has received in the fifth time in succession. 2 path trace message alignment type r/o path trace message alignment type: this read/write bit-field permits a user to specify how the receive sts-3c poh processor block will locate the boundary of the incoming path trace message (within the incoming sts-3c data-stream), as indicated below. 0 ? configures the receive sts-3c po h processor block to expect the path trace message boundary to be denoted by a ?line feed? character. 1 ? configures the receive sts-3c poh processor block to except the path trace message boundary to be denoted by the presence of a ?1? in the msb (most significant bit) of the first byte (within the incoming path trace message). in this case, all of the remaining bytes (within the incoming path trace message) will each have a ?0? within their msbs. 1 ? 0 path trace message length[1:0] r/w path trace message length[1:0]: these read/write bit-fields permit t he user to specify the length of the receive path trace message that the receive sts-3c poh processor block will accept and load into the ?actual? receive path trace message buffer. the relationship between the content of these bit-fields and the corresponding receive path trace message length is presented below. msg length[1:0] resulting path trace message length 00 1 byte 01 16 bytes 10/11 64 bytes
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 231 table 141: receive sts-3c path ? pointer value ? byte 1 (address location= 0x11a6) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 unused current_pointer value msb[9:8] r/o r/o r/o r/o r/o r/o r/o r/o 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 - 2 unused r/o 1 ? 0 current_pointer_value_msb[1:0] r/o current pointer value ? msb: these read-only bit-fields, along with that from the ?receive sts-3c path ? pointer value ? byte 0? register combine to reflect the current value of the pointer that the ?receive sts-3c poh processor? block is using to locate the sts-3c spe within the incoming sts-3c data stream. note: these register bits comprise the two-most significant bits of the pointer value. table 142: receive sts-3c path ? pointer value ? byte 0 (address location=0x11a7) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 current_pointer_value_lsb[7:0] r/o r/o r/o r/o r/o r/o r/o r/o 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 ? 0 current_pointer_value_lsb[7:0] r/o current pointer value ? lsb: these read-only bit-fields, along with that from the ?receive sts-3c path ? pointer value ? byte 1? register combine to reflect the current value of the pointer that the ?receive sts-3c poh processor? block is using to locate the sts-3c spe within the incoming sts-3c data stream. note: these register bits comprise the lower byte value of the pointer value.
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 232 table 143: receive sts-3c path ? lop-c status register (address location=0x11ab) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 unused lop-c defect declared sts- 1 time-slot # 3 lop-c defect declared sts- 1 time-slot # 2 unused r/o r/o r/o r/o r/o r/o r/o r/o 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 - 3 unused r/o 2 lop-c defect declared ? sts-1 time-slot # 3 r/o loss of pointer ? concatenation defect declared ? sts-1 time-slot # 3: this read-only bit-field indicates whether or not the receive sts-3c poh processor block is declaring the lop-c (loss of pointer ? concatenation) defect condition with sts-1 time-slot # 3 (within the incoming sts-3c signal). the receive sts-3c poh processor block will declare the lop- c defect condition, with sts-1 time-s lot # 3; if it does not receive the ?concatenation indicator? value of ?0x93ff? in the h1, h2 bytes (associated with sts-1 time-slot # 3) for 8 consecutive sts-3c frames. 0 ? indicates that the receive sts-3c poh processor block is not currently declaring the lop-c defect condition with sts-1 time-slot # 3 within the incoming sts-3c data-stream. 1 ? indicates that the receive sts-3c poh processor block is currently declaring the lop-c defect condition with sts-1 time- slot # 3 within the incoming sts-3c data-stream. note: this bit-field is only valid if the XRT94L33 is receiving and processing an sts-3c signal. 1 lop-c defect declared ? sts-1 time-slot # 2 r/o loss of pointer ? concatenation defect declared ? sts-1 time-slot # 2: this read-only bit-field indicates whether or not the receive sts-3c poh processor block is declaring the lop-c (loss of pointer ? concatenation) defect condition with sts-1 time-slot # 2 (within the incoming sts-3c signal). the receive sts-3c poh processor block will declare the lop- c defect condition, with sts-1 time-s lot # 2; if it does not receive the ?concatenation indicator? value of ?0x93ff? in the h1, h2 bytes (associated with sts-1 time-slot # 2) for 8 consecutive sts-3c frames. 0 ? indicates that the receive sts-3c poh processor block is not currently declaring the lop-c defect condition with sts-1 time-slot # 2 within the incoming sts-3c data-stream. 1 ? indicates that the receive sts-3c poh processor block is currently declaring the lop-c defect condition with sts-1 time- slot # 2 within the incoming sts-3c data-stream. note: this bit-field is only valid if the XRT94L33 is receiving and processing an sts-3c signal. 0 unused r/o
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 233 table 144: receive sts-3c path ? ais-c status register (address location=0x11b3) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 unused ais-c defect declared sts- 1 time-slot # 3 ais-c defect declared sts- 1 time-slot # 2 unused r/o r/o r/o r/o r/o r/o r/o r/o 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 - 3 unused r/o 2 ais-c defect declared ? sts-1 time-slot # 3 r/o ais ? concatenation defect declared ? sts-1 time-slot # 3: this read-only bit-field indicates whether or not the receive sts-3c poh processor block is declaring the ais-c (ais ? concatenation) defect condition with sts-1 time- slot # 3 (within the incoming sts-3c signal). the receive sts-3c poh processor block will declare the ais- c defect condition, with sts-1 time-s lot # 3; if it receives an ?all ones? string; in the h1, h2 bytes (associated with sts-1 time- slot # 3) for 3 consecutive sts-3c frames. 0 ? indicates that the receive sts-3c poh processor block is not currently declaring the ais- c defect condition with sts-1 time-slot # 3. 1 ? indicates that the receive sts-3c poh processor block is currently declaring the ais-c def ect condition with sts-1 time- slot # 3. note: this bit-field is only valid if the XRT94L33 is receiving and processing an sts-3c signal. 1 ais-c defect declared ? sts-1 time-slot # 2 r/o ais ? concatenation defect declared ? sts-1 time-slot # 2 this read-only bit-field indicates whether or not the receive sts-3c poh processor block is declaring the ais-c (loss of pointer ? concatenation) defect condition with sts-1 time-slot # 2 (within the incoming sts-3c signal). the receive sts-3c poh processor block will declare the ais- c defect condition, with sts-1 time-s lot # 2; if it receives an ?all ones? string in the h1, h2 bytes (associated with sts-1 time- slot # 2) for 3 consecutive sts-3c frames. 0 ? indicates that the receive sts-3c poh processor block is not currently declaring the ais- c defect condition with sts-1 time-slot # 2. 1 ? indicates that the receive sts-3c poh processor block is currently declaring the ais-c def ect condition with sts-1 time- slot # 2. note: this bit-field is only valid if the XRT94L33 is receiving and processing an sts-3c signal. 0 unused r/o
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 234 table 145: receive sts-3c path ? auto ais co ntrol register (address location= 0x11bb) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 unused transmit ais-p (down- stream) upon c2 byte unstable transmit ais-p (down- stream) upon uneq-p transmit ais-p (down- stream) upon plm- p transmit ais-p (down- stream) upon path trace message unstable transmit ais-p (down- stream) upon tim-p transmit ais-p (down- stream) upon lop-p transmit ais-p (down- stream) enable r/o r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 unused r/o 6 transmit ais-p (downstream) upon c2 byte unstable r/w transmit path ais (downstream, towards receive sts-1/stm-0 telecom bus interface # 0) upon declaration of the unstable c2 byte defect condition: this read/write bit-field permits the user to configure the receive sts-3c poh processor block to automatically transmit the path ais (ais-p) indicator via the ?downstr eam? sts-3c traffic (e.g., towards receive sts-1/stm-0 telecom bus interface # 0), anytime (and for the duration that) it declares unstable c2 byte defect condition within the ?incoming? sts-3c data-stream. 0 ? does not configure the receive sts-3c poh processor block to automatically transmit the ais-p indicator (via the ?downstream? traffic) whenever it declares ?uns table c2 byte? de fect condition. 1 ? configures the receive sts-3c poh processor block to automatically transmit the ais-p indicator (via the ?downstream? traffic) whenever (and for the durati on that) it declares the ?unstable c2 byte? defect condition. note: the user must also set bit 0 (transmit ais-p enable) to ?1? to configure the receive sts-3c poh processor block to automatically transmit the ais-p indicator, in response to this defect condition. 5 transmit ais-p (downstream) upon uneq-p r/w transmit path ais (downstream, towards the receive sts- 1/stm-0 telecom bus interface # 0) upon declaration of the uneq-p (path-unequipped) defect condition: this read/write bit-field permits the user to configure the receive sts-3c poh processor block to automatically transmit the path ais (ais-p) indicator via the ?downstr eam? traffic (e.g., towards receive sts-1/stm-0 telecom bus interface # 0), anytime (and for the duration that) it declares t he uneq-p defect condition. 0 ? does not configure the receive sts-3c poh processor block to automatically transmit the ais-p indicator (via the ?downstream? traffic, towards receive sts-1/stm-0 telecom bus interface # 0) whenever it declares the uneq-p defect condition. 1 ? configures the receive sts-3c poh processor block to automatically transmit the ais-p indicator (via the ?downstream? traffic, towards receive sts-1/stm-0 telecom bus interface # 0) whenever (and for the duration that ) it declares the uneq-p defect condition. note: the user must also set bit 0 ( transmit ais - p enable ) to ?1?
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 235 to configure the receive sts-3c poh processor block to automatically transmit the ais-p indicator, in response to this defect condition. 4 transmit ais-p (downstream) upon plm-p r/w transmit path ais (downstream, towards receive sts-1/stm-0 telecom bus interface # 0) upon declaration of the plm-p (path- payload label mismatch) defect condition: this read/write bit-field permits the user to configure the receive sts-3c poh processor block to automatically transmit the path ais (ais-p) indicator via the ?downstr eam? traffic (e.g., towards receive sts-1/stm-0 telecom bus interface # 0), anytime (and for the duration that) it declares the plm-p defect condition. 0 ? does not configure the receive sts-3c poh processor block to automatically transmit the ais-p indicator (via the ?downstream? traffic, towards receive sts-1/stm-0 telecom bus interface # 0) whenever it declares the plm-p defect condition. 1 ? configures the receive sts-3c poh processor block to automatically transmit the ais-p indicator (via the ?downstream? traffic, towards receive sts-1/stm-0 telecom bus interface # 0) whenever (and for the duration t hat) it declares the plm-p defect condition. note: the user must also set bit 0 (transmit ais-p enable) to ?1? to configure the receive sts-3c poh processor block to automatically transmit the ais-p indicator, in response to this defect condition. 3 transmit ais-p (downstream) upon path trace message unstable r/w transmit path ais (downstream, towards receive sts-1/stm-0 telecom bus interface # 0) upon declaration of the path-trace message unstable defect condition: this read/write bit-field permits the user to configure the receive sts-3c poh processor block to automatically transmit the path ais (ais-p) indicator via the ?downstr eam? traffic (e.g., towards receive sts-1/stm-0 telecom bus interface # 0), anytime (and for the duration that) it declares the path trace message unstable defect condition within the ?incom ing? sts-3c data-stream. 0 ? does not configure the receive sts-3c poh processor block to automatically transmit the ais-p indicator (via the ?downstream? traffic, towards receive sts-1/stm-0 telecom bus interface # 0) whenever it declares the ?pat h trace message unstable? defect condition. 1 ? configures the receive sts-3c poh processor block to automatically transmit the ais-p indicator (via the ?downstream? traffic, towards receive sts-1/stm-0 telecom bus interface # 0) whenever (and for the duration t hat) it declares the ?path trace message unstable? defect condition. note: the user must also set bit 0 (transmit ais-p enable) to ?1? to configure the receive sts-3c poh processor block to automatically transmit the ais-p indicator, in response to this defect condition. 2 transmit ais-p (downstream) upon tim-p r/w transmit path ais (downstream towards receive sts-1/stm-0 telecom bus interface # 0) upon detection of the tim-p (path- trace identification m essage mismatch defec t) defect condition: this read/write bit-field permits the user to configure the receive sts-3c poh processor block to automatically transmit a path ais (ais-p) indicator via the ?downstr eam? traffic (e.g., towards receive sts-1/stm-0 telecom bus interface # 0), anytime (and for the duration that ) it declares the tim-p defect condition, within the
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 236 incoming sts-3c data-stream. 0 ? does not configure the receive sts-3c poh processor block to automatically transmit the ais-p indicator (via the ?downstream? traffic towards receive sts-1/st m-0 telecom bus interface # 0) whenever it declares the tim-p defect condition. 1 ? configures the receive sts-3c poh processor block to automatically transmit the ais-p indicator (via the ?downstream? traffic towards receive sts-1/st m-0 telecom bus interface # 0) whenever (and for the duration t hat) it declares the tim-p defect condition, within the incoming sts-3c data-stream. note: the user must also set bit 0 (transmit ais-p enable) to ?1? to configure the receive sts-3c poh processor block to automatically transmit the ais-p indicator, in response to this defect condition. 1 transmit ais-p (downstream) upon lop-p r/w transmit path ais (downstream, towards receive sts-1/stm-0 telecom bus interface # 0) upon detection of loss of pointer (lop-p) defect condition: this read/write bit-field permits the user to configure the receive sts-3c poh processor block to automatically transmit the path ais (ais-p) indicator via the ?downstr eam? traffic (e.g., towards receive sts-3/stm-1 telecom bus interface # 0), anytime (and for the duration that) it declares the lo p-p defect condition within the incoming sts-3c data-stream. 0 ? does not configure the receive sts-3c poh processor block to automatically transmit the ais-p indicator (via the ?downstream? traffic, towards receive sts-1/stm-0 telecom bus interface # 0) whenever it declares the lop-p defect condition. 1 ? configures the receive sts-3c poh processor block to automatically transmit the ais-p indicator (via the ?downstream? traffic, towards receive sts-1/stm-0 telecom bus interface # 0) whenever (and for the duration th at) it declares the lop-p defect condition. note: the user must also set bit 0 (transmit ais-p enable) to ?1? to configure the receive sts-3c poh processor block to automatically transmit the ais-p indicator, in response to this defect condition. 0 transmit ais-p (downstream) enable r/w automatic transmission of ais-p enable: this read/write bit-field serves two purposes. it permits the user to configure the receive sts-3c poh processor block to automatically transmit the path ais (ais-p) indicator, via the down-stream traffic (e.g., toward s receive sts-1/stm-0 telecom bus interface # 0), whenever (and for the duration that) it declares either the uneq-p, plm-p, tim-p, lop-p, or path trace message unstable defect conditions. it also permits the user to configure the receive sts-3c poh processor block to automatically transmit the ais-p indicator via the ?downstream? traffic (e .g., towards receive sts-1/stm-0 telecom bus interface # 0) whenever (and for the duration that) it declares the ais-p defect condition, within the incoming sts-3c data-stream. 0 ? configures the receive sts- 3c poh processor block to not automatically transmit the ais-p indicator (via the ?downstream? traffic) upon detection of any of the ?above-mentioned? defect conditions. 1 ? configures the receive sts-3c poh processor block to automaticall y transmit the ais-p indicator ( via the ?downstream?
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 237 traffic, towards receive sts-1/stm-0 telecom bus interface # 0) whenever (and for the duration that) it declares any of the ?above- mentioned? defect condition. note: the user must also set the corresponding bit-fields (within this register) to ?1? in order to configure the receive sts- 3c poh processor block to au tomatically transmit the ais- p indicator upon detection of a given alarm/defect condition.
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 238 table 146: receive sts-3c path ? serial port control register (address location= 0x11bf) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 unused rxpoh_clock_speed[7:0] r/o r/o r/o r/o r/w r/w r/w r/w 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 - 4 unused r/o 3 - 0 rxpoh_clock_speed[7:0] r/w rxpohclk output clock signal speed: these read/write bit-fields permit the user to specify the frequency of the ?rxpohclk output clock signal. the formula that relates the contents of these register bits to the ?rxpohclk? frequency is presented below. freq = 19.44 /[2 * (rxpoh_clock_speed) note: for sts-3/stm-1 applications, the frequency of the rxpohclk output signal mu st be in the range of 0.304mhz to 9.72mhz
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 239 table 147: receive sts-3c path ? sonet receive auto alarm register ? byte 0 (address location= 0x11c3) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 transmit ais-p (via downstream sts-3c) upon lop-p unused transmit ais-p (via downstream sts-3cs) upon plm-p unused transmit ais-p (via downstream sts-3c) upon uneq-p transmit ais-p (via downstream sts-3c) upon tim-p transmit ais-p (via downstream sts-3c) upon ais-p unused r/w r/o r/w r/o r/w r/w r/w r/w 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 transmit ais-p (via downstream sts-3c) upon lop-p r/w transmit ais-p (via downstream sts-3c) upon lop-p this read/write bit-field permi ts the user to configure the transmit sts-3c poh processor block (within the corresponding channel) to automatically transmit the ais-p (path ais) indicator via the ?downstream? sts-3c signal, anytime the receive sts-3c poh processor block declares the lop-p defect. 0 ? does not configure the corresponding transmit sts-1 poh processor block to automatically transmit the ais- p indicator via the ?downstream? sts-3c signals, anytime the receive sts-3c poh processor block declares the lop-p defect. 1 ? configures the corresponding transmit sts-3c poh processor block to automatically transmit the ais- p indicator via the ?downstream? sts-3c signals, anytime the receive sts-3c poh processor block declares the lop-p defect. 6 unused r/o 5 transmit ais-p (via downstream sts-1s) upon plm-p r/w transmit ais-p (via downstream sts-1s) upon plm-p: this read/write bit-field permi ts the user to configure the transmit sts-1 poh processor block (within the corresponding channel) to automatica lly transmit the ais-p (path ais) indicator via the ?downstream? sts-1 signal, anytime the receive sts- 3c poh processor block declares the plm-p defect. 0 ? does not configure the corresponding transmit sts-1 poh processor block to automatically transmit the ais- p indicator via the ?downstream? sts-1 signals, anytime the receive sts-3c poh processor block declares the plm-p defect. 1 ? configures the corresponding transmit sts-1 poh processor block to automatically transmit the ais- p indicator via the ?downstream? sts-1 signals, anytime the receive sts-3c poh processor block declares the plm-p defect. 4 unused r/o 3 transmit ais-p (via downstream sts-1s) upon uneq-p r/w transmit ais-p (via downstream sts-1s) upon uneq-p: this read/write bit-field permi ts the user to configure the transmit sts-1 poh processor block (within the corresponding channel) to automatica lly transmit the ais-p (path ais) indicator via the ?downstream? sts-1 signal, anytime the receive sts- 3c poh processor block declares the uneq-p defect.
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 240 0 ? does not configure the corresponding transmit sts-1 poh processor block to automatically transmit the ais- p indicator via the ?downstream? sts-1 signals, anytime the receive sts-3c poh processor block declares the uneq-p defect. 1 ? configures the corresponding transmit sts-1 poh processor block to automatically transmit the ais- p indicator via the ?downstream? sts-1 signals, anytime the receive sts-3c poh processor block declares the uneq-p defect. 2 transmit ais-p (via downstream sts-1s) upon tim-p r/w transmit ais-p (via downstream sts-1s) upon tim-p: this read/write bit-field permi ts the user to configure the transmit sts-1 poh processor block (within the corresponding channel) to automatica lly transmit the ais-p (path ais) indicator via the ?downstream? sts-1 signal, anytime the receive sts- 3c poh processor block declares the tim-p defect. 0 ? does not configure the corresponding transmit sts-1 poh processor block to automatically transmit the ais- p indicator via the ?downstream? sts-1 signals, anytime the receive sts-3c poh processor block declares the tim-p defect. 1 ? configures the corresponding transmit sts-1 poh processor block to automatically transmit the ais- p indicator via the ?downstream? sts-1 signals, anytime the receive sts-3c poh processor block declares the tim-p defect. 1 transmit ais-p (via downstream sts-1s) upon ais-p r/w transmit ais-p (via downstream sts-1s) upon ais-p: this read/write bit-field permi ts the user to configure the transmit sts-1 poh processor block (within the corresponding channel) to automatica lly transmit the ais-p (path ais) indicator via the ?downstream? sts-1 signal, anytime the receive sts- 3c poh processor block declares the ais-p defect. 0 ? does not configure the corresponding transmit sts-1 poh processor block to automatically transmit the ais- p indicator via the ?downstream? sts-1 signals, anytime the receive sts-3c poh processor block declares the ais-p defect. 1 ? configures the corresponding transmit sts-1 poh processor block to automatically transmit the ais- p indicator via the ?downstream? sts-1 signal, anytime the receive sts-3c poh processor block declares the ais-p defect. 0 unused r/o
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 241 table 148: receive sts-3c path ? receive j1 byte value capture register (address location= 0x11d3) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 j1_byte_captur ed_value[7:0] r/o r/o r/o r/o r/o r/o r/o r/o 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 ? 0 j1_byte_captured_value[7:0] r/o receive j1 byte captured value[7:0] these read-only bit-fields contain the value of the j1 byte, within the most recently received sts-3c frame. this particular value is stored in this register for one sonet frame period. during the next sonet frame period, this value will be overridden with a new j1 byte value. table 149: receive sts-3c path ? receive b3 byte value capture register (address location= 0x11d7) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 b3_byte_captur ed_value[7:0] r/o r/o r/o r/o r/o r/o r/o r/o 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 ? 0 b3_byte_captured_value[7:0] r/o receive b3 byte captured value[7:0] these read-only bit-fields cont ain the value of the b3 byte, within the most recently received sts-3c frame. this particular value is stored in this register for one sonet frame period. during the next sonet frame period, this value will be overridden with a new b3 byte value.
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 242 table 150: receive sts-3c path ? receive c2 byte value capture register (address location= 0x11db) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 c2_byte_captured_value[7:0] r/o r/o r/o r/o r/o r/o r/o r/o 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 ? 0 c2_byte_captured_value[7:0] r/o received c2 byte captured value[7:0] these read-only bit-fields contain the value of the c2 byte, within the most recently received sts-3c frame. this particular value is stored in this register for one sonet frame period. during the next sonet frame period, this value will be overridden with a new c2 byte value. table 151: receive sts-3c path ? receive g1 byte value capture register (address location= 0x11df) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 g1_byte_captured_value[7:0] r/o r/o r/o r/o r/o r/o r/o r/o 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 ? 0 g1_byte_captured_value[7:0] r/o receive g1 byte captured value[7:0] these read-only bit-fields contain the value of the g1 byte, within the most recently received sts-3c frame. this particular value is stored in this register for one sonet frame period. during the next sonet frame period, this value will be overridden with a new g1 byte value.
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 243 table 152: receive sts-3c path ? receive f2 byte value capture register (address location=0x11e3) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 f2_byte_captured_value[7:0] r/o r/o r/o r/o r/o r/o r/o r/o 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 ? 0 f2_byte_captured_value[7:0] r/o receive f2 byte captured value[7:0] these read-only bit-fields cont ain the value of the f2 byte, within the most recently received sts-3c frame. this particular value is stored in this register for one sonet frame period. during the next sonet frame period, this value will be overridden with a new f2 byte value. table 153: receive sts-3c path ? receive h4 byte value capture register (address location=0x11e7) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 h4_byte_captured_value[7:0] r/o r/o r/o r/o r/o r/o r/o r/o 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 ? 0 h4_byte_captured_value[7:0] r/o receive h4 byte captured value[7:0] these read-only bit-fields contain the value of the h4 byte, within the most recently received sts-3c frame. this particular value is stored in this register for one sonet frame period. during the next sonet frame period, this value will be overridden with a new h4 byte value.
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 244 table 154: receive sts-3c path ? receive z3 byte value capture register (address location=0x11eb) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 z3_byte_captured_value[7:0] r/o r/o r/o r/o r/o r/o r/o r/o 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 ? 0 z3_byte_captured_value[7:0] r/o receive z3 byte captured value[7:0] these read-only bit-fields cont ain the value of the z3 byte, within the most recently received sts-3c frame. this particular value is stored in this register for one sonet frame period. during the next sonet frame period, this value will be overridden with a new z3 byte value. table 155: receive sts-3c path ? receive z4 (k3) byte value capture register (address location= 0x11ef) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 z4(k3)_byte_capt ured_value[7:0] r/o r/o r/o r/o r/o r/o r/o r/o 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 ? 0 z4(k3)_byte_capt ured_value[7:0] r/o receive z4 (k3) byte value captured value[7:0] these read-only bit-fields contain the value of the z4 (k3) byte, within the most recently received sts-3c frame. this particular value is stored in this register for one sonet frame period. during the ne xt sonet frame period, this value will be overridden with a new z4 (k3) byte value.
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 245 table 156: receive sts-3c path ? receive z5 byte value capture register (address location= 0x11f3) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 z5_byte_captured_value[7:0] r/o r/o r/o r/o r/o r/o r/o r/o 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 ? 0 z5_byte_captured_value[7:0] r/o receive z5 byte captured value[7:0] these read-only bit-fields cont ain the value of the z5 byte, within the most recently received sts-3c frame. this particular value is stored in this register for one sonet frame period. during the next sonet frame period, this value will be overridden with a new z5 byte value.
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 246 1.6 redundant receive st s-3 toh processor block the register map for the redundant receive sts-3 toh processor block is presented in the table below. additionally, a detailed description of each of the ?redundant receive sts-3 toh processor? block registers is presented below. in order to provide some orientation for the reader, an illustration of the functional block diagram for the XRT94L33, with the ?redundant receive sts-3 toh processor block ?highlighted? is presented below in figure 3. note: the redundant receive sts-3 toh processor block is only active if the user has configured the XRT94L33 device to suppor t line aps applications. figure 3: illustration of the functi onal block diagram of the XRT94L33 (whenever it has been configured to operate in the 3-channel ds3/sts-1 to sts-3 mapper mode), with the redundant receive sts-3 toh processor block ?high-lighted?. ds3/e3 framer block ds3/e3 framer block rx sts-1 pointer justification block rx sts-1 pointer justification block rx sts-1 poh block rx sts-1 poh block tx sts-1 poh block tx sts-1 poh block tx sts-1 pointer justification block tx sts-1 pointer justification block tx sts-1 toh block tx sts-1 toh block rx sts-1 toh block rx sts-1 toh block ds3/e3 jitter attenuator block ds3/e3 jitter attenuator block ds3/e3 mapper block ds3/e3 mapper block tx sonet poh processor block tx sonet poh processor block tx sts-3 toh processor block tx sts-3 toh processor block sts-3 telecom bus block sts-3 telecom bus block tx/rx line i/f block (primary) tx/rx line i/f block (primary) tx/rx line i/f block (aps) tx/rx line i/f block (aps) clock synthesizer block clock synthesizer block channel 1 to channels 2 ? 3 microprocessor interface microprocessor interface jtag test port jtag test port rx sonet poh processor block rx sonet poh processor block rx sts-3 toh processor block rx sts-3 toh processor block from channels 2 ? 3 rx sts-3 toh processor block (primary) rx sts-3 toh processor block (primary)
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 247 redundant receive sts-3 to h processor block register table 157: redundant receive sts-3 toh processor block control register ? address map a ddress l ocation r egister n ame d efault v alues 0x1600 ? 0x1702 reserved 0x1703 redundant receive sts-3 transport control register ? byte 0 0x00 0x1704 ? 0x1705 reserved 0x00 0x1706 redundant receive sts-3 transport status register ? byte 1 0x00 0x1707 redundant receive sts-3 transport status register ? byte 0 0x02 0x1708 reserved 0x00 0x1709 redundant receive sts-3 transport interrupt status register ? byte 2 0x00 0x170a redundant receive sts-3 transport interrupt status register ? byte 1 0x00 0x170b redundant receive sts-3 transport interrupt status register ? byte 0 0x00 0x170c reserved 0x00 0x170d redundant receive sts-3 transport interrupt enable register ? byte 2 0x00 0x170e redundant receive sts-3 transport interrupt enable register ? byte 1 0x00 0x170f redundant receive sts-3 transport interrupt enable register ? byte 0 0x00 0x1710 redundant receive sts-3 transport b1 error count ? byte 3 0x00 0x1711 redundant receive sts-3 transport b1 error count ? byte 2 0x00 0x1712 redundant receive sts-3 transport b1 error count ? byte 1 0x00 0x1713 redundant receive sts-3 transport b1 error count ? byte 0 0x00 0x1714 redundant receive sts-3 transport b2 error count ? byte 3 0x00 0x1715 redundant receive sts-3 transport b2 error count ? byte 2 0x00 0x1716 redundant receive sts-3 transport b2 error count ? byte 1 0x00 0x1717 redundant receive sts-3 transport b2 error count ? byte 0 0x00
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 248 a ddress l ocation r egister n ame d efault v alues 0x1718 redundant receive sts-3 transport rei-l error count ? byte 3 0x00 0x1719 redundant receive sts-3 transport rei-l error count ? byte 2 0x00 0x171a redundant receive sts-3 transport rei-l error count ? byte 1 0x00 0x171b redundant receive sts-3 transport rei-l error count ? byte 0 0x00 0x171c reserved 0x00 0x171d - 0x171e reserved 0x00 0x171f redundant receive sts-3 transport k1 byte value 0x00 0x1720 ? 0x1722 reserved 0x00 0x1723 redundant receive sts-3 transport k2 byte value 0x00 0x1724 ? 0x1726 reserved 0x00 0x1727 redundant receive sts-3 transport s1 byte value 0x00 0x1728 ? 0x172a reserved 0x00 0x172b redundant receive sts-3 transport ? in-sync threshold value 0x00 0x172c, 0x172d reserved 0x00 0x172e redundant receive sts-3 transport ? los threshold value ? msb 0xff 0x172f redundant receive sts-3 transport ? los threshold value ? lsb 0xff 0x1730 reserved 0x00 0x1731 redundant receive sts-3 transport ? sf set monitor interval ? byte 2 0x00 0x1732 redundant receive sts-3 transport ? sf set monitor interval ? byte 1 0x00 0x1733 redundant receive sts-3 transport ? sf set monitor interval ? byte 0 0x00 0x1734 ? 0x1735 reserved 0x00 0x1736 redundant receive sts-3 transport ? sf set threshold ? byte 1 0x00 0x1737 redundant receive sts-3 transport ? sf set threshold ? byte 0 0x00 0x1738, 0x1739 reserved 0x00 0x173a redundant receive sts-3 transport ? sf clear threshold ? byte 1 0x00
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 249 a ddress l ocation r egister n ame d efault v alues 0x173b redundant receive sts-3 transport ? sf clear threshold ? byte 0 0x00 0x173c reserved 0x00 0x173d redundant receive sts-3 transport ? sd set monitor interval ? byte 2 0x00 0x173e redundant receive sts-3 transport ? sd set monitor interval ? byte 1 0x00 0x173f redundant receive sts-3 transport ? sd set monitor interval ? byte 0 0x00 0x1740, 0x1741 reserved 0x00 0x1742 redundant receive sts-3 transport ? sd set threshold ? byte 1 0x00 0x1743 redundant receive sts-3 transport ? sd set threshold ? byte 0 0x00 0x1744, 0x1745 reserved 0x00 0x1746 redundant receive sts-3 transport ? sd clear threshold ? byte 1 0x00 0x1747 redundant receive sts-3 transport ? sd clear threshold ? byte 0 0x00 0x1748 ? 0x174a reserved 0x00 0x174b redundant receive sts-3 transport ? force sef condition 0x00 0x174c, 0x174e reserved 0x00 0x174f redundant receive sts-3 transport ? receive j0 trace buffer control 0x00 0x1750, 0x1751 reserved 0x00 0x1752 redundant receive sts-3 transport ? sd burst error count tolerance ? byte 1 0x00 0x1753 redundant receive sts-3 transport ? sd burst error count tolerance ? byte 0 0x00 0x1754, 0x1755 reserved 0x00 0x1756 redundant receive sts-3 transport ? sf burst error count tolerance ? byte 1 0x00 0x1757 redundant receive sts-3 transport ? sf burst error count tolerance ? byte 0 0x00 0x1758 reserved 0x00 0x1759 redundant receive sts-3 transport ?receive sd clear monitor interval ? byte 2 0xff 0x175a redundant receive sts-3 transport ? receive sd clear monitor interval ? byte 1 0xff
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 250 a ddress l ocation r egister n ame d efault v alues 0x175b redundant receive sts-3 transport ? receive sd clear monitor interval ? byte 0 0xff 0x175c reserved 0x00 0x175d redundant receive sts-3 transport ? receive sf clear monitor interval ? byte 2 0xff 0x175e redundant receive sts-3 transport ? receive sf clear monitor interval ? byte 1 0xff 0x5f 0x175f redundant receive sts-3 transport ? receive sf clear monitor ? byte 0 0xff 0x60 ? 0x62 0x1760 ? 0x1762 reserved 0x00 0x63 0x1763 redundant receive sts-3 transport ? auto ais control register 0x00 0x64 ? 0x66 0x1764 ? 0x1766 reserved 0x00 0x67 0x1767 redundant receive sts-3 transport ? serial port control register 0x00 0x68 ? 0x6a 0x1768 ? 0x176a reserved 0x00 0x6b 0x176b redundant receive sts-3 transport ? auto ais (in downstream sts-1s) control register 0x000 0x6c ? 0x79 0x176c ? 0x1779 reserved 0x7a 0x117a redundant receive sts-3 transport ? toh capture indirect address 0x00 0x7b 0x117b redundant receive sts-3 transport ? toh capture indirect address 0x00 0x7c 0x117c redundant receive sts-3 transport ? toh capture indirect data 0x00 0x7d 0x117d redundant receive sts-3 transport ? toh capture indirect data 0x00 0x7e 0x117e redundant receive sts-3 transport ? toh capture indirect data 0x00 0x7f 0x117f redundant receive sts-3 transport ? toh capture indirect data 0x00 0x80 ? 0xff 0x1780 ? 0x17ff reserved 0x00
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 251 1.6.1 redundant receive sts-3 toh pr ocessor block regist er description table 158: redundant receive sts-3 transport control register ? byte 0 (address location= 0x1703) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 sts-n oh extract sf detect condition detect enable sd detect condition defect enable descramble disable unused rei-l error type b2 error type b1 error type r/w r/w r/w r/w r/o r/w r/w r/w 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 sts-n oh extract r/w sts-n overhead extract: this read/write bit-field permits t he user to configure the rxtoh output port to output the toh for all lower-tri butary sts-1s within the incoming sts-3 signal. 0 ? disables this feature. in this mode, the rxtoh output port will only output the toh for the first sts-1 within the incoming sts-3 signal. 1 ? enables this feature. 6 sf defect condition detect enable r/w signal failure (sf) defect condition detect enable: this read/write bit-field permits the user to enable or disable sf defect declaration and clearance by the redundant receive sts-3 toh processor block, as described below. 0 ? configures the redundant receive sts-3 toh processor block to not declare nor clear the sf defect condition per the ?user-specified? sf defect declaration and clearance criteria. 1 ? configures the redundant receive sts-3 toh processor block to declare and clear the sf defect conditi on per the ?user-specified? sf defect declaration and clearance? critieria. note: the user must set this bit-field to ?1? in order to permit the redundant receive sts-3 toh processor block to declare and clear the sf defect condition. 5 sd defect condition detect enable r/w signal degrade (sd) defect condition detect enable: this read/write bit-field permits the user to enable or disable sd defect declaration and clearance by the redundant receive sts-3 toh processor block as described below. 0 ? configures the redundant receive sts-3 toh processro block to not declare nor clear the sd defect c ondition per the ?user-specified? sd defect declaration and clearance criteria. 1 ? configures the receive sts-3 toh processor block to declare and clear the sd defect condition per the ?user-specified? sd defect declaration and clearance? criteria. note: the user must set this bit-field to ?1? in order to permit the redundant receive sts-3 toh processro block to declare and clear the sd defect condition, 4 descramble disable r/w de-scramble disable: this read/write bit-field permits the user to either enable or disable de- scrambling by the redundant receive sts-3 toh processor block.
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 252 0 ? de-scrambling is enabled. 1 ? de-scrambling is disabled. 3 unused r/o 2 rei-l error type r/w rei-l (line ? remote erro r indicator) error type: this read/write bit-field permits t he user to specify how the ?redundant receive sts-3 toh processor block will count (or tally) rei-l events, for performance monitoring purposes. the user can configure the redundant receive sts-3 toh processor block to increment rei-l events on either a ?per-bit? or ?per-frame? basis. if the user configures the redundant receive sts-3 toh processor block to increment rei-l events on a ?per- bit? basis, then it will increment t he ?redundant receive sts-3 transport rei-l event count? registers by the contents within the m1 byte of the incoming sts-3 data-stream if the user configures the redundant receive sts-3 toh processor block to increment rei-l events on a ?per-frame? basis, then it will increment the ?redundant receive sts-3 transport rei-l event count? register each time it receives an sts-3 frame, in which the m1 byte is set to a ?non-zero? value. 0 ? configures the redundant receive sts-3 toh processor block to count or tally rei-l events on a per-bit basis. 1 ? configures the redundant receive sts-3 toh processor block to count or tally rei-l events on a per-frame basis. 1 b2 error type r/w b2 error type: this read/write bit-field permits t he user to specify how the ?redundant receive sts-3 toh processor block will count (or tally) b2 byte errors, for performance monitoring purposes. the user can configure the redundant receive sts-3 toh processor block to increment b2 byte errors on either a ?per-bit? or ?per-frame? basis. if the user configures the redundant receive sts-3 toh processor block to increment b2 byte errors on a ?per-bit? basis, then it will increm ent the redundant receive sts-3 transport - b2 byte error count? register by the number of bits (within each of the three b2 byte values) that is in error. if the user configures the redundant receive sts-3 toh processor block to increment b2 byte errors on a ?per-frame? basis, then it will increment the ?redundant receive sts-3 transport ? b2 byte error count? register, each time it receives an sts-3 frame that contains at least one erred b2 byte. 0 ? configures the redundant receive sts-3 toh processor block to count b2 byte errors on a ?per-bit? basis. 1 ? configures the redundant receive sts-3 toh processor block to count b2 byte errors on a ?per-frame? basis. 0 b1 error type r/w b1 error type: this read/write bit-field permits t he user to specify how the ?redundant receive sts-3 toh processor block will count (or tally) b1 byte errors, for performance monitoring purposes. the user can configure the redundant receive sts-3 toh processor block to increment b1 byte errors on either a ?per-bit? or ?per-frame? basis. if the user configures the redundant receive sts-3 toh processor block to increment b1 byte errors on a ?per-bit? basis, then it will incr ement the ?redundant receive sts-3 transport - b1 byte error count? register by the number of bits (within the b1 byte value) that is in error. if the user configures the redundant receive sts-3 toh processor block to increment b1 byte errors on a ?per-frame? basis, then it will increment the ?redundant receive sts-3 trans p ort ? b1 b y te error count? re g ister
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 253 each time it receives an sts-3 frame that contains an erred b1 byte. 0 ? configures the redundant receive sts-3 toh processor block to count b1 byte errors on a ?per-bit? basis. 1 ? configures the redundant receive sts-3 toh processor block to count b2 byte errors on a ?per-frame? basis.
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 254 table 159: redundant receive sts-3 transport status register ? byte 1 (address location= 0x1706) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 unused ais-l defect declared r/o r/o r/o r/o r/o r/o r/o r/o 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 ? 1 unused r/o 0 ais-l defect declared r/o ais-l defect declared: this read-only bit-field indicates wh ether or not the redundant receive sts-3 toh processor block is currently declaring the ais-l (line ais) defect condition within the incoming sts-3 data stream. the redundant receive sts-3 toh processor block wi ll declare the ais-l defect condition within the incoming sts-3 data-stream if bits 6, 7 and 8 (e.g., the least significant bits, within the k2 byte) are set to the value ?[1, 1, 1]? for five consecutive sts-3 frames. 0 ? indicates that the redundant receive sts-3 toh processor block is not currently declaring t he ais-l defect condition. 1 ? indicates that the redundant receive sts-3 toh processor block is currently declaring the ais-l defect condition.
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 255 table 160: redundant receive sts-3 transport status register ? byte 0 (address location= 0x1707) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 rdi-l defect declared s1 byte unstable defect declared k1, k2 byte unstable defect declared sf defect declared sd defect declared lof defect declared sef defect declared los defect declared r/o r/o r/o r/o r/o r/o r/o r/o 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 rdi-l defect declared r/o rdi-l (line remote defect indicator) defect declared: this read-only bit-field indicates whether or not the redundant receive sts- 3 toh processor block is currently declaring the rdi-l defect condition within the incoming sts-3 signal. the redundant receive sts-3 toh processor block will declare the rdi-l defect conditio n whenever it determines that bits 6, 7 and 8 (e.g., the three least significant bits) of the k2 byte contains the ?1, 1, 0? pattern within 5 consecutive incoming sts-3 frames. 0 ? indicates that the redundant receive sts-3 toh processor block is not currently declaring the rdi-l defect condition. 1 ? indicates that the redundant receive sts-3 toh processor block is currently declaring the rdi-l defect condition. 6 s1 byte unstable defect declared r/o s1 byte unstable defect declared: this read-only bit-field indicates whether or not the redundant receive sts- 3 toh processor block is currently de claring the ?s1 byte unstable? defect condition. the redundant receive sts- 3 toh processor block will declare the ?s1 byte unstable? defect condition whenever the ?s1 byte unstable counter? reaches the value 32. the redundant receive sts-3 toh processor block will increment the ?s1 byte unstable counter? each time that it receives an sts-3 frame that contains an s1 byte that diffe rs from the previously received s1 byte. the redundant receive sts-3 toh processor block will clear the contents of the ?s1 byte unstable counter? is cleared to ?0? whenever it receives the same s1 byte for 8 consecutive sts-3 frames. 0 ? indicates that the redundant receive sts-3 toh processor block is not currently declaring the ?s1 byte unstable? defect condition. 1 ? indicates that the redundant receive sts-3 toh processor block is currently declaring the s1 byte unstable? defect condition. 5 k1, k2 byte unstable defect declared r/o k1, k2 byte unstable defect declared: this read-only bit-field indicates whether or not the redundant receive sts- 3 toh processor block is currently declari ng the ?k1, k2 byte unstable? defect condition. the redundant receive sts- 3 toh processor block will declare the ?k1, k2 byte unstable? defect condition w henever it fails to receive the same set of k1, k2 bytes, in 12 consecutive sts-3 frames. the redundant receive sts-3 toh processor block will clear the ?k1, k2 byte unstable? defect condition whenever it receives a given set of k1, k2 byte values within three consecutive sts-3 frames. 0 ? indicates that the redundant receive sts-3 toh processor block is not currently declaring the k1, k2 unstable defect condition. 1 ? indicates that the redundant receive sts-3 toh processor block is currently declaring the k1, k2 unstable defect condition. 4 sf defect declared r/o sf (signal failure) defect declared: this read-only bit-field indicates whether or not the redundant receive sts-
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 256 3 toh processor block is currently declaring the sf defect condition. the redundant receive sts-3 toh processor block will declare the sf defect condition anytime it has det ermined that the number of b2 byte errors (measured over a user-selected period of time) exceeds a certain ?user-specified? b2 byte error? threshold. 0 ? indicates that the redundant receive sts-3 toh processor block is not currently declaring the sf defect condition. this bit is set to ?0? when the number of b2 byte errors (accumulated over a given interval of time) does not exceed t he ?sf defect declaration? threshold. 1 ? indicates that the redundant receive sts-3 toh processor block is currently declaring the sf defect condition. this bit is set to ?1? when the number of b2 byte errors (accumulated over a given interval of time) does exceed the ?sf defect declaration? threshold. 3 sd defect declared r/o sd (signal degrade) defect declared: this read-only bit-field indicates whether or not the redundant receive sts- 3 toh processor block is currently decl aring the sd defect condition. the redundant receive sts-3 toh processor block will declare the sd defect condition anytime it has det ermined that the number of b2 byte errors (measured over a ?user-specified? period of time) exceeds a certain ?user-specified? b2 byte error? threshold. 0 ? indicates that the redundant receive sts-3 toh processor block is not currently declaring the sd defect condition. this bit is set to ?0? when the number of b2 byte errors (accumulated over a given interval of time) does not exceed t he ?sd defect declaration? threshold. 1 ? indicates that the redundant receive sts-3 toh processor block is currently declaring the sd defect condition. this bit is set to ?1? when the number of b2 byte errors (accumulated over a given interval of time) does exceed the ?sd defect declaration? threshold. 2 lof defect declared r/o lof (loss of frame) defect declared: this read-only bit-field indicates whether or not the redundant receive sts- 3 toh processor block is currently decl aring the lof defect condition. the redundant receive sts-3 toh processo r block will declare the lof defect condition, if it has bee n declaring the sef (severely errored frame) defect condition for 3ms (or 24 sonet frame periods). 0 ? indicates that the redundant receive sts-3 toh processor block is not currently declaring the lof defect condition. 1 ? indicates that the redundant receive sts-3 toh processor block is currently declaring the lof defect condition. 1 sef defect declared r/o sef (severely errored frame) defect declared: this read-only bit-field indicates whether or not the redundant receive sts- 3 toh processor block is currently decl aring the sef defect condition. the redundant receive sts-3 toh processor block will declare the sef defect condition, if the ?sef declaration criteria?; per the settings of the frpatout[1:0] bits, within the redundant receive sts-3 transport ? in-sync threshold value register (address location= 0x172b) are met. 0 ? indicates that the redundant receive sts-3 toh processor block is not currently declaring the sef defect condition. 1 ? indicates that the redundant receive sts-3 toh processor block is currently declaring the sef defect condition. 0 los defect declared r/o los (loss of signal) defect declared: this read-only bit-field indicates whether or not the redundant receive sts-
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 257 declared 3 toh processor block is currently declaring the los (loss of signal) defect condition. the redundant receive sts- 3 toh processor block will declare the los defect condition if it detects ?l os_threshold[15:0]? consecutive ?all zero? bytes in the incoming sts-3 data stream. note: the user can set the ?los_threshold[15:0]? value by writing the appropriate data into the ?redundant receive sts-3 transport ? los threshold value? register (address location= 0x172e and 0x172f). 0 ? indicates that the redundant receive sts-3 toh processor block is not currently declaring the los defect condition. 1 ? indicates that the redundant receive sts-3 toh processor block is currently declaring the los defect condition.
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 258 table 161: redundant receive sts-3 transport interrupt status register ? byte 2 (address location= 0x1709) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 unused change of ais-l defect condition interrupt status change of rdi-l defect condition interrupt status r/o r/o r/o r/o r/o r/o rur rur 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 - 2 unused r/o 1 change of ais-l defect condition interrupt status rur change of ais-l (line ais) defect condition interrupt status: this reset-upon-read bit-field indicates whether or not the ?change of ais-l defect condition? interrupt has occurred since the last read of this register. the redundant receive sts-3 toh processor block will generate this interrupt in response to either of the following occurrences. ? whenever the redundant receive sts-3 toh processor block declares the ais-l defect condition. ? whenever the redundant receive sts-3 toh processor block clears the ais-l defect condition. 0 ? indicates that the ?change of ais- l defect condition? interrupt has not occurred since the last read of this register. 1 ? indicates that the ?change of ai s-l defect condition? interrupt has occurred since the last read of this register. note: the user can determine if the redundant receive sts-3 toh processor block is currently decla ring the ais-l defect condition by reading the contents of bit 0 (ais-l defect declared) within the ?redundant receive sts-3 transport status register ? byte 1? (address location= 0x1706). 0 change of rdi-l defect condition interrupt status rur change of rdi-l (line - remote de fect indicator) defect condition interrupt status: this reset-upon-read bit-field indicates whether or not the ?change of rdi-l defect condition? interrupt has occurred since the last read of this register. the redundant receive sts-3 toh processor block will generate this interrupt in response to either of the following occurrences. ? whenever the redundant receive sts-3 toh processor block declares the rdi-l defect condition. ? whenever the redundant receive sts-3 toh processor block clears the rdi-l defect condition 0 ? indicates that the ?ch ange of rdi-l defect cond ition? interrupt has not occurred since the last read of this register. 1 ? indicates that the ?c hange of rdi-l defect condition? interrupt has occurred since the last read of this register. note: the user can determine if the redundant receive sts-3 toh processor block is currently decla ring the rdi-l defect condition by reading out the state of bit 7 ( rdi-l defect declared) within the ?redundant receive sts-3 transport status register ? byte 0? (address location = 0x1707).
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 259 table 162: redundant receive sts-3 transport interrupt status register ? byte 1 (address location = 0x170a) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 new s1 byte interrupt status change in s1 byte unstable defect condition interrupt status unused receive toh cap done interrupt status change in k1, k2 bytes unstable defect condition interrupt status new k1k2 byte value interrupt status rur rur r/o r/o r/o rur rur rur 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 new s1 byte value interrupt status rur new s1 byte value interrupt status: this reset-upon-read bit-field indicates whether or not the ?new s1 byte value? interrupt has occurred since the last read of this register. the redundant receive sts-3 toh processor block will generate the ?new s1 byte value? interrupt anytime it has ?accepted? a new s1 byte, from the incoming sts-3 data-stream. 0 ? indicates that the ?new s1 byte value? interrupt has not occurred since the last read of this register. 1 ? indicates that the ?new s1 byte value? interrupt has occurred since the last read of this register. note: the user can obtain the value for th is most recently accepted value of the s1 byte by reading the ?redundant receive sts-3 transport s1 value? register (address location= 0x1727). 6 change in s1 byte unstable defect condition interrupt status rur change in s1 byte unstable defect condition interrupt status: this reset-upon-read bit-field indicates whether or not the ?change in s1 byte unstable defect condition? interrupt has occurred since the last read of this register. the redundant receive sts-3 toh processor block will generate this interrupt in response to either of the following events. ? whenever the redundant receive sts-3 toh processor block declares the ?s1 byte unstable? defect condition. ? whenever the redundant receive sts-3 toh processor block clears the ?s1 byte unstable? defect condition. 0 ? indicates that the ?change in s1 byte unstable defect condition? interrupt has occurred since the last read of this register. 1 ? indicates that the ?change in s1 byte unstable defect condition? interrupt has not occurred since the last read of this register. note: the user can determine if t he redundant receive sts-3 toh processor block is currently declaring the ?s1 byte unstable? defect condition by reading t he contents of bit 6 (s1 byte unstable defect declared) within the ?redundant receive sts-3 transport status register ? byte 0? (address location = 0x1707). 5 ? 3 r/o 2 receive toh cap done interrupt status rur receive toh capture done ? interrupt status: this reset-upon-read bit-field indicates whether the ?receive toh data capture ? interrupt has occurred since the last read of this register
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 260 capture? interrupt has occurred sinc e the last read of this register. if this interrupt is enabled, then the redundant receive sts-3 toh processor block will generate an interrupt anytime it has captured the last toh byte into the capture buffer. note: once the toh (of a given sts-3 frame) has been captured and loaded into the ?receive toh captur e? buffer, it will remain there for one sonet frame period. 0 ? indicates that the ?receive toh data capture? interrupt has not occurred since the last read of this register. 1 ? indicates that the ?receive toh data capture? interrupt has occurred since the last read of this register. 1 change in k1, k2 byte unstable defect condition interrupt status rur change of k1, k2 byte unstable defect condition interrupt status: this reset-upon-read bit-field indicates whether or not the ?change in k1, k2 byte unstable defect condition? interrupt has occurred since the last read of this register. the redundant receive sts-3 toh processor block will generate this interrupt in response to either of the following events. ? whenever the redundant receive sts-3 toh processor block declares the ?k1, k2 byte unstable defect? condition. ? whenever the redundant receive sts-3 toh processor block clears the ?k1, k2 byte unstable? defect condition. 0 ? indicates that the ?change of k1, k2 byte unstable defect condition? interrupt has not occurred since the last read of this register. 1 ? indicates that the ?change of k1, k2 byte unstable defect condition? interrupt has occurred since the last read of this register. note: the user can determine if t he redundant receive sts-3 toh processor block is currently declaring the ?k1, k2 unstable defect condition? by reading out the c ontents of bit 5 (k1, k2 byte unstable defect declared), within the ?redundant receive sts-3 transport status register ? byte 0? (address location = 0x1707). 0 new k1, k2 byte value interrupt status rur new k1, k2 byte value interrupt status: this reset-upon-read bit-field indicates whether or not the ?new k1, k2 byte value? interrupt has occurred since th e last read of this register. the redundant receive sts-3 toh processor block will generate this interrupt whenever it has ?accepted? a new set of k1, k2 byte values from the incoming sts-3 data-stream. 0 ? indicates that the ?new k1, k2 byte value? interrupt has not occurred since the last read of this register. 1 ? indicates that the ?new k1, k2 byte value? interrupt has occurred since the last read of this register. note: the user can obtain the contents of the new k1 byte by reading out the contents of the ?redundant re ceive sts-3 transport k1 byte value? register (address location= 0x171f). further, the user can also obtain the contents of t he new k2 byte by reading out the contents of the ?redundant rece ive sts-3 transport k2 byte value? register (address location= 0x1723).
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 261 table 163: redundant receive sts-3 transport interrupt status register ? byte 0 (address location= 0x170b) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 change in sf defect condition interrupt status change in sd defect condition interrupt status detection of rei-l event interrupt status detection of b2 byte error interrupt status detection of b1 byte error interrupt status change of lof defect condition interrupt status change of sef defect condition interrupt status change of los defect condition interrupt status rur rur rur rur rur rur rur rur 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 change in sf defect condition interrupt status rur change of signal failure (sf) defect condition interrupt status: this reset-upon-read bit-field indicates whether or not the ?change of sf defect condition interrupt? has occurred since the last read of this register. the redundant receive sts-3 toh processor block will generate this interrupt in response to either of the following events. ? whenever the redundant receive sts-3 toh processor block declares the sf defect condition. ? whenever the redundant receive sts-3 toh processor block clears the sf defect condition. 0 ? indicates that the ?change of sf defect condition interrupt? has not occurred since the last read of this register. 1 ? indicates that the ?change of sf defect condition interrupt? has occurred since the last read of this register. note: the user can determine if the redundant receive sts-3 toh processor block is currently declaring the ?sf? defect condition by reading out the state of bit 4 (sf defect declar ed) within the ?redundant receive sts-3 transpor t status register ? byte 0 (address location= 0x1707). 6 change of sd defect condition interrupt status rur change of signal degrade (sd) defect condition interrupt status: this reset-upon-read bit-field indicates whether or not the ?change of sd defect condition interrupt? has occurred since the last read of this register. the redundant receive sts-3 toh processor block will generate this interrupt in response to either of the following events. ? whenever the redundant receive sts-3 toh processor block declares the sd defect condition. ? whenever the redundant receive sts-3 toh processor block clears the sd defect condition. 0 ? indicates that the ?change of sd defect condition interrupt? has not occurred since the last read of this register. 1 ? indicates that the ?change of sd defect condition interrupt? has occurred since the last read of this register. note: the user can determine the w hether or not the redundant receive sts-3 toh processor block is currently declaring the sd defect condition by reading out the state of bit 3 (sd defect declared) within the ?redundant receive sts-3 transport status register ? byte 0 (address location= 0x1707). 5 detection of rei- rur detection of rei-l (line ? remote error indicator) event interrupt
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 262 l event interrupt status status: this reset-upon-read bit-field indicates whether or not the ?declaration of rei-l event? interrupt has occurred since the last read of this register. the redundant receive sts-3 toh processor block will generate this interrupt anytime it detects an rei-l event within the incoming sts-3 data- stream. 0 - indicates that the ?detection of rei-l event? interrupt has not occurred since the last read of this register. 1 ? indicates that the ?detection of rei-l event? interrupt has occurred since the last read of this register. 4 detection of b2 byte error interrupt status rur detection of b2 byte error interrupt status: this reset-upon-read bit-field indicates whether or not the ?detection of b2 byte error interrupt? has occurred sinc e the last read of this register. the redundant receive sts-3 toh processor block will generate this interrupt anytime it detects a b2 byte error within the incoming sts-3 data- stream. 0 ? indicates that the ?detection of b2 byte error interrupt? has not occurred since the last read of this register. 1 ? indicates that the ?detection of b2 byte error interrupt? has occurred since the last read of this register. 3 detection of b1 byte error interrupt status rur detection of b1 byte error interrupt status: this reset-upon-read bit-field indicates whether or not the ?detection of b1 byte error interrupt? has occurred sinc e the last read of this register. the redundant receive sts-3 toh processor block will generate this interrupt anytime it detects a b1 byte within the incoming sts-3 data- stream. 0 ? indicates that the ?detection of b1 byte error interrupt? has not occurred since the last read of this register. 1 ? indicates that the ?detection of b1 byte error interrupt? has occurred since the last read of this register 2 change of lof defect condition interrupt status rur change of loss of frame (lof) defect condition interrupt status: this reset-upon-read bit-field indicates whether or not the ?change of lof defect condition? interrupt has oc curred since the last read of this register. the redundant receive sts-3 toh processor block will generate this interrupt in response to either of the following events. ? whenever the redundant receive sts-3 toh processor block declares the lof defect condition. ? whenever the redundant receive sts-3 toh processor block clears the lof defect condition. 0 ? indicates that the ?change of lof defect condition? interrupt has not occurred since the last read of this register. 1 ? indicates that the ?change of lo f defect condition? interrupt has occurred since the last read of this register. note: the user can determine whether the redundant receive sts-3 toh processor block is currenly declaring the lof defect condition by reading out the state of bit 2 (lof defect declared) within the ?redundant receive st s-3 transport status register ? byte 0 (address location= 0x1707). 1 change of sef defect condition interrupt status rur change of sef defect condition interrupt status: this reset-upon-read bit-field indicates whether or not the ?change of sef? defect condition interru p t has occurred since the last read of this
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 263 register. the redundant receive sts-3 toh processor block will generate this interrupt in response to either of the following events. ? whenever the redundant receive sts-3 toh processor block declares the sef defect condition. ? whenever the redundant receive sts-3 toh processor block clears the sef defect condition. 0 ? indicates that the ?change of sef defect condition? interrupt has not occurred since the last read of this register. 1 ? indicates that the ?change of sef defect condition? interrupt has occurred since the last read of this register. note: the user can determine whether or not the redundant receive sts-3 toh processor block is currently declaring the sef defect condition by reading out the state of bit 1 (sef defect declared) within the ?redundant receive st s-3 transport status register ? byte 0 (address location= 0x1707). 0 change of los defect condition interrupt status rur change of loss of signal (los) defect condition interrupt status: this reset-upon-read bit-field indicates whether or not the ?change of los defect condition? interrupt has occurred since the last read of this register. the redundant receive sts-3 toh processor block will generate this interrupt in response to either of the following events. ? whenever the redundant receive sts-3 toh processor block declares the los defect condition. ? whenever the redundant receive sts-3 toh processor block clears the los defect condition. 0 ? indicates that the ?change of lo s defect condition? interrupt has not occurred since the last read of this register. 1 ? indicates that the ?change of lo s defect condition? interrupt has occurred since the last read of this register. note: the user can determine whether the redundant receive sts-3 toh processor block is currently declaring the los defect condition by reading out the contents of bit 0 (los defect declared) within the redundant receive sts-3 transport status register ? byte 0 (address location= 0x1707).
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 264 table 164: redundant receive sts-3 transport interrupt enable register ? byte 2 (address location= 0x170d) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 unused change of ais-l defect condition interrupt enable change of rdi-l defect condition interrupt enable r/o r/o r/o r/o r/o r/o r/w r/w 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 ? 2 unused r/o 1 change of ais-l defect condition interrupt enable r/w change of ais-l (line ais) defect condition interrupt enable: this read/write bit-field permits the user to either enable or disable the ?change of ais-l defect condition? interrupt. if the user enables this interrupt, then the XRT94L33 will generate an interrupt in response to either of the following conditions. ? whenever the redundant receive sts-3 toh processor block declares the ?ais-l? defect condition. ? whenever the redundant receive sts-3 toh processor block clears the ?ais-l? defect condition. 0 ? disables the ?change of ais-l defect condition? interrupt. 1 ? enables the ?change of ais-l defect condition? interrupt. note: the user can determi ne if the redundant receive sts-3 toh processor block is currently decl aring the ais-l defect condition by reading out the state of bit 0 (ais-l defect declared) within the ?redundant receive sts-3 trans port status register ? byte 1? (address location= 0x1706). 0 change of rdi-l defect condition interrupt enable r/w change of rdi-l (line remote defect indicator) defect condition interrupt enable: this read/write bit-field permits the user to either enable or disable the ?change of rdi-l defect condition? in terrupt. if the user enables this interrupt, then the XRT94L33 will generate an interrupt in response to either of the following conditions. ? whenever the redundant receive sts-3 toh processor block declares the ?rdi-l? defect condition. ? whenever the redundant receive sts-3 toh processor block clears the ?rdi-l? defect condition. 0 ? disables the ?change of rdi-l defect condition? interrupt. 1 ? enables the ?change of rdi-l defect condition? interrupt.
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 265 table 165: redundant receive sts-3 transport interrupt enable register ? byte 1 (address location= 0x170e) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 new s1 byte interrupt enable change in s1 byte unstable defect condition interrupt enable unused receive toh cap done interrupt enable change in k1, k2 byte unstable defect condition interrupt enable new k1k2 byte value interrupt enable r/w r/w r/o r/o r/o r/w r/w r/w 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 new s1 byte value interrupt enable r/w new s1 byte value interrupt enable: this read/write bit-field permits the user to enable or disable the ?new s1 byte value? interrupt. if the user enables this interrupt, then the redundant receive sts-3 toh processor block will generate this interrupt anytime it receives and accepts a new s1 byte value. the redundant receive sts-3 toh processor block will accept a new s1 byte after it has received it for 8 consecutive sts-3 frames. 0 ? disables the ?new s1 byte value? interrupt. 1 ? enables the ?new s1 byte value? interrupt. 6 change in s1 unstable state interrupt enable r/w change in s1 byte unstable defect condition interrupt enable: this read/write bit-field permits the user to either enable or disable the ?change in s1 byte unstable defect condition? interrupt. if the user enables this bit-field, then the redundant receive sts-3 toh processor block will generate an interrupt in response to either of the following conditions. ? whenever the redundant receive sts-3 toh processor block declares the ?s1 byte unstable? defect condition. ? whenever the redundant receive sts-3 toh processor block clears the ?s1 byte unstable? defect condition. 0 ? disables the ?change in s1 byte unstable defect condition? interrupt. 1 ? enables the ?change in s1 byte unstable defect condition? interrupt. 5 - 3 unused r/o 2 receive toh cap done interrupt enable r/w receive toh capture done ? interrupt enable: this read/write bit-field permits the user to either enable or disable the ?receive toh data capture? interrupt, within the redundant receive sts-3 toh processor block. if this interrupt is enabled, then t he redundant receive sts-3 toh processor block will generate an interrupt anytime it has captured the last toh byte into the capture buffer. note: once the toh (of a given sts-3 frame) has been captured and loaded into the ?receive toh capture? buffer, it will remain there for one sonet frame period. 0 ? disables the ?receive toh capture? interrupt. 1 ? enables the ?receive toh capture? interrupt.
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 266 1 change in k1, k2 byte unstable defect condition interrupt enable r/w change of k1, k2 byte unstable defect condition interrupt enable: this read/write bit-field permits the user to either enable or disable the ?change of k1, k2 byte unstable defect condition? interrupt. if the user enables this interrupt, then the redundant receive sts-3 toh processor block will generate an interrupt in respon se to either of the following events. ? whenever the redundant receive sts-3 toh processor block declares the ?k1, k2 byte unstable defect? condition. ? whenever the redundant receive sts-3 toh processor block clears the ?k1, k2 byte unstable defect? condition. 0 ? disables the ?change in k1, k2 byte unstable defect condition? interrupt 1 ? enables the ?change in k1, k2 byte unstable defect condition? interrupt 0 new k1k2 byte interrupt enable r/w new k1, k2 byte value interrupt enable: this read/write bit-field permits the user to either enable or disable the ?new k1, k2 byte value? in terrupt. if the user enable s this interrupt, then the redundant receive sts-3 toh processor block will generate this interrupt anytime it receives and accepts a new k1, k2 byte value. the redundant receive sts-3 toh processor block will accept a new k1, k2 byte value, after it has received it within 3 (or 5) consecutive sts-3 frames. 0 ? disables the ?new k1, k2 byte value? interrupt. 1 ? enables the ?new k1, k2 byte value? interrupt.
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 267 table 166: redundant receive sts-3 transport interrupt status register ? byte 0 (address location= 0x170f) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 change of sf defect condition interrupt enable change of sd defect condition interrupt enable detection of rei-l event interrupt enable detection of b2 byte error interrupt enable detection of b1 byte error interrupt enable change of lof defect condition interrupt enable change of sef defect condition interrupt enable change of los defect condition interrupt enable r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 change of sf defect condition interrupt enable r/w change of signal failure (sf) defect condition interrupt enable: this read/write bit-field permits the user to either enable or disable the ?change of signal failure (sf) defect condition? interrupt. if the user enables this interrupt, then the XRT94L33 will generate an interrupt in response to any of the following events. ? whenever the redundant receive sts-3 toh processor block declares the sf defect condition. ? whenever the redundant receive sts-3 toh processor block clears the sf defect condition. 0 ? disables the ?change of sf defect condition interrupt?. 1 ? enables the ?change of sf defect condition interrupt?. 6 change of sd defect condition interrupt enable r/w change of signal degrade (sd) defect condition interrupt enable: this read/write bit-field permits the user to either enable or disable the ?change of signal degrade (sd) defect condition? interrupt. if the user enables this interrupt, then the XRT94L33 will generate an interrupt in response to either of the following events. ? whenever the redundant receive sts-3 toh processor block declares the sd defect condition. ? whenever the redundant receive sts-3 toh processor block clears the sd defect condition. 0 ? disables the ?change of sd defect condition interrupt?. 1 ? enables the ?change of sd defect condition interrupt?. 5 detection of rei-l event interrupt enable r/w detection of rei-l (line ? remote error indicator) event interrupt enable: this read/write bit-field permits the user to either enable or disable the ?detection of line ? rei-l event? interrupt. if the user enables this interrupt, then the XRT94L33 will generate an interrupt anytime the redundant receive sts-3 toh processor block de tects an ?rei-l? event, within the incoming sts-3 data-stream. 0 ? disables the ?detection of rei-l event? interrupt. 1 ? enables the ?detection of rei-l event? interrupt. 4 detection of b2 byte error interrupt enable r/w detection of b2 byte error interrupt enable: this read/write bit-field permits the user to either enable or disable the ?detection of b2 byte error? interrupt. if the user enables this interrupt, then the XRT94L33 will g enerate an interru p t an y time the redundant receive
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 268 sts-3 toh processor block detects a b2 byte error within the incoming sts-3 data-stream. 0 ? disables the ?detection of b2 byte error interrupt?. 1 ? enables the ?detection of b2 byte error interrupt?. 3 detection of b1 byte error interrupt enable r/w detection of b1 byte error interrupt enable: this read/write bit-field permits the user to either enable or disable the ?detection of b1 byte error? interrupt. if the user enables this interrupt, then the XRT94L33 will generate an inte rrupt anytime the redundant receive sts-3 toh processor block detects a b1 byte error within the incoming sts-3 data-stream. 0 ? disables the ?detection of b1 byte error interrupt?. 1 ? enables the ?detection of b1 byte error interrupt?. 2 change of lof defect condition interrupt enable r/w change of loss of frame (lof) defect condition interrupt enable: this read/write bit-field permits the user to either enable or disable the ?change of lof defect condition? in terrupt. if the user enables this interrupt, then the XRT94L33 will generate an interrupt in response to either of the following conditions. ? whenever the redundant receive sts-3 toh processor block declares the ?lof? defect condition. ? whenever the redundant receive sts-3 toh processor clears the ?lof? defect condition. 0 ? disables the ?change of lof defect condition interrupt. 1 ? enables the ?change of lof defect condition? interrupt. 1 change of sef defect condition interrupt enable r/w change of sef defect condition interrupt enable: this read/write bit-field permits the user to either enable or disable the ?change of sef defect condition? interrupt. if the user enables this interrupt, then the XRT94L33 will generate an interrupt in response to either of the following conditions. ? whenever the redundant receive sts-3 toh processor block declares the ?sef? defect condition. ? whenever the redundant receive sts-3 toh processor block clears the ?sef? defect condition. 0 ? disables the ?change of sef defect condition interrupt?. 1 ? enables the ?change of sef defect condition interrupt?. 0 change of los defect condition interrupt enable r/w change of loss of signal (los) defect condition interrupt enable: this read/write bit-field permits the user to either enable or disable the ?change of lof defect condition? in terrupt. if the user enables this interrupt, then the XRT94L33 will generate an interrupt in response to either of the following conditions. ? whenever the redundant receive sts-3 toh processor block declares the ?lof? defect condition. ? whenever the redundant receive sts-3 toh processor block clears the ?lof? defect condition. 0 ? disables the ?change of lof defect condition interrupt. 1 ? enables the ?change of lof defect condition? interrupt.
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 269 table 167: redundant receive sts-3 transport ? b1 byte error count register ? byte 3 (address location= 0x1710) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 b1_byte_error_count[31:24] rur rur rur rur rur rur rur rur 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 - 0 b1_byte_error_ count[31:24] rur b1 byte error count ? msb: this reset-upon-read register, along with ?redundant receive sts-3 transport ? b1 byte error count register ? bytes 2 through 0; function as a 32 bit counter, which is incremented anytime the redundant receive sts-3 toh processor block detects a b1 byte error. note: 1. if the redundant receive sts-3 to h processor block is configured to count b1 byte errors on a ?per-bit? bas is, then it will increment this 32-bit counter by the number of bits, within the b1 byte (of each incoming sts-3 frame) that are in error. 2. if the redundant receive sts-3 to h processor block is configured to count b1 byte error on a ?per-frame? ba sis, then it will increment this 32-bit counter each time that receives an st s-3 frame that contains an erred b1 byte.
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 270 table 168: redundant receive sts-3 transport ? b1 byte error count register ? byte 2 (address location= 0x1711) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 b1_byte_error_count[23:16] rur rur rur rur rur rur rur rur 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 - 0 b1_byte error_count [23:16] rur b1 byte error count (bits 23 through 16): this reset-upon-read register, along with ?redundant receive sts-3 transport ? b1 byte error count register ? bytes 3, 1 and 0; function as a 32 bit counter, which is incremented anytime the redundant receive sts-3 toh processor block detects a b1 byte error. note: 1. if the redundant receive sts-3 to h processor block is configured to count b1 byte errors on a ?per-bit? basi s, then it will increment this 32-bit counter by the number of bits, within the b1 byte (of each incoming sts-3 frame) that are in error. 2. if the redundant receive sts-3 to h processro block is configured to count b1 byte errors on ?per-frame? bas is, then it will increment this 32-bit counter each time that it receives an sts-3 frame that contains an erred b1 byte.
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 271 table 169: redundant receive sts-3 transport ? b1 byte error count register ? byte 1 (address location= 0x1712) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 b1_byte error_count[15:8] rur rur rur rur rur rur rur rur 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 - 0 b1_byte_error_ count [15:8] rur b1 byte error count ? (bits 15 through 8) this reset-upon-read register, along with ?redundant receive sts-3 transport ? b1 byte error count register ? bytes 3, 2 and 0; function as a 32 bit counter, which is incremented anytime the redundant receive sts-3 toh processor block detects a b1 byte error note: 1. if the redundant receive sts-3 toh processor block is configured to count b1 byte errors on a ?per-bit? basis , then it will increment this 32-bit counter by the number of bits, within the b1 byte (of each incoming sts-3 frame) that are in error. 2. if the redundant receive sts-3 toh processor block is configured to count b1 byte errors on a ?per-frame? basis, then it will increment this 32-bit counter by the number of frames that contain erred b1 bytes.
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 272 table 170: redundant receive sts-3 transport ? b1 byte error count register ? byte 0 (address location= 0x1713) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 b1_byte error_count[7:0] rur rur rur rur rur rur rur rur 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 - 0 b1_byte_error_ count [7:0] rur b1 byte error count ? lsb: this reset-upon-read register, along with ?redundant receive sts-3 transport ? b1 byte error count register ? bytes 3 through 1; function as a 32 bit counter, which is incremented anytime the redundant receive sts-3 toh processor block detects a b1 byte error. note: 1. if the redundant receive sts-3 to h processor block is configured to count b1 byte errors on a ?per-bit? basis , then it will increment this 32-bit counter by the number of bits, within the b1 byte (of each incoming sts-3 frame) that are in error. 2. if the redundant receive sts-3 to h processor block is configured to count b1 byte errors on a ?per-frame? basis, then it will increment this 32-bit counter each time that it receives an sts-3 frame that contains an erred b1 byte.
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 273 table 171: redundant receive sts-3 transport ? b2 byte error count register ? byte 3 (address location= 0x1714) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 b2_byte_error_count[31:24] rur rur rur rur rur rur rur rur 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 - 0 b2_byte_error_ count [31:24] rur b2 byte error count ? msb: this reset-upon-read register, along with ?redundant receive sts-3 transport ? b2 byte error count register ? bytes 2 through 0; function as a 32 bit counter, which is incremented anytime the redundant receive sts-3 toh processor block detects a b2 byte error within the incoming sts-3 data-stream. note: 1. if the receive sts-3 toh processor block is configured to count b2 byte errors on a ?per-bit? basis, then it will increment this 32-bit counter by the number of bits, within the b2 bytes (of each incoming sts-3 frame) that are in error. 2. if the receive sts-3 toh processor block is configured to count b2 byte errors on a ?per-frame? basis, then it will increment this 32-bit counter each time that it receives an sts-3 fram e that contains at least one erred b2 byte.
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 274 table 172: redundant receive sts-3 transport ? b2 byte error count register ? byte 2 address location= 0x1715) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 b2_byte_error_count[23:16] rur rur rur rur rur rur rur rur 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 - 0 b2_byte_error_ count [23:16] rur b2 byte error count (bits 23 through 16): this reset-upon-read register, along with ?redundant receive sts-3 transport ? b2 byte error count register ? bytes 3, 1 and 0; function as a 32 bit counter, which is incremented anytime the redundant receive sts-3 toh processor block detects a b2 byte error. note: 1. if the receive sts-3 toh processor block is configured to count b2 byte errors on a ?per-bit? basis, then it will increment this 32-bit counter by the number of bits, within the b2 byte (of each incoming sts-3 frame) that are in error. 2. if the redundant receive sts-3 to h processor block is configured to count b2 byte errors on a ?per-frame? basis, then it will increment this 32-bit counter each time that it receives an sts-3 frame that contains at least one erred b2 byte.
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 275 table 173: redundant receive sts-3 transport ? b2 byte error count register ? byte 1 (address location= 0x1716) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 b2_byte_error_count[15:8] rur rur rur rur rur rur rur rur 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 - 0 b2_byte_error_ count [15:8] rur b2 byte error count ? (bits 15 through 8) this reset-upon-read register, along with ?redundant receive sts-3 transport ? b2 byte error count register ? bytes 3, 2 and 0; function as a 32 bit counter, which is incremented anytime the redundant receive sts-3 toh processor block detects a b2 byte error within the incoming sts-3 data-stream. note: 1. if the redundant receive sts-3 toh processor block is configured to count b2 byte errors on a ?per-bit? basis , then it will increment this 32-bit counter by the number of bits, within the b2 bytes (of each incoming sts-3 frame) that are in error. 2. if the redundant receive sts-3 toh processor block is configured to count b2 byte errors on a ?per-frame? basis, then it will increment this 32-bit counter each time that it receives an sts-3 frame that contains at least one erred b2 byte.
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 276 table 174: redundant receive sts-3 transport ? b2 byte error count register ? byte 0 (address location= 0x1717) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 b2_byte error_count[7:0] rur rur rur rur rur rur rur rur 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 - 0 b2_byte error_count[7:0] rur b2 byte error count ? lsb: this reset-upon-read register, along with ?redundant sts-3 receive transport ? b2 byte error count register ? bytes 3 through 1; function as a 32 bit counter, which is in cremented anytime the redundant receive sts-3 toh processor block detects a b2 byte error within the incoming sts-3 data-stream. note: 1. if the redundant receive sts-3 toh processor block is configured to count b2 byte errors on a ?per-bit? basis, then it will increment this 32-bit counter by the number of bits, with in the b2 bytes (of each incoming sts-3 frame) that are in error. 2. if the redundant receive sts-3 toh processor block is configured to count b2 byte errors on a ?per-frame? basis, then it will increment this 32- bit counter each time that it receives an sts-3 frame that contains at least one erred b2 bytes.
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 277 table 175: redundant receive sts-3 transport ? rei-l event count register ? byte 3 (address location= 0x1718) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 rei-l_event_count[31:24] rur rur rur rur rur rur rur rur 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 - 0 rei-l_event_count [31:24] rur rei-l event count ? msb: this reset-upon-read register, along with ?redundant receive sts-3 transport ? rei-l event count register ? bytes 2 through 0; function as a 32 bit counter, which is incremented anytime the redundant receive sts-3 toh processor block detects a line - remote error indicator event within the incoming sts-3 data- stream. note: 1. if the redundant receive sts-3 toh processor block is configured to count rei-l events on a ?per-bit? basis, then it will increment this 32 bit counter by the value within the rei-l fields of the m1 byte within the each incoming sts-3 frame. 2. if the redundant receive sts-3 toh processor block is configured to count rei-l events on a ?per-frame? basis, then it will increment this 32 bit counter each time that it receives an sts-3 frame that contains a ?non-zero? m1 byte value.
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 278 table 176: redundant receive sts-3 transport ? rei-l event count register ? byte 2 (address location= 0x1719) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 rei-l_event_count[23:16] rur rur rur rur rur rur rur rur 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 - 0 rei-l_event_count [23:16] rur rei-l event count (bits 23 through 16): this reset-upon-read register, along with ?redundant receive sts- 3 transport ? rei-l event count regist er ? bytes 3, 1 and 0; function as a 32 bit counter, which is in cremented anytime the redundant receive sts-3 toh processor block detects a line ? remote error indicator event within the incoming sts-3 data-stream. note: 1. if the redundant receive sts-3 to h processor block is configured to count rei-l events on a ?per-bit? ba sis, then it will increment this 32 bit counter by the value within the rei-l fields of the m1 byte within each incoming sts-3 frame. 2. if the redundant receive sts-3 toh processor block is configured to count rei-l events on a ?per-frame ? basis then it will increment this 32 bit counter each time that it rece ives an sts-3 frame that contains a non-zero m1 byte value.
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 279 table 177: redundant receive sts-3 transport ? rei-l event count register ? byte 1 (address location= 0x171a) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 rei-l_event_count[15:8] rur rur rur rur rur rur rur rur 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 - 0 rei-l event_count[15:8] rur rei-l event count ? (bits 15 through 8) this reset-upon-read register, along with ?redundant receive sts-3 transport ? rei-l error count register ? bytes 3, 2 and 0; function as a 32 bit counter, which is incremented anytime the redundant receive sts-3 toh processor block detects a line ? remote error indicator event within the incoming sts-3 data- stream. note: 1. if the redundant receive sts-3 toh processor block is configured to count rei-l events on a ?per-bit? basis, then it will increment this 32 bit counter by the value within the rei-l fields of the m1 byte within each incoming sts-3 frame. 2. if the redundant receive sts-3 toh processor block is configured to count rei-l events on a ?per-frame? basis, then it will increment this 32 bit counter each time that it receives an sts-3 frame that contains a non-zero m1 byte value.
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 280 table 178: redundant receive sts-3 transport ? rei-l event count register ? byte 0 (address location= 0x171b) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 rei-l_event_count[7:0] rur rur rur rur rur rur rur rur 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 - 0 rei-l_event_count [7:0] rur rei-l event count ? lsb: this reset-upon-read register, along with ?redundant receive sts-3 transport ? rei-l error count register ? bytes 3 through 1; function as a 32 bit counter, which is incremented anytime the redundant receive sts-3 toh processor block detects a line ? remote error indicator event within the incoming sts-3 data-stream. note: 1. if the redundant receive sts-3 toh processor block is configured to count rei-l events on a ?per-bit? basis, then it will increment this 32 bit counter by the value within the rei-l fields of the m1 byte within each incoming sts-3 frame. 2. if the redundant receive sts-3 toh processor blolck is configured to count rei-l events on a ?per-frame? basis , then it will increment this 32 bit counter each time that it receives an sts-3 frame that contains a non- zero m1 byte value.
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 281 table 179: redundant receive sts-3 transport ? received k1 byte value register (address location= 0x171f) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 filtered_k1_byte_value[7:0] r/o r/o r/o r/o r/o r/o r/o r/o 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 ? 0 filtered_k1_byte_value[7:0] r/o filtered/accepted k1 byte value: these read-only bit-fields contain the value of the most recently ?filtered? k1 byte value, that the redundant receive sts-3 toh processor block has received. these bit-fields are valid if the k1/k2 pair (to which it belongs) has been received for 3 consecutive sts-3 frames. this register should be polled by software in order to determine various aps codes. table 180: redundant receive sts-3 transport ? receive k2 byte value register (address location= 0x1723) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 filtered_k2_byte_value[7:0] r/o r/o r/o r/o r/o r/o r/o r/o 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 ? 0 filtered_k2_byte_val ue [7:0] r/o filtered/accepted k2 byte value: these read-only bit-fields contain the value of the most recently ?filtered? k2 byte value, that the redundant receive sts-3 toh processor block has received. these bit-fields are valid if the k1/k2 pair (to which it belongs) has been received for 3 consecutive sts-3 frames. this register should be polled by software in order to determine various aps codes.
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 282 table 181: redundant receive sts-3 transport ? received s1 byte value register (address location= 0x1727) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 filtered_s1_value[7:0] r/o r/o r/o r/o r/o r/o r/o r/o 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 ? 0 filtered_s1_value[7:0] r/o filtered/accepted s1 value: these read-only bit-fields contain the value of the most recently ?filtered? s1 byte value that the redundant receive sts-3 toh processor block has received. these bit-fields are valid if it has been received for 8 consecutive sts-3 frames.
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 283 table 182: redundant receive sts-3 transport ? in-sync threshold value (address location=0x172b) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 unused frpatout[1:0] frpatin[1:0] unused r/o r/o r/o r/w r/w r/w r/w r/o 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 ? 5 unused r/o 4 ? 3 frpatout[1:0] r/w framing pattern ? sef declaration criteria: these two read/write bit-fields permit the user to define the sef defect declaration criteria for the redundant receive sts-3 toh processor block. the relationship between the state of these bit-fields and the corresponding sef defect declaration criteria are presented below. frpatout[1:0] sef defect declaration criteria 00 01 the redundant receive sts-3 toh processor block will declare the sef defect condition if either of the following conditions are true for four consecutive sonet frame periods. ? if the last (of the 3) a1 bytes, in the sts-3 data stream is erred, or ? if the first (of the 3) a2 bytes, in the sts-3 data stream, is erred. hence, for this selection, a total of 16 bits are evaluated for sef defect declaration. 10 the redundant receive sts-3 toh processor block will declare the sef defect condition if either of the following conditions are true for four consecutive sonet frame periods. ? if the last two (of the 3) a1 bytes, in the sts-3 data stream, are erred, or ? if the first two (of the 3) a2 bytes, in the sts-3 data stream, are erred. hence, for this selection, a total of 32 bits are evaluated for sef defect declaration. 11 the redundant receive sts-3 toh processor block will declare the sef defect condition if either of the following conditions are true for four consecutive sonet frame periods. ? if the last three (of the 3) a1 bytes, in the sts- 3 data stream, are erred, or ? if the first three (of the 3) a2 bytes, in the sts- 3 data stream, are erred. hence, for this selection, a total of 48 bits are evaluated for sef defect declaration. 2 - 1 frpatin[1:0] r/w framing pattern ? sef defect clearance criteria:
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 284 these two read/write bit-fields permit the user to define the ?sef defect clearance? criteria for the redundant receive sts-3 toh processor block. the relationship between the state of these bit-fields and the corresponding sef defect clearance criteria are presented below. frpatin[1:0] sef defect clearance criteria 00 01 the redundant receive sts-3 toh processor block will clear the sef defect condition if both of the following conditions are true for two consecutive sonet frame periods. ? if the last (of the 3) a1 bytes, in the sts-3 data stream is un-erred, and ? if the first (of the 3) a2 bytes, in the sts-3 data stream, is un-erred. hence, for this selection, a total of 16 bits/frame are evaluated for sef defect clearance. 10 the redundant receive sts-3 toh processor block will clear the sef defect condition if both of the following conditions are true for two consecutive sonet frame periods. ? if the last two (of the 3) a1 bytes, in the sts-3 data stream, are un-erred, and ? if the first two (of the 3) a2 bytes, in the sts-3 data stream, are un-erred. hence, for this selection, a total of 32 bits/frame are evaluated for sef defect clearance. 11 the redundant receive sts-3 toh processor block will clear the sef defect condition if both of the following conditions are true for two consecutive sonet frame periods. ? if the last three (of the 3) a1 bytes, in the sts-3 data-stream, are un-erred, and ? if the first three (of the 3) a2 bytes, in the sts- 3 data stream, are un-erred. hence, for this selection, a total of 48 bits/frame are evaluated for sef defect declaration. 0 unused r/o
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 285 table 183: redundant receive sts-3 transport ? los threshold value - msb (address location= 0x172e) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 los_threshold[15:8] r/w r/w r/w r/w r/w r/w r/w r/w 1 1 1 1 1 1 1 1 b it n umber n ame t ype d escription 7 - 0 los_threshold[15:8] r/w los threshold value ? msb: these read/write bits, along the contents of the ?redundant receive sts-3 transport ? los threshold value ? lsb? register specify the number of consecut ive (all zero) bytes that the redundant receive sts-3 toh processor block must detect before it can declare the lo s defect condition. table 184: redundant receive sts-3 transport ? los threshold value - lsb (address location= 0x172f) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 los_threshold[7:0] r/w r/w r/w r/w r/w r/w r/w r/w 1 1 1 1 1 1 1 1 b it n umber n ame t ype d escription 7 - 0 los_threshold[7:0] r/w los threshold value ? lsb: these read/write bits, along the contents of the ?redundant receive sts-3 transport ? los threshold value ? msb? register specify the number of c onsecutive (all zero) bytes that the redundant receive sts-3 toh processor block mu st detect before it can declare the los defect condition.
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 286 table 185: redundant receive sts-3 transport ?receive sf set monitor interval ? byte 2 (address location= 0x1731) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 sf_set_monitor_window[23:16] r/w r/w r/w r/w r/w r/w r/w r/w 1 1 1 1 1 1 1 1 b it n umber n ame t ype d escription 7 - 0 sf_set_monitor_ window [23:16] r/w sf_set_monitor_interval ? msb: these read/write bits, along the contents of the ?redundant receive sts-3 transport ? sf set monitor interval ? byte 1 and byte 0? registers permit the user to specify the length of the ?monitoring period? (in terms of ms) for sf (signal failure) defect declaration. when the redundant receive sts-3 toh processor block is checking the incoming sts-3 signal in order to determine if it should declare the sf defect condition, it will accumulate b2 byte errors throughout the user-specified ?sf defect declaration monitoring period?. if, during this ?sf defect declaration monitoring period?, the redundant receive sts-3 toh processor block accumulates more b2 byte errors than that specified within the ?redundant receive sts-3 transport sf set threshold? register, then the redundant receive sts-3 toh processor block will declare the sf defect condition. notes: 1. the value that the user writ es into these three (3) ?sf set monitor window? registers, specifies the duration of the ?sf defect declaration monitori ng period, in terms of ms. 2. this particular register byte contains the ?msb? (most significant byte) value of the th ree registers that specify the ?sf defect declaration monitoring period?.
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 287 table 186: redundant receive sts-3 transport ? receive sf set monitor interval ? byte 1 (address location= 0x1732) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 sf_set_monitor_window[15:8] r/w r/w r/w r/w r/w r/w r/w r/w 1 1 1 1 1 1 1 1 b it n umber n ame t ype d escription 7 - 0 sf_set_monitor_window [15:8] r/w sf_set_monitor_interval (bits 15 through 8): these read/write bits, along the contents of the ?redundant receive sts-3 transport ? sf se t monitor interval ? byte 2 and byte 0? registers permit the user to specify the length of the ?monitoring period? (in terms of ms) for sf (signal failure) defect declaration. when the redundant receive sts-3 toh processor block is checking the incoming sts-3 signal in order to determine if it should declare the sf defect condition, it will accumulate b2 byte errors throughout the user s pecified ?sf defect declaration monitoring period?. if, during th is ?sf defect declaration monitoring period? the redundant receive sts-3 toh processor block accumu lates more b2 byte errors than that specified within the ?redundant receive sts-3 transport sf set threshold? register, then the redundant receive sts-3 toh processor block will declare the sf defect condition. note: the value that the user wr ites into these three (3) ?sf set monitor window? registers, specifies the duration of the ?sf defect declaration? monitori ng period, in terms of ms.
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 288 table 187: redundant receive sts-3 transport ? receive sf set monitor interval ? byte 0 (address location= 0x1733) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 sf_set_monitor_window[7:0] r/w r/w r/w r/w r/w r/w r/w r/w 1 1 1 1 1 1 1 1 b it n umber n ame t ype d escription 7 - 0 sf_set_monitor_window[7:0] r/w sf_set_monitor_interval ? lsb: these read/write bits, along the contents of the ?redundant receive sts-3 transport ? sf set monitor interval ? byte 2 and byte 1? registers permit the user to specify the length of the ?monitoring period? (in terms of ms) for sf (signal failure) defect declaration. when the redundant receive sts-3 toh processor block is checking the incoming sts-3 signal in order to determine if it should declare the sf defect condition, it will accumulate b2 byte errors throughout the user- specified ?sf defect declaration monitoring period?. if, during this ?sf defect declaration monitoring period?, the redundant receive sts-3 toh processor block accumulates more b2 byte e rrors than that specified within the ?redundant receive sts-3 transport sf set threshold? register, then the redundant receive sts-3 toh processor block will declare the sf defect condition. notes: 1. the value that the user writes into these three (3) ?sf set monitor window? registers, specifies the duration of the ?sf defect declaration? monitoring period, in terms of ms. 2. this particular register byte contains the ?lsb? (least significant byte) value of the three registers that specify the ?sf defect declaration monitoring period?.
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 289 table 188: redundant receive sts-3 transport ? receive sf set threshold ? byte 1 (address location= 0x1736) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 sf_set_threshold[15:8] r/w r/w r/w r/w r/w r/w r/w r/w 1 1 1 1 1 1 1 1 b it n umber n ame t ype d escription 7 - 0 sf_set_threshold[15:8] r/w sf_set_threshold ? msb: these read/write bits, along the contents of the ?redundant receive sts-3 transport ? sf set threshold ? byte 0? registers permit the user to specify the number of b2 byte errors that will cause t he redundant receive sts-3 toh processor block to declare the sf (signal failure) defect condition. when the redundant receive sts-3 toh processor block is checking the incoming sts-3 signal, in order to determine if it should declare the sf defect condition, it will accumulate b2 byte errors throughout the ?sf defect declaration monitoring period?. if the number of accumulated b2 byte errors exceeds that value, which is of pr ogrammed into this and the ?redundant receive sts-3 transport sf set threshold ? byte 0? register, then the redundant receive sts-3 toh processor block will declare the sf defect condition.
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 290 table 189: redundant receive sts-3 transport ? receive sf set threshold ? byte 0 address location= 0x1737) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 sf_set_threshold[7:0] r/w r/w r/w r/w r/w r/w r/w r/w 1 1 1 1 1 1 1 1 b it n umber n ame t ype d escription 7 - 0 sf_set_threshold[7: 0] r/w sf_set_threshold ? lsb: these read/write bits, along the contents of the ?redundant receive sts-3 transport ? sf set threshold ? byte 1? registers permit the user to specify the number of b2 byte errors that will cause the redundant receive sts-3 toh processor block to declare the sf (signal failure) defect condition. when the redundant receive sts-3 toh processor block is checking the incoming sts-3 signal in order to determine if it should declare the sf defect conditi on, it will accumulate b2 byte errors throughout the ?sf defect monitoring period?. if the number of accumulated b2 byte errors exceeds that which has been programmed into this and the ?redundant receive sts-3 transport sf set threshold ? byte 1? register, then the redundant receive sts-3 toh processor block will declares the sf defect condition.
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 291 table 190: redundant receive sts-3 transport ? receive sf clear threshold ? byte 1 (address location= 0x173a) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 sf_clear_threshold[15:8] r/w r/w r/w r/w r/w r/w r/w r/w 1 1 1 1 1 1 1 1 b it n umber n ame t ype d escription 7 - 0 sf_clear_threshold [15:8] r/w sf_clear_threshold ? msb: these read/write bits, along the contents of the ?redundant receive sts-3 transport ? sf clear threshold ? byte 0? registers permit the user to specify the upper limit for the number of b2 byte errors that will cause the redundant receive sts-3 toh processor block to clear the sf (signal failure) defect condition. when the redundant receive sts-3 toh processor block is checking the incoming sts-3 signal in order to determine if it should clear the sf defect condition, it will accumulate b2 byte errors throughout the ?sf defect clearance monitoring period?. if the number of accumulated b2 byte errors is less than that programmed into this and the ?redundant receive sts-3 transport sf clear threshold ? byte 0? register, then the redundant receive sts-3 toh processor block will clear the sf defect condition.
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 292 table 191: redundant receive sts-3 transport ? receive sf clear threshold ? byte 0 (address location= 0x173b) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 sf_clear_threshold[7:0] r/w r/w r/w r/w r/w r/w r/w r/w 1 1 1 1 1 1 1 1 b it n umber n ame t ype d escription 7 - 0 sf_clear_threshold [7:0] r/w sf_clear_threshold ? lsb: these read/write bits, along the contents of the ?redundant receive sts-3 transport ? sf clear threshold ? byte 1? registers permit the user to specify the upper limit for the number of b2 bit errors that will cause the redundant receive sts-3 toh processor block to clear the sf (signal failure) defect condition. when the redundant receive sts-3 toh processor block is checking the incoming sts-3 signal in order to determine if it should clear the sf defect condition, it will accumulate b2 byte errors throughout the ?sf defect clearance monitoring period?. if the number of accumulated b2 byte errors is less than that programmed into this and the ?redundant receive sts-3 transport sf clear threshold ? byte 1? register, then the redundant receive sts-3 toh processor block will clear the sf defect condition.
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 293 table 192: redundant receive sts-3 transport ? receive sd set monitor interval ? byte 2 (address location= 0x173d) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 sd_set_monitor_window[23:16] r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7-0 sd_set_monitor_window [23:16] r/w sd_set_monitor_interval ? msb: these read/write bits, along the contents of the ?redundant receive sts-3 transport ? sf set monitor interval ? byte 1 and byte 0? registers permit the user to specify the length of the ?monitoring period? (in terms of ms) for sd (signal degrade) defect declaration. when the redundant receive sts-3 toh processor block is checking the incoming sts-3 signal, in order to determine if it should declare sd defect condition, it will accumulate b2 byte errors throughout the user- specified ?sd defect declarat ion monitoring period?. if, during this ?sd defect declaration monitoring period?, the redundant receive sts-3 toh processor block accumulates more b2 byte errors than that specified within the ?redundant receive sts-3 transport sd set threshold? register, then the redundant receive sts-3 toh processor block will declare the sd defect condition. notes: 1. the value that the user writes into these three (3) ?sd set monitor window? registers, specifies the duration of the ?sd defect declaration monitoring period?, in terms of ms. 2. this particular register byte contains the ?msb? (most signficant byte) value of the three registers that specify the ?sd defect declaration monitoring period?.
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 294 table 193: redundant receive sts-3 transport ? receive sd set monitor interval ? byte 1 (address location= 0x173e) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 sd_set_monitor_window[15:8] r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7-0 sd_set_monitor_window[15:8] r/w sd_set_monitor_interval ? bits 15 through 8: these read/write bits, along the contents of the ?redundant receive sts-3 transport ? sd set monitor interval ? byte 2 and byte 0? registers permit the user to specify the length of the ?monitoring period? (in terms of ms) for sd (signal degrade) defect declaration. when the redundant receive sts-3 toh processor block is checking the incoming sts-3 signal in order to determine if it should declare the sd defect condition, it will accumulate b2 byte errors throughout the user- specified ?sd defect declaration monitoring period?. if, during this ?sd defect declaration monitoring period? the redundant receive sts-3 toh processor block accumulates more b2 byte errors than that specified within the ?redundant receive sts-3 transport sd set threshold? register, then the redundant receive sts-3 toh processor block will declare the sd defect condition. note: the value that the user writes into these three (3) ?sd set monitor window? registers, specifies the duration of the ?sd defect declaration? monitoring period, in terms of ms.
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 295 table 194: redundant receive sts-3 transport ? receive sd set monitor interval ? byte 0 (address location= 0x173f) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 sd_set_monitor_window[7:0] r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7-0 sd_set_monitor_window[ 7:0] r/w sd_set_monitor_interval ? lsb: these read/write bits, along the contents of the ?redundant receive sts-3 transport ? sd set monitor interval ? byte 2 and byte 1? registers permit the user to specify the length of the ?monitoring period? (in terms of ms) for sd (signal degrade) defect declaration. when the redundant receive sts-3 toh processor block is checking the incoming sts-3 signal in order to determine if it should declare the sd defect condition, it will accumulate b2 byte errors throughout the user- specified ?sd defect declarat ion monitoring period?. if, during the ?sd defect declaration monitoring period?, the redundant receive sts-3 toh processor block accumulates more b2 byte e rrors than that specified within the ?redundant receive sts-3 transport sd set threshold? register, then the redundant receive sts-3 toh processor block will declare the sd defect condition. notes: 1. the value that the user writes into these three (3) ?sd set monitor window? registers, specifies the duration of the ?sd defect declaration? monitoring period, in terms of ms. 2. this particular register byte contains the ?lsb? (least significant byte) value of the three registers that specify the ?sd defect declaration monitoring period?.
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 296 table 195: redundant receive sts-3 transport ? receive sd set threshold ? byte 1 (address location= 0x1742) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 sd_set_threshold[15:8] r/w r/w r/w r/w r/w r/w r/w r/w 1 1 1 1 1 1 1 1 b it n umber n ame t ype d escription 7 - 0 sd_set_threshold[15:8] r/w sd_set_threshold ? msb: these read/write bits, along the contents of the ?redundant receive sts-3 transport ? sd set threshold ? byte 0? registers permit the user to specify the number of b2 byte errors that will cause t he redundant receive sts-3 toh processor block to declare the sd (signal degrade) defect condition. when the redundant receive sts-3 toh processor block is checking the incoming sts-3 signal in order to determine if it should declare the sd defect condition, it will accumulate b2 byte errors throughout the ?sd defect declaration monitoirng period?. if the number of accumulated b2 byte errors exceeds that value, which is programm ed into this and the ?redundant receive sts-3 transport sd set threshold ? byte 0? register, then the redundant receive sts-3 toh processor block will declare the sd defect condition.
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 297 table 196: redundant receive sts-3 transport ? receive sd set threshold ? byte 0 (address location= 0x1743) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 sd_set_threshold[7:0] r/w r/w r/w r/w r/w r/w r/w r/w 1 1 1 1 1 1 1 1 b it n umber n ame t ype d escription 7 - 0 sd_set_threshold[7:0] r/w sd_set_threshold ? lsb: these read/write bits, along the contents of the ?redundant receive sts-3 transport ? sd set threshold ? byte 1? registers permit the user to specify the number of b2 byte errors that will cause t he redundant receive sts-3 toh processor block to declare the sd (signal degrade) defect condition. when the redundant receive sts-3 toh processor block is checking the incoming sts-3 signal in order to determine if it should declare the sd defect condition, it will accumulate b2 byte errors throughout the ?sd defect monitoring period?. if the number of accumulated b2 byte errors exceeds that which has been programmed into this and the ?redundant receive sts-3 transport sd set threshold ? byte 1? register, then the redundant receive sts-3 toh processor block will declare the sd defect condition.
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 298 table 197: redundant receive sts-3 transport ? receive sd clear threshold ? byte 1 (address location= 0x1746) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 sd_clear_threshold[15:8] r/w r/w r/w r/w r/w r/w r/w r/w 1 1 1 1 1 1 1 1 b it n umber n ame t ype d escription 7 - 0 sd_clear_threshold[15:8] r/w sd_clear_threshold ? msb: these read/write bits, along the contents of the ?redundant receive sts-3 transport ? sd clear threshold ? byte 0? registers permit the user to specify the upper limit for the number of b2 byte errors that will cause the redundant receive sts-3 toh processor block to clear the sd (signal degrade) defect condition. when the redundant receive sts-3 toh processor block is checking the incoming sts-3 signal in order to determine if it should clear the sd defect condition, it will accumulate b2 byte errors throughout the ?sd defect clearance monitoring period?. if the number of accumulated b2 byte errors is less than that programmed into this and the ?redundant receive sts-3 transport sd clear threshold ? byte 0? register, then the redundant receive sts-3 toh processor block will clear the sd defect condition.
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 299 table 198: redundant receive sts-3 transport ? receive sd clear threshold ? byte 1 (address location= 0x1747) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 sd_clear_threshold[7:0] r/w r/w r/w r/w r/w r/w r/w r/w 1 1 1 1 1 1 1 1 b it n umber n ame t ype d escription 7 - 0 sd_clear_threshold[7:0] r/w sd_clear_threshold ? lsb: these read/write bits, along the contents of the ?redundant receive sts-3 transport ? sd clear threshold ? byte 1? registers permit the user to specify the upper limit for the number of b2 byte errors that will cause the redundant receive sts-3 toh processor block to clear the sd (signal degrade) defect condition. when the redundant receive sts-3 toh processor block is checking the incoming sts-3 signal in order to determine if it should clear the sd defect condition, it will accumulate b2 byte errors, throughout the ?sd defect clearance monitoring period?. if the number of accumulated b2 byte errors is less than that programmed into this and the ?redundant receive sts-3 transport sd clear threshold ? byte 1? register, then the redundant receive sts-3 toh processor block will clear the sd defect condition.
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 300 table 199: redundant receive sts-3 transport ? force sef condition register (address location= 0x174b) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 unused sef force r/o r/o r/o r/o r/o r/o r/o r/w 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 ? 1 unused r/o 0 sef force r/w sef force: this read/write bit-field permits the user to force the redundant receive sts-3 toh processor block to declare the sef defect condition. the redundant receive sts-3 toh processor block will then attempt to reacquire framing. writing a ?1? into this bit-field c onfigures the redundant receive sts-3 toh processor block to declare the sef defect. the redundant receive sts-3 toh processor block will automatically set this bit-field to ?0? once it has reacquired framing (e.g., has detec ted two consecutive sts-3 frames with the correct a1 and a2 bytes).
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 301 table 200: redundant receive sts-3 transport ? receive sd burst error tolerance ? byte 1 (address location= 0x1752) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 sd_burst_tolerance[15:8] r/w r/w r/w r/w r/w r/w r/w r/w 1 1 1 1 1 1 1 1 b it n umber n ame t ype d escription 7 - 0 sd_burst_ tolerance [15:8] r/w sd_burst_tolerance ? msb: these read/write bits, along with the contents of the ?redundant receive sts-3 transport ? sd burst tolerance ? byte 0? registers permit the user to specify the maximum number of b2 bit errors that the redundant receive sts-3 toh processor block can accumulate during a single sub- interval period (e.g., an sts-3 frame period), when determining whether or not to declare the sd (signal degrade) defect condition. note: the purpose of this feature is to permit the user to provide some level of b2 byte error burst filtering, when the redundant receive sts-3 toh processor block is accumulating b2 byte errors in order to declare the sd defect condition. the user can implement this feature in order to config ure the redundant receive sts-3 toh processor block to detect b2 bit errors in multiple ?sub- interval? periods before it will dec lare the sd defect condition.
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 302 table 201: redundant receive sts-3 transport ? receive sd burst error tolerance ? byte 0 (address location= 0x1753) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 sd_burst_tolerance[7:0] r/w r/w r/w r/w r/w r/w r/w r/w 1 1 1 1 1 1 1 1 b it n umber n ame t ype d escription 7 - 0 sd_burst_ tolerance [7:0] r/w sd_burst_tolerance ? lsb: these read/write bits, along with t he contents of the ?redundant receive sts-3 transport ? sd burst tolerance ? byte 1? registers permit the user to specify the maximum number of b2 bi t errors that the redundant receive sts-3 toh processor block can accumulate during a single sub-interval period (e.g., an sts-3 frame period), when determining whether or not to declare the sd (signal degrade) defect condition. note: the purpose of this feature is to permit the user to provide some level of b2 byte error burst filtering, when the redundant receive sts-3 toh processor block is accumulating b2 byte errors in order to declare the sd defect condition. the user can implement this feature in order to configure the redundant receive sts-3 toh processor block to detect b2 bit errors in multiple ?sub-interval? periods before it will declare the sd defect condition.
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 303 table 202: redundant receive sts-3 transport ? receive sf burst error tolerance ? byte 1 (address location= 0x1756) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 sf_burst_tolerance[15:8] r/w r/w r/w r/w r/w r/w r/w r/w 1 1 1 1 1 1 1 1 b it n umber n ame t ype d escription 7 - 0 sf_burst_ tolerance [15:8] r/w sf_burst_tolerance ? msb: these read/write bits, along with t he contents of the ?redundant receive sts-3 transport ? sf burst tolerance ? byte 0? registers permit the user to specify the maximum number of b2 bit errors that the redundant receive sts-3 toh processor block can accumulate during a single sub-interval period (e.g., an sts-3 frame period), when determining whether or not to declare the sf (signal failure) defect condition. note: the purpose of this feature is to permit the user to provide some level of b2 byte error burst filtering, when the redundant receive sts-3 toh processor block is accumulating b2 byte errors in order to declare the sf defect condition. the user can implement this feature in order to configure the redundant receive sts-3 toh processor block to detect b2 bit errors in multiple ?sub-interval? periods before it will declare the sf defect condition. table 203: redundant receive sts-3 transport ? receive sf burst error tolerance ? byte 0 (address location= 0x1757) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 sf_burst_tolerance[7:0] r/w r/w r/w r/w r/w r/w r/w r/w 1 1 1 1 1 1 1 1 b it n umber n ame t ype d escription 7 - 0 sf_burst_ tolerance [7:0] r/w sf_burst_tolerance ? lsb: these read/write bits, along with t he contents of the ?redundant receive sts-3 transport ? sf burst tolerance ? byte 1? registers permit the user to specify the maximum number of b2 bit errors that the redundant receive sts-3 toh processor block can accumulate during a single sub-interval period (e.g., an sts-3 frame period), when determining whether or not to declare the sf (signal failure) defect condition. note: the purpose of this feature is to permit the user to provide some level of b2 byte error burst filtering, when the redundant receive sts-3 toh processor block is accumulating b2 byte errors in order to declare the sf defect condition. the user can implement this feature in order to configure the redundant receive sts-3 toh processor block to detect b2 bit errors in multiple ?sub-interval? periods before it will declare the sf defect condition. table 204: redundant receive sts-3 transport ? receive sd clear monitor interval ? byte 2 (address location= 0x1759)
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 304 b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 sd_clear_monitor_window[23:16] r/w r/w r/w r/w r/w r/w r/w r/w 1 1 1 1 1 1 1 1 b it n umber n ame t ype d escription 7 - 0 sd_clear_monitor_window[23: 16] r/w sd_clear_monitor_interval ? msb: these read/write bits, along the contents of the ?redundant receive sts-3 transport ? sd clear monitor interval ? byte 1 and byte 0? registers permit the user to specify the leng th of the ?monitoring period? (in terms of ms) for sd (signal degrade) defect clearance. when the redundant receive sts-3 toh processor block is checking the incoming sts-3 signal in order to determine if it should clear the sd defect condition, it will accumulate b2 byte errors throughout the user- specified ?sd defect clearance? monitoring period. if, during this ?sd defect clearance monitoring? period, the redundant receive sts-3 toh processor block accumulates less b2 byte errors than that programmed into the ?redundant receive sts-3 transport sd clear threshold? register, then the redundant receive sts-3 toh processor block will clear the sd defect condition. notes: 1. the value that the user writes into these three (3) ?sd clear monitor window? registers, specifies the duration of the ?sd defect clearance monitoring peri od? in terms of ms. 2. this particular register byte contains the ?msb? (most significant byte) value of the three registers that specify the ?sd defect clearance monitoring? period.
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 305 table 205: redundant receive sts-3 transport ? receive sd clear monitor interval ? byte 1 (address location= 0x175a) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 sd_clear_monitor_window[15:8] r/w r/w r/w r/w r/w r/w r/w r/w 1 1 1 1 1 1 1 1 b it n umber n ame t ype d escription 7 - 0 sd_clear_monitor_window[15:8] r/w sd_clear_monitor_interval ? bits 15 through 8: these read/write bits, along the contents of the ?redundant receive sts-3 transport ? sd clear monitor interval ? byte 2 and byte 0? registers permit the user to specify the le ngth of the ?monitoring period? (in terms of ms) for sd (signal degrade) defect clearance. when the redundant receive sts-3 toh processor block is checking the incoming sts-3 signal in order to determine if it should clear the sd defect condition, it will accumulate b2 byte errors throughout the user-specified ?sd defect clearance? monitoring period. if, during this ?sd defect clearance monitoring period? the redundant receive sts-3 toh processor block accumulates less b2 byte errors than that programmed into the ?redundant receive sts-3 transport sd clear threshold? register, then the redundant receive sts-3 toh processor block will clear the sd defect condition. note: the value that the us er writes into these three (3) ?sd clear monitor window? registers, specifies the duration of the ?sd defect clearance monitoring period?, in terms of ms.
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 306 table 206: redundant receive sts-3 transport ? receive sd clear monitor interval ? byte 0 (address location= 0x175b) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 sd_clear_monitor_window[7:0] r/w r/w r/w r/w r/w r/w r/w r/w 1 1 1 1 1 1 1 1 b it n umber n ame t ype d escription 7 - 0 sd_clear_monitor_window[ 7:0] r/w sd_clear_monitor_interval ? lsb: these read/write bits, along the contents of the ?redundant receive sts-3 transport ? sd clear monitor interval ? byte 2 and byte 1? registers permit the user to specify the length of the ?monitoring period? (in terms of ms) for sd (signal degrade) defect clearance. when the redundant receive sts-3 toh processor block is checking the incoming sts-3 signal in order to determine if it should clear the sd defect condition, it will accumulate b2 byte errors throughout the user-specified ?sd defect clearance? monitori ng period. if, during this ?sd defect clearance monitoring? period, the redundant receive sts-3 toh processor block accumulates less b2 byte errors than that programmed into the ?redundant receive sts-3 transport sd clear threshold? register, then the redundant receive sts-3 toh processor block will clear the sd defect condition. notes: 1. the value that the user writes into these three (3) ?sd clear monitor window? registers, specifies the duration of the ?s d defect clearance monitoring period?, in terms of ms. 2. this particular register byte contains the ?lsb? (least significant byte) value of the three registers that specify the ?sd defect clearance monitoring? period.
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 307 table 207: redundant receive sts-3 transport ? receive sf clear monitor interval ? byte 2 (address location= 0x175d) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 sf_clear_monitor_window[23:16] r/w r/w r/w r/w r/w r/w r/w r/w 1 1 1 1 1 1 1 1 b it n umber n ame t ype d escription 7 - 0 sf_clear_monitor_windo w [23:16] r/w sf_clear_monitor_interval ? msb: these read/write bits, along the contents of the ?redundant receive sts-3 transport ? sf clear monitor interval ? byte 1 and byte 0? registers permit the user to specify the length of the ?monitoring period? (in terms of ms) for sf (signal failure) defect clearance. when the redundant receive sts-3 toh processor block is checking the incoming sts-3 signal in order to determine if it should clear the sf defect condition, it will accumulate b2 byte errors throughout the user-specified ?sf defect clearance? monitoring period. if, during the ?sf defect clearance? monitoring period, the redundant receive sts- 3 toh processor block accumula tes less b2 byte errors than that programmed into the ?redundant receive sts-3 transport sf clear threshold? register, then the redundant receive sts-3 toh processor block will clear the sf defect condition. notes: 3. the value that the user writes into these three (3) ?sf clear monitor window registers?, specifies the duration of the ?sf defect clearance monitoring period?, in terms of ms. 4. this particular register byte contains the ?msb? (most significant byte) value fo the three registers that specify the ?sf defect clearance monitoring? period.
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 308 table 208: redundant receive sts-3 transport ? receive sf clear monitor interval ? byte 1 (address location= 0x175e) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 sf_clear_monitor_window[15:8] r/w r/w r/w r/w r/w r/w r/w r/w 1 1 1 1 1 1 1 1 b it n umber n ame t ype d escription 7 - 0 sf_clear_monitor_window [15:8] r/w sf_clear_monitor_interval ? bits 15 through 8: these read/write bits, along the contents of the ?redundant receive sts-3 transport ? sf clear monitor interval ? byte 2 and byte 0? registers permit the user to specify the length of the ?monitoring period? (in terms of ms) for sf (signal failure) defect clearance. when the redundant receive sts-3 toh processor block is checking the incoming sts-3 signal in order to determine if it should clear the sf defect condition, it will accumulate b2 byte errors throughout the user- specified ?sf defect clearance? monitoring period. if, during this ?sf defect clearance? monitoring period, the redundant receive sts-3 toh processor block accumulates less b2 byte errors than that programmed into the ?redundant receive sts-3 transport sf clear threshold? register, then the redundant receive sts- 3 toh processor block will clear the sf defect condition. notes: the value that the user writes into these three (3) ?sf clear monitor window? registers, specifies the duration of the ?sf defect clearance monitoring period?, in terms of ms.
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 309 table 209: redundant receive sts-3 transport ? receive sf clear monitor interval ? byte 0 (address location= 0x175f) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 sf_clear_monitor_window[7:0] r/w r/w r/w r/w r/w r/w r/w r/w 1 1 1 1 1 1 1 1 b it n umber n ame t ype d escription 7 - 0 sf_clear_monitor_window [7:0] r/w sf_clear_monitor_interval ? lsb: these read/write bits, along the contents of the ?redundant receive sts-3 transport ? sf clear monitor interval ? byte 2 and byte 1? registers permit the user to specify the length of the ?monitoring period? (in terms of ms) for sf (signal failure) defect clearance. when the redundant receive sts-3 toh processor block is checking the incoming sts-3 signal in order to determine if it should clear the sf defect condition, it will accumulate b2 byte errors throughout the user- specified ?sf defect clearance? monitoring period. if, during this ?sf defect clearance monitoring? period, the redundant receive sts-3 toh processor block accumulates less b2 byte errors than that programmed into the ?redundant receive sts-3 transport sf clear threshold? register, then the redundant receive sts- 3 toh processor block will clear the sf defect condition. notes: 3. the value that the user writes into these three (3) ?sf clear monitor window? registers, specifies the duration of the ?sf defect clearance monitoring? period, in terms of ms. 4. this particular register byte contains the ?lsb? (least significant byte) value of the three registers that specify the ?sf defect clearance monitoring? period.
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 310 table 210: redundant receive sts-3 transport ? serial port control register (address location= 0x1767) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 unused rxtoh_clock_speed[7:0] r/o r/o r/o r/o r/w r/w r/w r/w 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 - 4 unused r/o 3 - 0 rxtoh_clock_speed[7:0] r/w rxtohclk output clock signal speed: these read/write bit-fields permit the user to specify the frequency of the ?rxtohclk output clock signal. the formula that relates the contents of these register bits to the ?rxtohclk? frequency is presented below. freq = 19.44 /[2 * (rxtoh_clock_speed + 1) note: for sts-3/stm-1 applications, the frequency of the rxtohclk output signal mu st be in the range of 0.6075mhz to 9.72mhz
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 311 1.7 transmit sts-3 toh processor block the register map for the transmit sts-3 toh processor block is presented in the table below. additionally, a detailed description of each of the ?transmit sts- 3 toh processor? block registers is presented below. in order to provide some orientation for the reader, an illustration of the functional block diagram for the XRT94L33, with the ?transmit sts-3 toh processor block ?highlighted? is presented below in figure 4 figure 4: illustration of the function al block diagram of the XRT94L33 , with the transmit sts-3 toh processor block ?high-lighted?. ds3/e3 framer block ds3/e3 framer block rx sts-1 pointer justification block rx sts-1 pointer justification block rx sts-1 poh block rx sts-1 poh block tx sts-1 poh block tx sts-1 poh block tx sts-1 pointer justification block tx sts-1 pointer justification block tx sts-1 toh block tx sts-1 toh block rx sts-1 toh block rx sts-1 toh block ds3/e3 jitter attenuator block ds3/e3 jitter attenuator block ds3/e3 mapper block ds3/e3 mapper block tx sonet poh processor block tx sonet poh processor block tx sts-3 toh processor block tx sts-3 toh processor block sts-3 telecom bus block sts-3 telecom bus block tx/rx line i/f block (primary) tx/rx line i/f block (primary) tx/rx line i/f block (aps) tx/rx line i/f block (aps) clock synthesizer block clock synthesizer block channel 1 to channels 2 ? 3 microprocessor interface microprocessor interface jtag test port jtag test port rx sonet poh processor block rx sonet poh processor block rx sts-3 toh processor block rx sts-3 toh processor block from channels 2 ? 3 rx sts-3 toh processor block (primary) rx sts-3 toh processor block (primary)
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 312 transmit sts-3 toh processor block register table 211: transmit sts-3 toh processor block registers ? address map a ddress l ocation r egister n ame d efault v alues 0x1800 ? 0x1901 reserved 0x00 0x1902 transmit sts-3 transport ? sonet transmit control register ? byte 1 0x00 0x1903 transmit sts-3 transport ? sonet transmit control register ? byte 0 0x00 0x1904 ? 0x1915 reserved 0x00 0x1916 reserved 0x00 0x1917 transmit sts-3 transport ? transmit a1 byte error mask ? low register ? byte 0 0x00 0x1918 ? 0x191e reserved 0x00 0x191f transmit sts-3 transport ? transmit a2 byte error mask ? low register ? byte 0 0x00 0x1920 ? 0x1921 reserved 0x00 0x1923 transmit sts-3 transport ? b1 byte error mask register 0x00 0x1924 ? 0x1926 reserved 0x00 0x1927 transmit sts-3 transport ? transmit b2 byte error mask register ? byte 0 0x00 0x1928 ? 0x192a reserved 0x00 0x192b transmit sts-3 transport ? transmit b2 byte - bit error mask register ? byte 0 0x00 0x192c ? 0x192d reserved 0x00 0x192e transmit sts-3 transport ? k1k2 byte (aps) value register ? byte 1 0x00 0x192f transmit sts-3 transport ? k1k2 byte (aps) value register ? byte 0 0x00 0x1930 ? 0x1931 reserved 0x00 0x1933 transmit sts-3 transport ? rdi-l control register 0x00 0x1934 ? 0x1936 reserved 0x00 0x1937 transmit sts-3 transport ? m1 byte value register 0x00 0x1938 ? 0x193a reserved 0x00 0x193b transmit sts-3 transport ? s1 byte value register 0x00 0x193c ? 0x193e reserved 0x00 0x193f transmit sts-3 transport ? f1 byte value register 0x00 0x40 ? 0x42 0x1940 ? 0x1942 reserved 0x00 0x1943 transmit sts-3 transport ? e1 byte value register 0x00 0x1944 transmit sts-3 transport ? e2 byte control register 0x00 0x1945 reserved 0x00
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 313 a ddress l ocation r egister n ame d efault v alues 0x1946 transmit sts-3 transport ? e2 byte pointer register 0x00 0x1947 transmit sts-3 transport ? e2 byte value register 0x00 0x1948 ? 0x194a reserved 0x00 0x194b transmit sts-3 transport ? transmit j0 byte value register 0x00 0x194c ? 0x194e reserved 0x00 0x194f transmit sts-3 transport ? transmit j0 byte control register 0x00 0x1950 ? 0x1952 reserved 0x00 0x1953 transmit sts-3 transport ? serial port control register 0x00 0x1954 ?0x19ff reserved 0x00
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 314 1.7.1 transmit sts-3 toh processo r block register description table 212: transmit sts-3 transport ? sonet transm it control register ? byte 1 (address location= 0x1902) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 reserved sts-n overhead insert e2 byte insert method e1 byte insert method f1 byte insert method s1 byte insert method k1k2 byte insert method m1 byte insert method[1] r/o r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 unused r/o 6 sts-n overhead insert r/w sts-n overhead insert: this read/write bit-field permits the user to configure the txtoh input port to insert th e toh for all lower-tributary sts-1s within the outbound sts-3 signal. 0 ? disables this feature. in this mode, the txtoh input port will only accept the toh for the first sts-1 within the outbound sts-3 signal. 1 ? enables this feature. 5 e2 byte insert method r/w e2 byte insert method: this read/write bit-field permits the user to configure the transmit sts-3 toh processor block to use either the contents within the ?transmit sts-3 transport ? e2 byte value? register or the txtoh input port as the source for the e2 by te, within the outbound sts-3 data- stream, as described below. 0 ? configures the transmit sts-3 toh processor block to accept externally supplied data (via the ?txtoh serial input port) and to insert this data into the e2 byte positi on within each outbound sts-3 frame. 1 ? configures the transmit sts-3 toh processor block to insert the contents within the ?transmit sts-3 transport ? e2 byte value? register (address location = 0x1947) into the e2 byte-position, within each outbound sts-3 frame. this configur ation selection permits the user to have software control over the value of the e2 byte within the ?transmit output? sts-3 data-stream. 4 e1 byte insert method r/w e1 byte insert method: this read/write bit-field permits the user to configure the transmit sts-3 toh processor block to use either the contents within the ?transmit sts-3 transport ? e1 byte value? register or the txtoh input port as the source for the e1 byte, within the outbound sts-3 data- stream, as described below. 0 ? configures the transmit sts-3 toh processor block to accept externally supplied data (via the ?txtoh serial input port) and to insert this data into the e1 byte positi on within each outbound sts-3 frame. 1 ? configures the transmit sts-3 toh processor block to insert the contents within the ?transmit sts-3 transport ? e1 byte value? register (address location = 0x1943) into the e1 byte-position, within each outbound sts-3 frame. this configur ation selection permits the user to have software control over the value of the e1 byte within the ?transmit output? sts-3 data-stream.
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 315 3 f1 byte insert method r/w f1 byte insert method: this read/write bit-field permits the user to configure the transmit sts-3 toh processor block to use either the contents within the ?transmit sts-3 transport ? f1 byte value? register or the txtoh input port as the source for the f1 by te, within the outbound sts-3 data- stream, as described below. 0 ? configures the transmit sts-3 toh processor block to accept externally supplied data (via the ?txtoh? serial input port) and to insert this data into the f1 byte positi on within each outbound sts-3 frame. 1 ? configures the transmit sts-3 toh processor block to insert the contents within the ?transmit sts-3 transport ? f1 byte value? register (address location = 0x193f) into the f1 byte-position, within each outbound sts-3 frame. this configur ation selection permits the user to have software control over the value of the f1 byte within the ?transmit output? sts-3 data-stream. 2 s1 byte insert method r/w s1 byte insert method: this read/write bit-field permits the user to configure the transmit sts-3 toh processor block to use either the contents within the ?transmit sts-3 transport ? s1 byte value? register or the txtoh input port as the source for the e1 byte, within the outbound sts-3 data- stream, as described below. 0 ? configures the transmit sts-3 toh processor block to accept externally supplied data (via the ?txtoh? serial input port) and to insert this data into the s1 byte position within each outbound sts-3 frame. 1 ? configures the transmit sts-3 toh processor block to insert the contents within the ?transmit sts-3 transport ? s1 byte value? register (address location = 0x193b). this configuration selection permits the user to have software control over the value of the s1 byte within the ?transmit output? sts-3 data-stream. 1 k1k2 byte insert method r/w k1k2 byte insert method: this read/write bit-field permits the user to configure the transmit sts-3 toh processor block to use either the contents within the ?transmit sts-3 transport ? k1 byte value? and ?transmit sts-3 transport ? k2 byte value? register s or the ?txtoh input port as the source for the k1 and k2 bytes, wi thin the outbound sts-3 data-stream, as described below. 0 ? configures the transmit sts-3 toh processor block to accept externally supplied data (via the ?txtoh? serial input port) and to insert this data into the k1 and k2 byte positions within each outbound sts-3 frame. 1 ? configures the transmit sts-3 toh processor block to insert the contents within the ?transmit sts-3 tr ansport ? k1 byte value? register (address location = 0x192e) and the ?transmit sts-3 transport ? k2 byte value? register (address location = 0x192f) into the k1 and k2 byte-positions, within each outbound sts-3 frame. this configuration selection permits the user to have soft ware control over the value of the k1 and k2 bytes within the ?transmit output? sts-3 data-stream. 0 m1 byte insert method[1] r/w m1 byte insert method ? bit 1: this read/write bit-field, along with the ?m1 insert method[0]? bit-field (located in the ?transmit sts-3 tr ansport ? sonet control register ? byte 0?) permits the user to specify the source of the contents of the m1 byte, within the ?transmit? output sts-3 data stream. the relationship between these two bit-fields and the corresponding source of the m1 b y te ( within each outbound sts-3 frame ) is p resented
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 316 below. m1 byte insert method[1:0] source of m1 byte 0 0 functions as the rei-l indicator (based upon the number of b2 byte errors that have been detected by the receive sts-3 toh processor block) 0 1 the m1 byte value is obtained from the contents of the ?transmit sts-3 transport ? m1 byte value? regist er (address location = 0x1937). note: this configuration selection permits the user to exercise software control over the contents within the m1 byte, of each outbound sts-3 frame. 1 0 the m1 byte value is obtained from the ?txtoh? serial input port. 1 1 functions as the rei-l bit-field (based upon the number of b2 byte errors that have been detected by the receive sts-3 toh processor block).
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 317 table 213: transmit sts-3 transport ? sonet transm it control register ? byte 0 (address location= 0x1903) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 m1 byte insert method[0] unused force transmission of rdi-l force transmission of ais-l force tranmission of los patttern scrambler enable b2 byte error insert a1a2 byte error insert r/w r/o r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 m1 byte insert method[0] r/w m1 byte insert method ? bit 0: this read/write bit-field, along with the ?m1 insert method[1]? bit- field (located in the ?transmit sts-3 transport ? sonet control register ? byte 1?) permits the us er to specify the source of the contents of the m1 byte, within the ?transmit? output sts-3 data stream. the relationship between these two bit-fields and the corresponding source of the m1 byte (within each outbound sts-3 frame) is presented below. m1 insert method[1:0] source of m1 byte 0 0 functions as the rei-l indicator (based upon the number of b2 byte errors that have been detected by the receive sts-3 toh processor block) 0 1 the m1 byte value is obtained from the contents of the ?transmit sts-3 transport ? m1 byte value? register (address location= 0x1937). note: this configuration selection permits the user to exercise software control over the contents within the m1 byte of each outbound sts-3 frame. 1 0 the m1 byte value is obtained from the ?txtoh? serial input port. 1 1 functions as the rei-l bit-field (based upon the number of b2 byte errors that have been detected by the receive sts-3 toh processor block. 6 unused r/o 5 force transmission of rdi-l r/w force transmission of rdi-l (line - remote defect indicator): this read/write bit-field permits the user to (by software control) force the transmit sts-3 toh processor block to generate and transmit the rdi-l indicator to the remote terminal equipment as described below. 0 ? does not configure the transmit sts-3 toh processor block to generate and transmit the rdi-l indicato r. in this setting, the transmit sts-3 toh processor block will only generate and transmit the rdi-l indicator w henever the receive sts-3 toh processor block is
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 318 declaring a defect condition. 1 ? configures the transmit sts-3 toh processor block to generate and transmit the rdi-l indicator to the remote terminal equipment. in this case, the sts-3 transmitter will force bits 6, 7 and 8 (of the k2 byte) to the value ?1, 1, 0?. note: this bit-field is ignored if the transmit sts-3 toh processor block is transmitting the line ais (ais-l) indicator or the los pattern. 4 force transmission of ais-l r/w force transmission of ais-l (line ais) indicator: this read/write bit-field permits the user to (by software control) force the transmit sts-3 toh processor block to generate and transmit the ais-l indicator to the remote terminal equipment, as described below. 0 ? does not configure the transmit sts-3 toh processor block to generate and transmit the ais-l indicato r. in this case, the transmit sts-3 toh processor block will continue to transmit normal traffic to the remote terminal equipment. 1 ? configures the transmit sts-3 toh processor block to generate and transmit the ais-l indicator to the remote terminal equipment. in this case, the transmit sts-3 toh processor block will force all bits (within the ?outbound? sts-3 frame) with the exception of the section overhead bytes to an ?all ones? pattern. note: this bit-field is ignored if the transmit sts-3 toh processor block is transmitting the los pattern. 3 force transmission of los pattern r/w force transmission of los pattern: this read/write bit-field permits the user to (by software control) force the transmit sts-3 toh proc essor block to transmit the los (loss of signal) pattern to the remo te terminal equipment, as described below. 0 ? does not configure the transmit sts-3 toh processor block to generate and transmit the los pattern. in this case, the transmit sts- 3 toh processor block will continue to transmit ?normal? traffic to the remote terminal equipment. 1 ? configures the transmit sts-3 toh processor block to transmit the los pattern to the remote terminal equipment. in this case, the transmit sts-3 toh processor block will force all bytes (within the ?outbound? sonet frame) to an ?all zeros? pattern. 2 scrambler enable r/w scrambler enable: this read/write bit-field permits the user to either enable or disable the scrambler, within the transmit sts-3 toh processor block circuitry 0 ? disables the scrambler. 1 ? enables the scrambler. 1 b2 byte error insert r/w transmit b2 byte error insert enable: this read/write bit-field permits the user to configure the transmit sts-3 toh processor block to insert errors into the ?outbound? b2 bytes, per the contents within the ?transmit sts-3 transport ? transmit b2 byte error mask registers? as described below. 0 ? configures the transmit sts-3 toh processor block to not insert errors into the b2 bytes, within the outbound sts-3 signal. 1 ? configures the transmit sts-3 toh processor block to insert errors into the b2 b y tes (p er the contents within the ?transmit b2 b y te
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 319 error mask registers?). 0 a1a2 byte error insert r/w transmit a1a2 byte error insert enable: this read/write bit-field permits the user to configure the transmit sts-3 toh processor block to insert errors into the ?outbound? a1 and a2 bytes, per the contents within the ?transmit sts-3 transport ? transmit a1 byte error mask? and transmit a2 byte error mask? registers. 0 ? configures the transmit sts-3 toh processor block to not insert errors into the a1 and a2 bytes, within the outbound sts-3 data- stream. 1 ? configures the transmit sts-3 toh processor block to insert errors into the a1 and a2 bytes (per the contents within the ?transmit a1 byte error mask? and ?transmit a2 byte error mask? registers.
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 320 table 214: transmit sts-3 transport ? transmit a1 byte error mask ? low register ? byte 0 (address location= 0x1917) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 unused a1 byte error in sts-1 # 2 a1 byte error in sts-1 # 1 a1 byte error in sts-1 # 0 r/o r/o r/o r/o r/o r/w r/w r/w 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7-3 unused r/o 2 a1 byte error in sts-1 # 2 r/w a1 byte error in sts-1 # 2, within outbound sts-3 signal: this read/write bit-field permits the user to configure the transmit sts-3 toh processor block to transmi t an erred a1 byte, within sts-1 # 2 within the outbound sts-3 signal, as described below. 0 ? configures the transmit sts-3 toh processor block to not transmit an erred a1 byte, within sts-1 channel 2. 1 ? configures the transmit sts-3 toh processor block to transmit an erred a1 byte, within sts-1 channel 2. in this configuration setting, the state of each bit (within this particular a1 byte) will be inverted. hence all 8-bits within this particular a1 byte will be erred. note: this bit-field is only valid if bit 0 (a1a2 byte error insert), within the ?transmit sts-3 transport ? sonet transmit control register ? byte 0 (address location= 0x1903) to ?1?. 1 a1 byte error in sts-1 # 1 r/w a1 byte error in sts-1 # 1, within outbound sts-3 signal: this read/write bit-field permits the user to configure the transmit sts-3 toh processor block to transmi t an erred a1 byte, within sts-1 # 1 within the outbound sts-3 signal, as described below. 0 ? configures the transmit sts-3 toh processor block to not transmit an erred a1 byte, within sts-1 channel 1. 1 ? configures the transmit sts-3 toh processor block to transmit an erred a1 byte, within sts-1 channel 1. in this configuration setting, the state of each bit (within this particular a1 byte) will be inverted. hence all 8-bits within this particular a1 byte will be erred. note: this bit-field is only valid if bit 0 (a1a2 byte error insert), within the ?transmit sts-3 transport ? sonet transmit control register ? byte 0 (address location= 0x1903) to ?1?. 0 a1 byte error in sts-1 # 0 r/w a1 byte error in sts-1 # 0, within outbound sts-3 signal: this read/write bit-field permits the user to configure the transmit sts-3 toh processor block to transmi t an erred a1 byte, within sts-1 # 0 within the outbound sts-3 signal, as described below. 0 ? configures the transmit sts-3 toh processor block to not transmit an erred a1 byte, within sts-1 channel 0. 1 ? configures the transmit sts-3 toh processor block to transmit an erred a1 byte, within sts-1 channel 0. in this configuration setting, the state of each bit (within this particular a1 byte) will be inverted. hence, all 8-bits within this particular a1 byte will be erred. note: this bit-field is only valid if bit 0 (a1a2 byte error insert), within the ?transmit sts-3 transport ? sonet transmit control register ? byte 0 (address location= 0x1903) to ?1?.
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 321 table 215: transmit sts-3 transport ? transmit a2 byte error mask ? low register ? byte 0 (address location= 0x191f) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 unused a2 byte error in sts-1 # 2 a2 byte error in sts-1 # 1 a2 byte error in sts-1 # 0 r/o r/o r/o r/o r/o r/w r/w r/w 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7-3 unused r/o 2 a2 byte error in sts-1 # 2 r/w a2 byte error in sts-1 # 2, within outbound sts-3 signal: this read/write bit-field permits the user to configure the transmit sts-3 toh processor block to transmit an erred a2 byte, within sts-1 # 2 within the outbound sts-3 signal, as described below. 0 ? configures the transmit sts-3 toh processor block to not transmit an erred a2 byte, within sts-1 channel 2. 1 ? configures the transmit sts-3 toh processor block to transmit an erred a2 byte, within sts-1 channel 2. in th is configuration settti ng, the state of bit (within this particular a2 byte) will be inverted. hence all 8-bits within this particular a2 byte will be erred. note: this bit-field is only valid if bit 0 (a1a2 byte error insert), within the ?transmit sts-3 transport ? sonet transmit control register ? byte 0 (address location= 0x1903) to ?1?. 1 a2 byte error in sts-1 # 1 r/w a2 byte error in sts-1 # 1, within outbound sts-3 signal: this read/write bit-field permits the user to configure the transmit sts-3 toh processor block to transmit an erred a2 byte, within sts-1 # 1 within the outbound sts-3 signal, as described below. 0 ? configures the transmit sts-3 toh processor block to not transmit an erred a2 byte, within sts-1 channel 1. 1 ? configures the transmit sts-3 toh processor block to transmit an erred a2 byte, within sts-1 channel 1. in this configuration se tting, the state of each bit (within this particular a2 byte) will be inverted. hence all 8-bits within this particular a2 byte will be erred. note: this bit-field is only valid if bit 0 (a1a2 byte error insert), within the ?transmit sts-3 transport ? sonet transmit control register ? byte 0 (address location= 0x1903) to ?1?. 0 a2 byte error in sts-1 # 0 r/w a2 byte error in sts-1 # 0, within the outbound sts-3 signal: this read/write bit-field permits the user to configure the transmit sts-3 toh processor block to transmit an erred a2 byte, within sts-1 # 0 within the outbound sts-3 signal, as described below. 0 ? configures the transmit sts-3 toh processor block to not transmit an erred a2 byte, within sts-1 channel 0. 1 ? configures the transmit sts-3 toh processor block to transmit an erred a2 byte, within sts-1 channel 0. in this configuration se tting, the state of each bit (within this particular a2 byte) will be inverted. hence, all 8-bits within this particular a2 byte will be erred. note: this bi t - field is onl y valid if bit 0 ( a1a2 b y te error insert ) , within the
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 322 ?transmit sts-3 transport ? sonet transmit control register ? byte 0 (address location= 0x1903) to ?1?.
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 323 table 216: transmit sts-3 transport ? b1 byte error mask register (address location= 0x1923) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 b1_byte_error_mask[7:0] r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 ? 0 b1_byte_error_mask [7:0] r/w b1 byte error mask[7:0]: these read/write bit-fields permit the user to insert bit errors into the b1 bytes, within t he outbound sts-3 data stream. the transmit sts-3 toh processor block will perform an xor operation with the contents of t he b1 byte (within each outbound sts-3 frame), and the contents within this register. the results of this calculation will be inserted into the b1 byte position within the ?outbound? sts-3 dat a stream. for each bit-field (within this register) that is set to ?1?, the corresponding bit, within the b1 byte will be in error. note: for normal operation, the user should set this register to 0x00.
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 324 table 217: transmit sts-3 transport ? transmit b2 byte error mask register ? byte 0 (address location= 0x1927) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 unused b2 byte error in sts-1 channel 2 b2 byte error in sts-1 channel 1 b2 byte error in sts-1 channel 0 r/o r/o r/o r/o r/o r/w r/w r/w 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7-3 unused r/o 2 b2 byte error in sts-1 channel # 2 r/w b2 byte error in sts-1 channel # 2: this read/write bit-field permits the user to configure the transmit sts-3 toh processor block to transmit an erred b2 byte, within sts-1 channel 2. if the user enables this feature, t hen the transmit sts-3 toh processor block will perform an xor operation of the contents of the b2 byte (within sts-1 channel 2) and the contents of the ?transmit sts-3 transport ? transmit b2 bit error mask register ? byte 0 (address location= 0x192b). the results of this calculation will be written back into the ?b2 byte? position, within sts-1 channel 2, prior to transmission to the remote terminal. 0 ? configures the transmit sts-3 toh processor block to not insert errors into this particular b2 byte, within sts-1 channel 2. 1 ? configures the transmit sts-3 toh processor block to insert errors into the b2 byte, within sts-1 channel 2. note: this bit-field is only valid if bit 1 (b2 byte error insert), within the ?transmit sts-3 transport ? sonet transmit control register ? byte 0 (address = 0x1903) to ?1?. 1 b2 byte error in sts-1 channel # 1 r/w b2 byte error in sts-1 channel # 1: this read/write bit-field permits the user to configure the transmit sts-3 toh processor block to transmit an erred b2 byte, within sts-1 channel 1. if the user enables this feature, t hen the transmit sts-3 toh processor block will perform an xor operation of the contents of the b2 byte (within sts-1 channel 1) and the contents of the ?transmit sts-3 transport ? transmit b2 bit error mask register ? byte 0 (address location= 0x192b). the results of this calculation will be written back into the ?b2 byte? position, within sts-1 channel 1, prior to transmission to the remote terminal. 0 ? configures the transmit sts-3 toh processor block to not insert errors into this particular b2 byte, within sts-1 channel 1. 1 ? configures the transmit sts-3 toh processor block to insert errors into the b2 byte, within sts-1 channel 1. note: this bit-field is only valid if bit 1 (b2 byte error insert), within the ?transmit sts-3 transport ? sonet transmit control register ? byte 0 (address location= 0x1903) to ?1?. 0 b2 byte error in sts - 1 channel # 0 r/w b2 byte error in sts-1 channel # 0:
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 325 sts-1 channel # 0 this read/write bit-field permits the user to configure the transmit sts-3 toh processor block to transmit an erred b2 byte, within sts-1 channel 0. if the user enables this feature, t hen the transmit sts-3 toh processor block will perform an xor operation of the contents of the b2 byte (within sts-1 channel 0) and the contents of the ?transmit sts-3 transport ? transmit b2 bit error mask register ? byte 0 (address location= 0x192b). the results of this calculation will be written back into the ?b2 byte? position, within sts-1 channel 0, prior to transmission to the remote terminal. 0 ? configures the transmit sts-3 toh processor block to not insert errors into the b2 byte, within sts-1 channel 0. 1 ? configures the transmit sts-3 toh processor block to insert errors into this particular b2 byte , within sts-1 channel 0. note: this bit-field is only valid if bit 1 (b2 byte error insert), within the ?transmit sts-3 transport ? sonet transmit control register ? byte 0 (address location= 0x1903) to ?1?.
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 326 table 218: transmit sts-3 transport ? transmit b2 bit error mask register ? byte 0 (address location= 0x192b) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 transmit_b2_error_mask[7:0] r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 ? 0 transmit_b2_error_mask[7:0] r/w transmit b2 error mask byte: these read/write bit-fields permit the user to specify exact which bits, within the ?selected? b2 byte (within the outbound sts-3 signal) will be erred. if the user configures the transmit sts-3 toh processor block to transmit one or more erred b2 bytes, then the transmit sts-3 toh processor block will perform an xor operation of the contents of the b2 byte (withi n the ?selected? sts-1 channel) and the contents of this register. the results of this calculation will be written back into the ?b2 byte? position within the ?selected? sts-1 channel, (within the outbound sts-3 signal) prior to transmission to the remote terminal. the user can select which sts-1 channels (within the outbound sts-3 signal) will contain the ?erred? b2 byte, by writing the appropriate data into the ?transmit sts-3 transport ? transmit b2 byte error mask register ? bytes 1 and 0 (address location= 0x1927). note: this bit-field is only valid if bit 1 (b2 error insert), within the ?transmit sts-3 transport ? sonet transmit control register ? byte 0 (address location= 0x1903) to ?1?.
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 327 table 219: transmit sts-3 transport ? k1k2 (aps) value register ? byte 1 (address location= 0x192e) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 transmit_k2_byte_value[7:0] r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 ? 0 transmit_k2_byte_value[7:0] r/w transmit k2 byte value: if the user has configured the transmit sts-3 toh processor block to use the contents of the ?transmit k2 byte value? register as the source for the k2 byte value (within the outbound sts-3 data- stream), then these read/write bit- fields will permit the user to specify the contents of the k2 byte, within the ?outbound? sts-3 signal. if bit 1 (k1k2 byte insert method) within the transmit sts-3 transport ? sonet transmit control register ? byte 1 (address location= 0x1902) is set to ?1?, then the transmit sts-3 toh processor block will load the contents of this register into the ?k2? byte-field, within each outbound sts-3 frame. note: these register bits are ignored if bit 1 (k1k2 insert method) is set to ?0?.
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 328 table 220: transmit sts-3 transport ? k1k2 (aps) value register ? byte 0 (address location= 0x192f) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 transmit_k1_byte_value[7:0] r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 ? 0 transmit_k1_byte_value[7:0] r/w transmit k1 byte value: if the user has configured the transmit sts-3 toh processor block to use the contents of the ?transmit k1 byte value? register as the source for the k1 byte value (within the outbound sts-3 data-stream), then these read/write bit-fields will permit the user to specify the contents of the k1 byte, within the ?outbound? sts-3 signal. if bit 1 (k1k2 byte insert method) within the transmit sts-3 transport ? sonet transmit control register ? byte 1 (address location= 0x1902) is set to ?1?, then the transmit sts-3 toh processor block will load the content s of this register into the ?k1? byte-field, within each outbound sts-3 frame. note: these register bits are ignored if bit 1 (k1k2 insert method) is set to ?0?.
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 329 table 221: transmit sts-3 transport ? rdi-l control register (address location= 0x1933) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 unused external rdi-l enable transmit rdi-l upon ais-l transmit rdi-l upon lof transmit rdi-l upon los r/o r/o r/o r/o r/w r/w r/w r/w 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 ? 4 unused r/o 3 external rdi-l enable r/w external rdi-l insertion enable: this read/write bit-field permits the user to configure the transmit sts-3 toh processor to accept data via the ?txtoh? input pin, when transmitting the rdi-l indicator to the remote terminal equipment. 0 ? configures the transmit sts-3 toh processor block to internally generate the rdi-l indicator based upon defect conditions that are being declared by the receive sts-3 toh processor block. 1 ? configure the transmit sts-3 toh processor block accept external data via the ?txtoh? input port and to load this value into bits 6, 7 and 8 (within the k2 byte) within each outbound sts-3 data-stream. 2 transmit rdi-l upon ais-l r/w transmit line remote defe ct indicator (rdi-l) upon declaration of the ais-l defect condition: this read/write bit-field permits the user to configure the transmit sts-3 toh processor block to automatically transmit the rdi-l indicator to the remote lte anytime (and for the duration) that the receive sts- 3 toh processor is declaring the line ais (ais-l) defect condition as described below. 0 ? configures the transmit sts-3 toh processor block to not automatically transmit the rdi-l indicator, whenever (and for the duration that) the receive st s-3 toh processor block is declares the ais-l defect condition. 1 ? configures the transmit sts-3 toh processor block to automatically transmit the rdi-l indicator, whenever (and for the duration that) the receive sts-3 toh processor block declares the ais-l defect condition. 1 transmit rdi-l upon lof r/w transmit line remote defe ct indicator (rdi-l) upon declaration of the lof defect condition: this read/write bit-field permits the user to configure the transmit sts-3 toh processor block to automatically transmit the rdi-l indicator to the remote lte anytime (and for the duration) that the receive sts-3 toh processor block is declaring the lof defect condition as described below. 0 ? configures the transmit sts-3 toh processor to not automatically transmit the rdi-l indicator, whenever the receive sts-3 toh processor block declares the lof defect condition. 1 ? configures the transmit sts-3 toh processor block to automatically transmit the rdi-l indicator, whenever (and for the duration that ) the receive sts-3 toh processor block declares
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 330 the lof defect condition. 0 transmit rdi-l upon los r/w transmit line remote defe ct indicator (rdi-l) upon declaration of the los defect condition: this read/write bit-field permits the user to configure the transmit sts-3 toh processor block to automatically transmit the rdi-l indicator to the remote lte anytime (and for the duration) that the receive sts-3 toh processor block declares the los defect condition. 0 ? configures the transmit sts-3 toh processor block to not automatically transmit the rdi-l indicator, whenever the receive sts-3 toh processor block declares the los defect condition. 1 ? configures the transmit sts-3 toh processor block to automatically transmit the rdi-l indicator, whenever (and for the duration that) the receive sts-3 toh processor block declares the los defect condition.
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 331 table 222: transmit sts-3 transport ? m1 byte value register (address location= 0x1937) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 transmit_m1_byte_value[7:0] r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 ? 0 transmit_m1_byte_value [7:0] r/w transmit m1 byte value: if the appropriate ?m1 byte insert method? is selected, then these read/write bit-fields will permit the user to specify the contents of the m1 byte, within the ?outbound? sts-3 signal. if bit 0 (m1 byte insert method ? bit 1) within the transmit sts-3 transport ? sonet transmit control register ? byte 1 (address location= 0x1902) and bit 7 (m1 byte insert method ? bit 0) within the transmit sts-3 transport ? sonet transmit control register ? byte 0 (address location = 0x1903) is set to ?[0, 1]?, then the transmit sts-3 toh processor block will load the contents of this register into the ?m1? byte-field, within each outbound sts-3 frame. note: these register bits are ignored if the m1 byte insert method[1:0] bits are set to any value other than ?[0, 1]?. table 223: transmit sts-3 transport ? s1 byte value register (address location= 0x193b) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 transmit_s1_byte_value[7:0] r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 ? 0 transmit_s1_byte_value[7:0] r/w transmit s1 byte value: if the appropriate ?s1 insert me thod? is selected, then these read/write bit-fields will permit the user to specify the contents of the s1 byte, within the ?outbound? sts-3 signal. if bit 2 (s1 byte insert method) within the transmit sts-3 transport ? sonet transmit control register ? byte 1 (address location= 0x1902) is set to ?1?, then the transmit sts-3 toh processor block will load the content s of this register into the ?s1? byte-field, within each outbound sts-3 frame. note: these register bits are ignored if bit 2 (s1 byte insert method) is set to ?0?.
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 332 table 224: transmit sts-3 transport ? f1 byte value register (address location= 0x193f) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 transmit_f1_byte_value[7:0] r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 ? 0 transmit_f1_byte_value[7:0] r/w transmit f1 byte value : if the appropriate ?f1 byte insert method? is selected, then these read/write bit-fields will permit the user to specify the contents of the f1 byte, within the ?outbound? sts-3 signal. if bit 3 (f1 byte insert method) within the transmit sts-3 transport ? sonet transmit control register ? byte 1 (address location= 0x1902) is set to ?1?, then the transmit sts-3 toh processor block will load the contents of this register into the ?f1? byte-field, within each outbound sts-3 frame. note: these register bits are ignored if bit 3 (f1 byte insert method) is set to ?0?. table 225: transmit sts-3 transport ? e1 byte value register (address location= 0x1943) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 transmit_e1_byte_value[7:0] r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 ? 0 transmit_e1_byte_value[7:0] r/w transmit e1 byte value: if the appropriate ?e1 byte insert method? is selected, then these read/write bit-fields will permit the user to specify the contents of the e1 byte, within the ?outbound? sts-3 signal. if bit 4 (e1 byte insert method) within the transmit sts-3 transport ? sonet transmit control register ? byte 1 (address location= 0x1902) is set to ?1?, then the transmit sts-3 toh processor block will load the contents of this register into the ?e1? byte-field, within each outbound sts-3 frame. note: these register bits are ignored if bit 4 (e1 byte insert method) is set to ?0?.
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 333 table 226: transmit sts-3 transport ? e2 byte control register (address location= 0x1944) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 enable all sts-1s unused r/w r/o r/o r/o r/o r/o r/o r/o 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 enable all sts-1s r/w enable all sts-1s: this read/write bit-field permits the user to implement either of the following configurations options for soft ware control of the e2 byte value, within the outbound sts-3 signal. 0 ? configures the transmit sts-3 toh processor block to read out the contents of the ?transmit sts-3 transpor t ? e2 byte value? register and load that value into the e2 byte (w ithin sts-1 # 1) within the outbound sts-3 signal. 1 ? configures the transmit sts-3 toh processor block to read out the contents of the 3 ?shadow? registers, an d to load these values into the e2 byte positions, within each corresponding sts-1 signal; within the outbound sts-3 signal. note: this register bit is ignored if bit 5 (e2 byte insert method) within the ?transmit sts-3 transport ? sonet transmit control register ? byte 1? (address location= 0x1902) is set to ?0?. 6 - 0 unused r/o
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 334 table 227: transmit sts-3 transport ? e2 pointer register (address location= 0x1946) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 unused e2_pointer[1:0] r/o r/o r/o r/o r/w r/w r/w r/w 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 ? 2 unused r/o 1 - 0 e2_pointer[1:0] r/w e2 pointer[3:0]: these read/write bit-fields permit the user to uniquely identify one of the 3 sts-1 e2 byte ?shadow? registers, when performing read or write operations to these registers. if the user has set bit 7 (enable all sts-1s), within this register to ?1?, then the contents of these four register bits, act as a pointer to a given ?shadow? register. once the user specifies this pointer value; then he/she completes the read or write operation (to or from the ?shadow? register) by performing a read or write to the ?transmit sts-3 transport ? e2 byte value? register (address location= 0x1947). valid ?shadow? pointer values range from ?0x00? to ?0x02? (where the pointer value of ?0x00? corresponds to the e2 ?shadow? register, corresponding to sts-1 # 1; and so on). note: this register bit is ignored if bit 7 (enable all sts-1s) is set to ?1?; or if bit 5 (e2 byte insert method) within the ?transmit sts- 3 transport ? sonet transmit control register ? byte 1? (address location= 0x1902) is set to ?0?.
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 335 table 228: transmit sts-3 transport ? e2 byte value register (address location=0x1947) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 transmit_e2_byte_value[7:0] r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 ? 0 transmit_e2_byte_value[7:0] r/w transmit e2 byte value: the exact function of these register bits depends upon whether bit 7 (enable all sts-1s) within the ?transmit sts-3 transport ? e2 byte control? register (address location= 0x1944) has been set to ?0? or ?1?; as described below. if ?enable all sts-1s? is set to ?0? if the appropriate ?e2 insert me thod? is selected, then these read/write bit-fields will permit the user to specify the contents of the e2 byte, within the ?outbound? sts-3 signal. more specifically, this value will be loaded into the e2 byte position, within sts-1 # 1 (wit hin the outbound sts-3 signal). if bit 5 (e2 insert method) within the transmit sts-3 transport ? sonet transmit control register ? byte 1 (address location= 0x1902) is set to ?1?, then the transmit sts-3 toh processor block will load the contents of this register into the ?e2? byte-field, within each outbound sts-3 frame. if ?enable all sts-1s? is set to ?1? in this mode, these register bi t permit the user to have direct read/write access of the ?sts-1 e2 byte shadow? register; that is being pointed at by the ?e2 pointer[1:0]? value. these register bits are ignored if bit 5 (e2 byte insert method) is set to ?0?.
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 336 table 229: transmit sts-3 transport ? j0 byte value register (address location= 0x194b) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 transmit_j0_byte_value[7:0] r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 ? 0 transmit_j0_value[7:0] r/w transmit j0 byte value[7:0]: if the user has configured the transmit sts-3 toh processor block to use the ?transmit j0 byte value? register as the ?source? of the ?outbound? section trace message, then these read/write bits will permit the user to specify the contents within the j0 byte of each outbound sts-3 frame. note: this register is only valid if the transmit sts-3 toh processor block is configur ed to read out the contents from this register and insert it into the j0 byte-field within each outbound sts-3 frame. the user accomplishes this by setting the ?transmit section trace message source[1:0]? bit-fields (within the transmit sts-3 transport ? transmit section trace message control register ? address = 0x194f) to ?1, 0?..
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 337 table 230: transmit sts-3 transport ? transmit section trace message control register (address location= 0x194f) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 unused transmit section trace messsage l ength[1:0] transmit section trace message source[1:0] r/o r/o r/o r/o r/w r/w r/w r/w 0 0 0 0 1 1 0 0 b it n umber n ame t ype d escription 7 ? 4 unused r/o 3 ? 2 transmit section trace message length[1:0] r/w transmit section trace message length[1:0]: these two read/write bit-fields permit the user to specify the length of the section trace message that t he transmit sts-3 toh processor block will repeatedly transmit to the remote lte. the relationship between the contents of these bit-fields and the corresponding transmit section trace message length is presented below. transmit section trace message length[1:0] resulting section trace message length (in terms of bytes) 00 1 byte 01 16 bytes 10 or 11 64 bytes 1 ? 0 transmit section trace message source[1:0] r/w transmit section trace message source[1:0]: these two read/write bit-fields permit the user to specify the source of the ?outbound? section trace message that will be transported via the j0 byte channel within the out bound sts-3 data-stream, as depicted below. transmit section trace message source[1:0] resulting source of the section trace message. 00 fixed value: the transmit sts-3 toh processor block will automatically set the j0 byte, in each ?outbound? sts-3 frame to the value ?0x01?. 01 the ?transmit section trace message buffer?. the transmit sts-3 toh processor block will read out the contents within the transmit section trace message buffer, and will transmit this message to the remote lte. the ?transmit sts-3 toh processor block - transmit section trace message buffer? memory is located at address location 0x1b00 through 0x1b3f. 10 from the ?transmit j0 value[7:0]? register.
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 338 11 from the ?txtoh? input pin (pin f8). in this configuration setting, the transmit sts-3 toh processor block will externally accept the contents of the ?section trace message? via the ?txtoh input port? and it will transport this message (via the j0 byte -channel) to the remote lte. table 231: transmit sts-3 transport ? serial port control register (address location= 0x1953) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 unused txtoh_clock_speed[7:0] r/o r/o r/o r/o r/w r/w r/w r/w 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 - 4 unused r/o 3 - 0 txtoh_clock_speed[7:0] r/w txtohclk output clock signal speed: these read/write bit-fields permits the user to specify the frequency of the ?txtohclk output clock signal. the formula that relates the contents of these register bits to the ?txtohclk? frequency is presented below. freq = 19.44 /[2 * (txtoh_clock_speed + 1) note: for sts-3/stm-1 applications, the frequency of the txtohclk output signal mu st be in the range of 0.6075mhz to 9.72mhz
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 339 1.8 transmit sts-3c poh processor block registers the register map for the transmit sts-3c poh proc essor block is presented in the table below. additionally, a detailed description of each of the ?t ransmit sts-3c poh processor? block registers is presented below. in order to provide some orientation for the reader, an illustration of the functional block diagram for the XRT94L33, with the ?transmit sts-3c poh processor block ?highlighted? is presented below in figure 5. figure 5: illustration of the function al block diagram of the XRT94L33 , with the transmit sts-3c poh processor block ?high-lighted?. receive sts-1 toh processor block receive sts-1 toh processor block receive sts-1 poh processor block receive sts-1 poh processor block transmit sts-1 poh processor block transmit sts-1 poh processor block transmit sts-1 toh processor block transmit sts-1 toh processor block receive sonet poh processor block receive sonet poh processor block transmit sonet poh processor block transmit sonet poh processor block transmit sts-3 toh processor block transmit sts-3 toh processor block receive sts-3 toh processor block receive sts-3 toh processor block transmit sts-1 telecom bus interface block transmit sts-1 telecom bus interface block receive sts-1 telecom bus interface block receive sts-1 telecom bus interface block receive sts-3 telecom bus interface block receive sts-3 telecom bus interface block transmit sts-3 telecom bus interface block transmit sts-3 telecom bus interface block clock synthesizer block clock synthesizer block clock & data recovery block clock & data recovery block transmit sts-3 pecl interface block transmit sts-3 pecl interface block receive sts-3 pecl interface block receive sts-3 pecl interface block to channels 1 & 2 from channels 1 & 2 channel 0 ds3/e3 framer block ds3/e3 framer block ds3/e3 jitter attenuator block ds3/e3 jitter attenuator block ds3/e3 mapper block ds3/e3 mapper block
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 340 1.8.1 transmit sts-3 c poh processor block registers table 232: transmit sts-3c poh processor block - register address map a ddress l ocation r egister n ame d efault v alues 0x1900 ? 0x1981 reserved 0x00 0x1982 transmit sts-3c path ? sonet control register ? byte 1 0x00 0x1983 transmit sts-3c path ? sonet control register ? byte 0 0x00 0x1984 ? 0x1992 reserved 0x00 0x1993 transmit sts-3c path ? transmit j1 byte value register 0x00 0x1994 ? 0x1996 reserved 0x00 0x1997 transmit sts-3c path ? b3 byte mask register 0x00 0x1998 ? 0x199a reserved 0x00 0x199b transmit sts-3c path ? transmit c2 byte value register 0x00 0x199c ? 0x199e reserved 0x00 0x199f transmit sts-3c path ? transmit g1 byte value register 0x00 0x19a0 ? 0x19a2 reserved 0x00 0x19a3 transmit sts-3c path ? transmit f2 byte value register 0x00 0x19a4 ? 0x19a6 reserved 0x00 0x19a7 transmit sts-3c path ? transmit h4 byte value register 0x00 0x19a8 ? 0x19aa reserved 0x00 0x19ab transmit sts-3c path ? transmit z3 byte value register 0x00 0x19ac ? 0x19ae reserved 0x00 0x19af transmit sts-3c path ? transmit z4 byte value register 0x00 0x19b0 ? 0x19b2 reserved 0x00 0x19b3 transmit sts-3c path ? transmit z5 byte value register 0x00 0x19b4 ? 0x19b6 reserved 0x00 0x19b7 transmit sts-3c path ? transmit path control register ? byte 0 0x00 0x19b8 ? 0x19ba reserved 0x00 0x19bb transmit sts-3c path ? transmit j1 control register 0x00 0x19bc ? 0x19be reserved 0x00 0x19bf transmit sts-3c path ? transmit arbitrary h1 byte pointer register 0x94 0x19c0 ? 0x19c2 reserved 0x00 0x19c3 transmit sts-3c path ? transmit arbitrary h2 byte pointer register 0x00 0x19c4 ? 0x19c5 reserved 0x00
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 341 a ddress l ocation r egister n ame d efault v alues 0x19c6 transmit sts-3c path ? transmit po inter byte register ? byte 1 0x02 0x19c7 transmit sts-3c path ? transmit po inter byte register ? byte 0 0x0a 0x19c8 reserved 0x00 0x19c9 transmit sts-3c path ? rdi-p control register ? byte 2 0x40 0x19ca transmit sts-3c path ? rdi-p control register ? byte 1 0xc0 0x19cb transmit sts-3c path ? rdi-p control register ? byte 0 0xa0 0x19cc ? 0x19ce reserved 0x00 0x19cf transmit sts-3c path ? transmit path serial port control register 0x00 0x19d0 ? 0x19ff reserved 0x00
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 342 1.8.2 transmit sts-3 c poh processor block register description table 233: transmit sts-3c path ? sonet control register ? byte 1 (address location= 0x1982) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 unused z5 byte insertion type z4 byte insertion type z3 byte insertion type h4 byte insertion type r/w r/o r/o r/o r/w r/w r/w r/w 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 ? 4 unused r/o 3 z5 byte insertion type r/w z5 byte insertion type: this read/write bit-field permits the user to configure the transmit sts- 3c poh processor block to use either the contents within the ?transmit sts-3c path ? transmit z5 byte value? register or the tpoh input pin as the source for the z5 byte, in the outbound sts-3c spe data-stream, as described below. 0 ? configures the transmit sts-3c poh processor block to insert the contents within the ?transmit sts-3c path ? transmit z5 byte value? register into the z5 byte position within ea ch outbound sts-3c spe. 1 ? configures the transmit sts-3c poh processor block to accept externally supplied data (via the ?tpoh? input port) and to insert this data into the z5 byte position within each outbound sts-3c spe. note: the address location of the tr ansmit sts-3c poh processor block - transmit z5 byte value register is 0x19b3 2 z4 byte insertion type r/w z4 byte insertion type: this read/write bit-field permits the user to configure the transmit sts- 3c poh processor block to use either the contents within the ?transmit sts-3c path ? transmit z4 byte value? register or the txpoh input pin as the source for the z4 byte, in the outbound sts-3c spe data-stream, as described below. 0 ? configures the transmit sts-3c poh processor block to insert the contents within the ?transmit sts-3c path ? transmit z4 byte value? register into the z4 byte position within ea ch outbound sts-3c spe. 1 ? configures the transmit sts-3c poh processor block to accept externally supplied data (via the ?txpoh? input port) and to insert this data into the z4 byte position within each outbound sts-3c spe. note: the address location of the transmit sts-3c poh processor block -transmit z4 byte value register is 0x19af 1 z3 byte insertion type r/w z3 byte insertion type: this read/write bit-field permits the user to configure the transmit sts- 3c poh processor block to use either the contents within the ?transmit sts-3c path ? transmit z3 byte value? register or the txpoh input pin as the source for the z3 byte, in the outbound sts-3c spe data-stream, as described below. 0 ? configures the transmit sts-3c poh processor block to insert the contents within the ?transmit sts-3c path ? transmit z3 byte value? register into the z3 byte position within ea ch outbound sts-3c spe. 1 ? confi g ures the transmit sts-3c poh processor block to acce p t
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 343 externally supplied data (via the ?txpoh? input port) and to insert this data into the z3 byte position within each outbound sts-3c spe. note: the address location of the tr ansmit sts-3c poh processor block - transmit z3 byte value register is 0x19ab 0 h4 byte insertion type r/w h4 byte insertion type: this read/write bit-field permits the user to configure the transmit sts- 3c poh processor block to use either the contents within the ?transmit sts-3c path ? transmit h4 byte value? register or the txpoh input pin as the source for the h4 byte, in t he outbound sts-3c spe data-stream, as described below. 0 ? configures the transmit sts-3c poh processor block to insert the contents within the ?transmit sts-3c path ? transmit h4 byte value? register into the h4 byte positi on within each outbound sts-3c spe. 1 ? configures the transmit sts-3c poh processor block to accept externally supplied data (via the ?tpoh? input port) and to insert this data into the h4 byte position within each outbound sts-3c spe. note: the address location of the tr ansmit sts-3c poh processor block -transmit h4 byte value register is 0x19a7
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 344 table 234: transmit sts-3c path ? sonet control register ? byte 0 (address location= 0x1983) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 f2 byte insertion type rei-p insertion type[1:0] rdi-p insertion type[1:0] c2 byte insertion type unused force transmission of ais-p r/w r/w r/w r/w r/w r/w r/o r/w 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 f2 byte insertion type r/w f2 byte insertion type: this read/write bit-field permits the user to configure the transmit sts-3c poh processor block to use either the contents within the ?transmit sts-3c path ? transmit f2 byte value? register or the txpoh input pin as the source for the f2 byte, in the outbound sts- 3c spe data-stream, as described below. 0 ? configures the transmit sts-3c poh processor block to insert the contents within the ?transmit sts-3c path ? transmit f2 byte value? register into the f2 byte position within each outbound sts-3c spe. 1 ? configures the transmit sts-3c poh processor block to accept externally supplied data (via the ?tpoh? input port) and to insert this data into the f2 byte position within each outbound sts-3c spe. note: the address location of the transmit sts-3c poh processor block - transmit f2 byte value register is 0x19a3 6 - 5 rei-p insertion type[1:0] r/w rei-p insertion type[1:0]: these two read/write bit-fields permit the user to configure the transmit sts-3c poh processor block to use one of the three following sources for the rei-p bit-fields (e.g., bits 1 through 4, within the g1 byte) within each outbound sts-3c spe. ? from the receive sts-3c poh processor block (e.g., the transmit sts-3c poh processor block will set the rei-p bit-fields to the appropriate value, based upon the number of b3 byte errors that the receive sts-3c poh processor block detects and flags, within its incoming sts-3c spe data- stream). ? from the ?transmit g1 byte value? register. in this case, the transmit sts- 3c poh processor block will insert the contents of bits 7 through 4 within the ?transmit sts-3c poh processor block ? transmit g1 byte value? register into the rei-p bit-fields within each outbound sts-3c spe. ? from the ?tpoh? input pin. in this case, the transmit sts-3c poh processor block will accept externally s upplied data (via the ?tpoh? input port) and it will insert this data into the rei- p bit-fields within each outbound sts-3c spe. 00/11 ? configures the transmit sts-3c poh processor block to set bits 1 through 4 (in the g1 byte of the outbound spe) based upon the number of b3 byte errors that the receive sts-3c poh processor block detects and flags within the incoming sts-3c data-stream. 01 ? configures the transmit sts-3c poh processor block to set bits 1 through 4 (in the g1 byte of the outbo und spe) based upon the contents within the ?transmit sts-3c poh processor block - transmit g1 byte value? register. 10 ? configures the transmit sts-3c poh processor block to accept externally supplied data (via the tpoh input port) and to insert this data into the rei-p bit- positions within each outbound sts-3c spe. note: the address location of the transmit sts - 3c poh processor block -
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 345 transmit g1 byte value register is 0x199f 4 - 3 rdi-p insertion type[1:0] r/w rdi-p insertion type[1:0]: these two read/write bit-fields permit the user to configure the transmit sts-3c poh processor block to use one of the three following sources for the rdi-p bit-fields (e.g., bits 5 through 7, within the g1 byte) within each outbound sts-3c spe. ? from the corresponding receive sts-3c poh processor block (e g., the transmit sts-3c poh processor block will set the rdi-p bit-fields to the appropriate value, based upon which defect conditions are being declared by the receive sts-3c poh processor blo ck, within its incoming sts-3c spe data-stream). ? from the ?transmit g1 byte value? register. in this case, the transmit sts- 3c poh processor blolck will insert the content of bits 2 through 0 within the ?transmit sts-3c poh processor block ? transmit g1 byte value? register into the rdi-p bit-fields within each outbound sts-3c spe. ? from the ?tpoh? input pin. in this case, the transmit sts-3c poh processor block will accept externally s upplied data (via the ?tpoh? input port) and it will insert this data into the rdi-p bit-fields within each outbound sts-3c spe. 00/11 ? configures the transmit sts-3c poh processor block to set bits 5 through 7 (in the g1 byte of the outbound spe) based upon the defects conditions that the receiv e sts-3c poh processor block is currently declaring within the incoming sts-3c data-stream. 01 ? configures the transmit sts-3c poh processor block to set bits 5 through 7 (in the g1 byte of the outbo und spe) based upon the contents within the ?transmit sts-3c poh processor block - transmit g1 byte value? register. 10 ? configures the transmit sts-3c poh processor block to accept externally supplied data (via the tpoh input port) and to insert this data into the rdi-p bit- positions within each outbound sts-3c spe. note: the address location of the transmit sts-3c poh processor block - transmit g1 byte value register is 0x199f 2 c2 byte insertion type r/w c2 byte insertion type: this read/write bit-field permits the user to configure the transmit sts-3c poh processor block to use either the contents within the ?transmit sts-3c path ? transmit c2 byte value? register or the tpoh input pin as the source for the c2 byte, in the outbound sts-3c spe data-stream, as described below. 0 ? configures the transmit sts-3c poh processor block to insert the contents within the ?transmit sts-3c path ? transmit c2 byte value? register into the c2 byte-position within each outbound sts-3c spe. 1 ? configures the transmit sts-3c poh processor block to accept externally supplied data (via the ?tpoh? input port) and to insert this data into the c2 byte position within each outbound sts-3c spe. note: the address location of the transmit sts-3c poh processor block - transmit c2 byte value register is 0x199b 1 unused r/o 0 force transmission of ais-p r/w force transmission of ais-p: this read/write bit-field permits the user to configure the transmit sts-3c poh processor block to (via software co ntrol) transmit the ais-p indicator to the remote pte. if this feature is enabled, then the tr ansmit sts-3c poh processor block will automatically set the h1, h2, h3 and all the ?outbound? sts-3c spe bytes to an ?all ones? p attern, p rior to routin g this data to the transmit sts-3 toh
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 346 processor block. 0 ? configures the transmit sts-3c po h processor block to not transmit the ais-p indicator to the remote pte. in this case, the transmit sts-3c poh processor block will transmit ?norma l? traffic to the remote pte. 1 ? configures the transmit sts-3c poh processor block to transmit the ais-p indicator to th e remote pte.
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 347 table 235: transmit sts-3c path ? transmitter j1 byte value register (address location= 0x1993) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 transmit_j1_byte[7:0] r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 - 0 transmit j1 byte value[7:0] r/w transmit j1 byte value: these read/write bit-fields permit the user to have software control over the value of the j1 byte, within each outbound sts-3c spe. if the user configures the transmit st s-3c poh processor block to this register as the source of the j1 byte , then it will automatically write the contents of this register into the j1 byte location, within each ?outbound? sts-3c spe. this feature is enabled whenever the user writes the value ?[1, 0]? into bits 1 and 0 (transmit path trace message source[1:0]) within the ?transmit sts- 3c path ? sonet path trace message control register? register. note: the address location of the transmit sts-3c path ? sonet j1 byte control register is 0x19bb table 236: transmit sts-3c path ? transmitter b3 byte error mask register (address location= 0x1997) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 transmit_b3_byte_error_mask[7:0] r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 - 0 transmit b3 byte error_mask[7:0] r/w transmit b3 byte error mask[7:0]: this read/write bit-field permits the user to insert errors into the b3 byte within each ?outbound? sts-3c spe, prior to transmission to the transmit sts-3 toh processor block. the transmit sts-3c poh processor block will perform an xor operation with the contents of this re gister, and its ?locally-computed? b3 byte value. the results of this o peration will be written back into the b3 byte-position within each ?outbound? sts-3c spe. if the user sets a particular bit-field, within this register, to ?1?, then that corresponding bit, within the ?outbound? b3 byte will be in error. note: for normal operation, the user should set this register to 0x00.
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 348 table 237: transmit sts-3c path ? transmit c2 byte value register (address location= 0x199b) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 transmit_c2_byte_value[7:0] r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 - 0 transmit c2 byte value[7:0] r/w transmit c2 byte value: these read/write bit-fields permit the user to have software control over the value of the c2 byte, within each outbound sts-3c spe. if the user configures the transmit st s-3c poh processor block to this register as the source of the c2 byte , then it will automatically write the contents of this register into the c2 byte location, within each ?outbound? sts-3c spe. this feature is enabled whenever the us er writes a ?0? into bit 2 (c2 byte insertion type) within the ?transmit st s-3c path ? sonet control register ? byte 0? register. note: the address location of the transmit sts-3c path ? sonet control register ? byte 0? register is 0x1983 table 238: transmit sts-3c path ? transmit g1 byte value register (address location= 0x199f) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 transmit_g1_byte_value[7:0] r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 - 0 transmit g1 byte value[7:0] r/w transmit g1 byte value: these read/write bit-fields permit the user to have software control over the contents of the rdi-p and rei-p bit-fields, within each g1 byte in the ?outbound? sts-3c spe. if the users sets ?rei-p_ins ertion_type[1:0]? and ?rdi- p_insertion_type[1:0]? bits to the val ue [0, 1], then contents of the rei-p and the rdi-p bit-fields (within each g1 byte of the ?outbound? sts-3c spe) will be dictated by the contents of this register. note: 1. the ?rei-p_insertion_type[1:0]? and ?rdi-p_insertion_type[1:0]? bit- fields are located in the ?transmit sts-3c path ? sonet control register ? byte 0? register. 2. the address location of the tran smit sts-3c path ? sonet control register ? byte 0? register is 0x1983
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 349 table 239: transmit sts-3c path ? transmit f2 byte value register (address location= 0x19a3) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 transmit_f2_byte_value[7:0] r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 - 0 transmit f2 byte value[7:0] r/w transmit f2 byte value: these read/write bit-fields permit the user to have software control over the value of the f2 byte, within each outbound sts-3c spe. if the user configures the transmit st s-3c poh processor block to this register as the source of the f2 byte , then it will automatically write the contents of this register into the f2 byte location, within each ?outbound? sts-3c spe. this feature is enabled whenever the user writes a ?0? into bit 7 (f2 insertion type) within the ?transmit st s-3c path ? sonet control register ? byte 0? register. note: the address location of the transmit sts-3c path ? sonet control register is 0x1983 table 240: transmit sts-3c path ? transmit h4 byte value register (address location= 0x19a7) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 transmit_h4_byte_value[7:0] r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 - 0 transmit h4 byte value[7:0] r/w transmit h4 byte value: these read/write bit-fields permit the user to have software control over the value of the h4 byte, within each outbound sts-3c spe. if the user configures the transmit st s-3c poh processor block to this register as the source of the h4 byte , then it will automatically write the contents of this register into the h4 byte location, within each ?outbound? sts-3c spe. this feature is enabled whenever the user writes a ?0? into bit 0 (h4 insertion type) within the ?transmit st s-3c path ? sonet control register ? byte 1? register. note: the address location for the ?transmit sts-3c path ? sonet control register ? byte 1? register is 0x1982
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 350 table 241: transmit sts-3c path ? transmit z3 byte value register (address location= 0x19ab) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 transmit_z3_byte_value[7:0] r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 - 0 transmit z3 byte value[7:0] r/w transmit z3 byte value: these read/write bit-fields permit the user to have software control over the value of the z3 byte, within each outbound sts-3c spe. if the user configures the transmit st s-3c poh processor block to this register as the source of the z3 byte , then it will automatically write the contents of this register into the z3 byte location, within each ?outbound? sts-3c spe. this feature is enabled whenever the user writes a ?0? into bit 1 (z3 insertion type) within the ?transmit st s-3c path ? sonet control register ? byte 1? register. note: the address location for the ?transmit sts-3c path ? sonet control register ? byte 1? register is 0x1982 table 242: transmit sts-3c path ? transmit z4 byte value register (address location= 0x19af) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 transmit_z4_byte_value[7:0] r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 - 0 transmit z4 byte value[7:0] r/w transmit z4 byte value: these read/write bit-fields permit the user to have software control over the value of the z4 byte, within each outbound sts-3c spe. if the user configures the transmit st s-3c poh processor block to this register as the source of the z4 byte , then it will automatically write the contents of this register into the z4 byte location, within each ?outbound? sts-3c spe. this feature is enabled whenever the user writes a ?0? into bit 2 (z4 insertion type) within the ?transmit st s-3c path ? sonet control register ? byte 0? register. note: the address location of the transmit sts-3c path ? sonet control register ? byte 0? register is 0x1982
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 351 table 243: transmit sts-3c path ? transmit z5 byte value register (address location= 0x19b3) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 transmit_z5_byte_value[7:0] r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 - 0 transmit z5 byte value[7:0] r/w transmit z5 byte value: these read/write bit-fields permit the user to have software control over the value of the z5 byte, within each outbound sts-3c spe. if the user configures the transmit st s-3c poh processor block to this register as the source of the z5 byte , then it will automatically write the contents of this register into the z5 byte location, within each ?outbound? sts-3c spe. this feature is enabled whenever the user writes a ?0? into bit 3 (z5 insertion type) within the ?transmit st s-3c path ? sonet control register ? byte 0? register. note: the address location of the transmit sts-3c path ? sonet control register ? byte 0? register is 0x1982
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 352 table 244: transmit sts-3c path ? transmit path control register (address location= 0x19b7) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 unused pointer force check stuff insert negative stuff insert positive stuff insert continuous ndf events insert single ndf event r/o r/o r/w r/w w w r/w r/w 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 - 6 unused r/o 5 pointer force r/w pointer force: this read/write bit-field permits the user to load the values contained within the ?transmit sts-3c poh arbitrary h1 pointer byte? and ?transmit sts-3c poh arbitrary h2 pointer byte? registers into the h1 and h2 bytes (within the outbound sts-3c data stream). note: the actual location of the spe will not be adjusted, per the value of h1 and h2 bytes. hence, this feature should cause the remote terminal to declare an ?invalid pointer? condition. 0 ? configures the transmit sts-3c poh and transmit sts-3 toh processor blocks to transmit sts-3c/sts-3 data with normal and correct h1 and h2 bytes. 1 ? configures the transmit sts-3c poh and transmit sts-3 toh processor blocks to overwrite the values of the h1 and h2 bytes (i n the outbound sts- 3c/sts-3 data-stream) with the values in the ?transmit sts-3c poh arbitrary h1 and h2 pointer byte? registers. note: 1. the address location of the transmi t sts-3c arbitrary h1 pointer byte register is 0x19bf 2. the address location of the transmi t sts-3c arbitrary h2 pointer byte register is 0x19c3 4 check stuff r/w check stuff monitoring: this read/write bit-field permits the user to configure the transmit sts-3c poh and transmit sts-3 toh processor blocks to only execute a ?positive?, ?negative? or ?ndf? event (via the ?insert positive stuff?, ?insert negative stuff?, ?insert continuous or single ndf? options, via software command) if no pointer adjustment (ndf or otherwise ) has occurred during the last 3 sonet frame periods. 0 ? disables this feature. in this mode, the transmit sts-3c poh and transmit sts-3 toh processor blocks will execute a ?software-co mmanded? pointer adjustment event, independent of whether a pointer adjust ment event has occurred in the last 3 sonet frame periods. 1 ? enables this feature. in this mode, the transmit sts-3c poh and transmit sts-3 toh processor blocks will only execute a ?software- commanded? pointer adjustment event, if no pointer adjustment event has o ccurred during the last 3 sonet frame periods. 3 insert negative stuff r/w insert negative stuff: this read/write bit-field p ermits the user to confi g ure the transmit sts-3c
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 353 poh and transmit sts-3 toh processor blocks to insert a negative-stuff into the outbound sts-3c/sts-3 data stream. this command, in-turn will cause a ?pointer decrementing? event at the remote terminal. writing a ?0? to ?1? transition into this bit-field causes the following to happen. ? a negative-stuff will occur (e.g., a single payload byte will be inserted into the h3 byte position within the outbound sts-1/sts-3 data stream). ? the ?d? bits, within the h1 and h2 bytes will be inverted (to denote a ?decrementing? pointer adjustment event). ? the contents of the h1 and h2 bytes will be decremented by ?1?, and will be used as the new pointer from this point on. note: once the user writes a ?1? into this bit-field, the XRT94L33 will automatically clear this bit-field. hence, there is no need to subsequently reset this bit-field to ?0?. 2 insert positive stuff r/w insert positive stuff: this read/write bit-field permits the user to configure the transmit sts-3c poh and transmit sts-3 toh processor bl ocks to insert a positive-stuff into the outbound sts-3c/sts-3 data stream. this command, in-turn will cause a ?pointer incrementing? event at the remote terminal. writing a ?0? to ?1? transition into this bit-field causes the following to happen. ? a positive-stuff will occur (e.g., a single stuff-byte will be inserted into the sts-3c/sts-3 data-stream, immediately a fter the h3 byte position within the outbound sts-3c/sts-3 data stream). ? the ?i? bits, within the h1 and h2 bytes will be inverted (to denote a ?incrementing? pointer adjustment event). ? the contents of the h1 and h2 bytes will be incremented by ?1?, and will be used as the new pointer from this point on. note: once the user writes a ?1? into this bit-field, the XRT94L33 will automatically clear this bit-field. hence, there is no need to subsequently reset this bit-field to ?0?. 1 insert continuous ndf events r/w insert continuous ndf events: this read/write bit-field permits t he user configure the transmit sts-3c poh and transmit sts-3 toh processor bl ocks to continuously insert a new data flag (ndf) pointer adjustment into the outbound sts-3c/sts-3 data stream. note: as the transmit sts-3c poh and transmit sts-3 toh processor blocks insert the ndf event into the sts-1/sts-3 data stream, it will proceed to load in the contents of the ?transmit sts-3c poh arbitrary h1 pointer? and ?transmit sts-3c poh arbitrary h2 pointer? registers into the h1 and h2 bytes (within the outbound sts-3c/sts-3 data stream). 0 ? configures the ?transmit st s-3c toh and transmit sts-3 poh processor? blocks to not continuously insert ndf events in to the ?outbound? sts-3c/sts-3 data stream. 1- configures the ?transmit sts-3c toh and transmit sts-3 poh processor? blocks to continuously insert ndf events into the ?outbound? sts- 3c/sts-3 data stream. 0 insert single ndf event r/w insert single ndf event: this read/write bit-field permits the user to configure the transmit sts-3c poh and transmit sts-3 toh processor blocks to insert a new data flag (ndf) pointer adjustment into the out bound sts-3c/sts-3 data stream.
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 354 writing a ?0? to ?1? transition into this bit-field causes the following to happen. ? the ?n? bits, within the h1 byte will set to the value ?1001? ? the ten pointer-value bits (within the h1 and h2 bytes) will be set to new pointer value per the contents within t he ?transmit sts-3c poh ? arbitrary h1 pointer? and ?transmit sts-3c poh arbitrary h2 pointer? registers (address location= 0xn9bf and 0xn9c3). ? afterwards, the ?n? bits will resume their normal value of ?0110?; and this new pointer value will be used as the new pointer from this point on. note: 1. once the user writes a ?1? into this bit-field, the XRT94L33 will automatically clear this bit-field. h ence, there is no need to subsequently reset this bit-field to ?0?. 2. the address location of the transmi t sts-3c arbitrary h1 pointer byte register is 0x19bf 3. the address location of the transmi t sts-3c arbitrary h2 pointer byte register is 0x19c3
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 355 table 245: transmit sts-3c path ? transmit path trace message control register (address location= 0x19bb) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 unused transmit path trace message_length[1:0] transmit path trace message source[1:0] r/o r/o r/o r/o r/w r/w r/w r/w 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 ? 4 unused r/o 3 - 2 transmit path trace message_length[1:0] r/w transmit path trace message length[1:0]: these read/write bit-fields permit the user to specify the length of the path trace message, that the transmi t sts-3c poh processor block will repeatedly transmit to the remote pte. the relationship between the content of these bit-fields and the corresponding path trace message length is presented below. transmit path trace message length[1:0] resulting path trace message length (in terms of bytes) 00 1 byte 01 16 bytes 10/11 64 bytes 1 - 0 transmit path trace message source[1:0] r/w transmit path trace message source[1:0]: these read/write bit-fields permit the user to specify the source of the ?outbound? path trace message that will be transported via the j1 byte channel within the outbound sts-3c data-stream, as depicted below. transmit path trace message source[1:0] resulting source of the path trace message 00 fixed value: the transmit sts-3c poh processor block will automatically set th e j1 byte, within each outbound sts-3c spe to the value ?0x00?. 01 the transmit path trace message buffer: the transmit sts-3c poh processor block will read out the contents within the transmit path trace message buffer, and will transmit this message to the remote pte. the transmit sts-3c poh processor block ? transmit path trace message buffer memory is located at address location 0x1d00 through 0x1d3f. 10 from the ?transmit j1 byte value[7:0]? register: in this setting, the transmit sts-3c poh processor block will read out the contents of
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 356 the ?transmit sts-3c path ? transmit j1 byte value register, and will insert this value into the j1 byte-position within each outbound sts-3c spe. 11 from the ?txpoh? input pin: in this configuration setting, the transmit sts-3c poh processor block will externally accept the contents of the ?path trace message? via the ?txpoh input port? and it will transport this message (via the j1 byte- channel) to the remote pte.
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 357 table 246: transmit sts-3c path ? transmit arbi trary h1 byte pointer register (address location= 0x19bf) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 ndf bits ss bits h1 pointer value r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 - 4 ndf bits r/w ndf (new data flag) bits: these read/write bit-fields permit the user provide the value that will be loaded into the ?ndf? bit-field (of the h1 byte), whenever a ?0 to 1? transition occurs in bit 5 (pointer force) within the ?transmit sts-3c path ? transmit path control? register. note: the address location of the transmit sts-3c path ? transmit path control register is 0x19b7 3 - 2 ss bits r/w ss bits these read/write bit-fields permits the user to provide the value that will be loaded into the ?ss? bit-fi elds (of the h1 byte) whenever a ?0 to 1? transition occurs in bit 5 (pointer force) within the ?transmit sts-3c path ? transmit path control? register. note: 1. for sonet applications, the ?ss? bits have no functional value, within the h1 byte. 2. the address location of the transmit sts-3c path ? transmit path control register is 0x19b7 1 - 0 h1 pointer value[1:0] r/w h1 pointer value[1:0]: these two read/write bit-fields, along with the constants of the ?transmit sts-3c path ? transmit arbitrary h2 byte pointer? register (address location= 0xn9c3) permit the user to provide the content s of the 10-bit pointer word. these two read/write bit-fields permit the user to define the value of the two most significant bits within the pointer word. whenever a ?0 to 1? transition occurs in bit 5 (pointer force) within the transmit sts-3c path ? transmit path control? register, the values of these two bits will be loaded into the two most significant bits within the pointer word. note: the address location of the transmit sts-3c path ? transmit path control register is 0x19b7
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 358 table 247: transmit sts-3c path ? transmit arbitrary h2 byte pointer register (address location= 0x19c3) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 h2 pointer value[7:0] r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 - 0 h2 pointer value[7:0] r/w h2 pointer value[1:0]: these eight read/write bit-fields, along with the constants of bits 1 and 0 within the ?transmit sts-3c path ? transmit arbitrary h1 pointer? register permit the user to provide the contents of the 10-bit pointer word. these two read/write bit-fields permit the user to define the value of the eight least significant bits within the pointer word. whenever a ?0 to 1? transition occurs in bit 5 (pointer force) within the transmit sts-3c path ? transmit path control? register, the values of these eight bits will be loaded into the h2 byte, within the outbound sts-3c/sts-3 data stream. note: 1. the address location of the transmit sts-3c path ? transmit arbitrary h1 pointer? register is 0x19c3 2. the address location of the transmit sts-3c path ? transmit path control register is 0x19b7 table 248: transmit sts-3c path ? transmit current pointer byte register ? byte 1 (address location= 0x19c6) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 unused tx_pointer_high[1:0] r/o r/o r/o r/o r/o r/o r/o r/o 0 0 0 0 0 0 1 0 b it n umber n ame t ype d escription 7 ? 2 unused r/o 1 - 0 tx_pointer_ high[1:0] r/o transmit pointer word ? high[1:0]: these two read-only bits, along with the contents of the ?transmit sts-3c path ? transmit current pointer byte register ? byte 0? reflect the current value of the pointer (or o ffset of the sts-3c spe wi thin the outbound sts-3c frame). these two bits contain the two most sign ificant bits within the ?10-bit pointer? word. note: the address location of the transmit sts-3c path ? transmit current pointer byte ? byte 0 register is 0x19c7
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 359 table 249: transmit sts-3c path ? transmit current pointer byte register ? byte 0 (address location= 0x19c7) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 tx_pointer_low[7:0] r/o r/o r/o r/o r/o r/o r/o r/o 0 0 0 0 1 0 1 0 b it n umber n ame t ype d escription 7 ? 0 tx_pointer_ low[7:0] r/o transmit pointer word ? low[7:0]: these two read-only bits, along with the contents of the ?transmit sts-3c path ? transmit current pointer byte register ? byte 1? reflect the current value of the pointer (or offset of t he sts-3c spe within the output sts-3c frame). these two bits contain the eight least sign ificant bits within the ?10-bit pointer? word. note: the address location of the transmit sts-3c path ? transmit current pointer byte ? byte 0 register is 0x19c6
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 360 table 250: transmit sts-3c path ? rdi-p control register ? byte 2 (address location= 0x19c9) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 unused plm-p rdi-p code[2:0] transmit rdi-p upon plm-p r/o r/o r/o r/o r/w r/w r/w r/w 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 ? 4 unused r/o 3 - 1 plm-p rdi-p code[2:0] r/w plm-p (path ? payload mismatch) defect ? rdi-p code: these three read/write bit-fields permit the user to specify the value that the transmit sts-3c po h processor block will transmit, within the rdi-p bit-fields of the g1 byte (within each ?outbound? sts-3c spe), whenever (and for t he duration that) the receive sts- 3c poh processor block detects and declares the plm-p defect condition. note: in order to enable this feat ure, the user must set bit 0 (transmit rdi-p upon plm-p) within this register to ?1?. 0 transmit rdi-p upon plm-p r/w transmit the rdi-p indicator upon declaration of the plm-p defect condition: this read/write bit-field permits the user to configure the transmit sts-3c poh processor block to au tomatically tran smit the rdi-p code (as configured in bits 3 through 1 ? within this register) towards the remote pte whenever (and for the duration that) the receive sts-3c poh processor block declares the plm-p defect condition. 0 ? configures the transmit sts- 3c poh processor block to not automatically transmit the rdi-p indicator whenever (and for the duration that) the receive sts-3c poh processor block declares the plm-p defect condition. 1 ? configures the transmit st s-3c poh processor block to automatically transmit the rdi-p indicator whenever (and for the duration that) the receive sts-3c poh processor block declares the plm-p defect condition. note: the transmit sts-3c poh processor block will transmit the rdi-p indicator (in response to the receive sts-3c poh processor block declaring the plm-p defect condition) by setting the rdi-p bit- fields (within each out bound sts-3c spe) to the contents within the ?plm-p rdi-p code[2:0]? bit-fi elds within this register.
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 361 table 251: transmit sts-3c path ? rdi-p control register ? byte 1 (address location= 0x19ca) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 tim-p rdi-p code[2:0] transmit rdi-p upon tim-p uneq-p rdi-p code[2:0] transmit rdi-p upon uneq-p r/w r/w r/w r/w r/w r/w r/w r/w 1 1 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 - 5 tim-p rdi-p code[2:0] r/w tim-p (path ? trace identification mismatch) defect ? rdi-p code: these three read/write bit-fields permit the user to specify the value that the transmit sts-3c po h processor block will transmit, within the rdi-p bit-fields of the g1 byte (within each ?outbound? sts-3c spe), whenever (and for t he duration that) the receive sts- 3c poh processor block detects and declares the tim-p defect condition. note: in order to enable this feat ure, the user must set bit 4 (transmit rdi-p upon tim-p) within this register to ?1?. 4 transmit rdi-p upon tim-p r/w transmit the rdi-p indicator upon declaration of the tim-p defect condition: this read/write bit-field permits the user to configure the transmit sts-3c poh processor block to au tomatically tran smit the rdi-p code (as configured in bits 7 through 5 ? within this register) towards the remote pte whenever (and for the duration that) the receive sts-3c poh processor block decla res the tim-p defect condition. 0 ? configures the transmit sts- 3c poh processor block to not automatically transmit the rdi-p indicator whenever (and for the duration that) the receive sts-3c poh processor block declares the tim-p defect condition. 1 ? configures the transmit st s-3c poh processor block to automatically transmit the rdi-p indicator whenever (and for the duration that) the receive sts-3c poh processor block declares the tim-p defect condition. note: the transmit sts-3c poh processor block will transmit the rdi-p indicator (in response to the receive sts-3c poh processor block declaring the tim-p defect condition) by setting the rdi-p bit- fields (within each out bound sts-3c spe) to the contents within the ?tim-p rdi-p code[2:0]? bit-fi elds within this register. 3 - 1 uneq-p rdi-p code[2:0] r/w uneq-p (path ? unequipped) defect ? rdi-p code: these three read/write bit-fields permit the user to specify the value that the transmit sts-3c po h processor block will transmit, within the rdi-p bit-fields of the g1 byte (within each ?outbound? sts-3c spe), whenever (and for t he duration that) the receive sts- 3c poh processor block detects and declares the uneq-p defect condition. note: in order to enable this feat ure, the user must set bit 0 (transmit rdi-p upon uneq-p) within this register to ?1?. 0 transmit rdi-p upon uneq-p r/w transmit the rdi-p indicator upon declaration of the uneq-p defect condition: this read/write bit-field permits the user to configure the transmit sts-3c poh processor block to automaticall y transmit the rdi-p
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 362 code (as configured in bits 7 through 5 ? within this register) towards the remote pte whenever (and for the duration that) the receive sts-3c poh processor block declare s the uneq-p defect condition. 0 ? configures the transmit sts- 3c poh processor block to not automatically transmit the rdi-p indicator whenever (and for the duration that) the receive sts-3c poh processor block declares the uneq-p defect condition. 1 ? configures the transmit st s-3c poh processor block to automatically transmit the rdi-p indicator whenever (and for the duration that) the receive sts-3c poh processor block declares the uneq-p defect condition. note: the transmit sts-3c poh processor block will transmit the rdi-p indicator (in response to the receive sts-3c poh processor block declaring the uneq-p defect co ndition) by setting the rdi-p bit-fields (within each outbound sts-3c spe) to the contents within the ?uneq-p rdi-p code[2:0]? bit- fields within this register.
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 363 table 252: transmit sts-3c path ? rdi-p control register ? byte 1 (address location= 0x19cb) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 lop-p rdi-p code[2:0] transmit rdi-p upon lop-p ais-p rdi-p code[2:0] transmit rdi-p upon ais-p r/w r/w r/w r/w r/w r/w r/w r/w 1 1 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 - 5 lop-p rdi-p code[2:0] r/w lop-p (path ? loss of pointer) defect ? rdi-p code: these three read/write bit-fields permit the user to specify the value that the transmit sts-3c po h processor block will transmit, within the rdi-p bit-fields of the g1 byte (within each ?outbound? sts-3c spe), whenever (and for t he duration that) the receive sts- 3c poh processor block detect s and declares the lop-p defect condition. note: in order to enable this feat ure, the user must set bit 4 (transmit rdi-p upon lop-p) within this register to ?1?. 4 transmit rdi-p upon lop-p r/w transmit the rdi-p indicator upon declaration of the lop-p defect condition: this read/write bit-field permits the user to configure the transmit sts-3c poh processor block to au tomatically tran smit the rdi-p code (as configured in bits 7 through 5 ? within this register) towards the remote pte whenever (and for the duration that) the receive sts-3c poh processor block declares the lop-p defect condition. 0 ? configures the transmit sts- 3c poh processor block to not automatically transmit the rdi-p indicator whenever (and for the duration that) the receive sts-3c poh processor block declares the lop-p defect condition. 1 ? configures the transmit st s-3c poh processor block to automatically transmit the rdi-p indicator whenever (and for the duration that) the receive sts-3c poh processor block declares the lop-p defect condition. note: the transmit sts-3c poh processor block will transmit the rdi-p indicator (in response to the receive sts-3c poh processor block declaring the lop-p defect condition) by setting the rdi-p bit- fields (within each out bound sts-3c spe) to the contents within the ?lop-p rdi-p code[2:0]? bit-fi elds within this register. 3 - 1 ais-p rdi-p code[2:0] r/w ais-p (path ? ais) defect ? rdi-p code: these three read/write bit-fields permit the user to specify the value that the transmit sts-3c po h processor block will transmit, within the rdi-p bit-fields of the g1 byte (within the ?outbound? sts- 3c spe), whenever (and for the duration that) the receive sts-3c poh processor block detects and declares the ais-p defect condition. note: in order to enable this feat ure, the user must set bit 0 (transmit rdi-p upon ais-p) within this register to ?1?. 0 transmit rdi-p upon ais-p r/w transmit the rdi-p indicator upon declaration of the ais-p defect condition: this read/write bit-field permits the user to configure the transmit sts-3c poh processor block to automaticall y transmit the rdi-p
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 364 code (as configured in bits 7 through 5 ? within this register) towards the remote pte whenever (and for the duration that) the receive sts-3c poh processor block decla res the ais-p defect condition. 0 ? configures the transmit sts- 3c poh processor block to not automatically transmit the rdi-p indicator whenever (and for the duration that) the receive sts-3c poh processor block declares the ais-p defect condition. 1 ? configures the transmit st s-3c poh processor block to automatically transmit the rdi-p indicator whenever (and for the duration that) the receive sts-3c poh processor block declares the ais-p defect condition. note: the transmit sts-3c poh processor block will transmit the rdi-p indicator (in response to the receive sts-3c poh processor block declaring the ais-p defect c ondition) by setting the rdi-p bit- field (within each outb ound sts-3c spe) to t he contents within the ?ais-p rdi-p code[2:0]? bit-fi elds within this register.
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 365 table 253: transmit sts-3c path ? serial port control register (address location= 0x19cf) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 unused txpoh clock speed [3:0] r/o r/o r/o r/o r/w r/w r/w r/w 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 ? 4 unused r/o 3 ? 0 txpoh clock speed [3:0] r/w txpohclk output clock signal speed: these read/write bit-fields permit the user to specify the frequency of the ?txpohclk output clock signal. the formula that relates the contents of these re gister bits to the ?txpohclk? frequency is presented below. freq = 19.44/[2 * (txpoh_clock_speed + 1) note: for sts-3/stm-1 applications, the frequency of the rxpohclk output signal must be in the range of 0.304mhz to 9.72mhz
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 366 1.9 receive sonet poh processor block the register map for the receive sonet poh processor block is presented in the table below. additionally, a detailed description of each of the ?receive sonet poh processor? block registers is presented below. in order to provide some orientation for the reader, an illustration of the functional block diagram for the XRT94L33, with the ?receive sonet poh processor block ?highlighted? is presented below in figure 6 figure 6: illustration of the function al block diagram of the xrt94l 33, with the receive sonet poh processor block ?high-lighted?. ds3/e3 framer block ds3/e3 framer block rx sts-1 pointer justification block rx sts-1 pointer justification block rx sts-1 poh block rx sts-1 poh block tx sts-1 poh block tx sts-1 poh block tx sts-1 pointer justification block tx sts-1 pointer justification block tx sts-1 toh block tx sts-1 toh block rx sts-1 toh block rx sts-1 toh block ds3/e3 jitter attenuator block ds3/e3 jitter attenuator block ds3/e3 mapper block ds3/e3 mapper block tx sonet poh processor block tx sonet poh processor block tx sts-3 toh processor block tx sts-3 toh processor block sts-3 telecom bus block sts-3 telecom bus block tx/rx line i/f block (primary) tx/rx line i/f block (primary) tx/rx line i/f block (aps) tx/rx line i/f block (aps) clock synthesizer block clock synthesizer block channel 1 to channels 2 ? 3 microprocessor interface microprocessor interface jtag test port jtag test port rx sonet poh processor block rx sonet poh processor block rx sts-3 toh processor block rx sts-3 toh processor block from channels 2 ? 3 rx sts-3 toh processor block (primary) rx sts-3 toh processor block (primary)
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 367 r eceive sonet poh p rocessor b lock r egister table 254: receive sonet poh processor block register - address map a ddress l ocation r egister n ame d efault v alues 0xn000 ? 0xn181 reserved 0x00 0xn182 receive sonet path ? control register ? byte 1 0x00 0xn183 receive sonet path ? control register ? byte 0 0x00 0xn184, 0xn185 reserved 0x00 0xn186 receive sonet path ? status register ? byte 1 0x00 0xn187 receive sonet path ? status register ? byte 0 0x00 0xn188 reserved 0x00 0xn189 receive sonet path ? interrupt status register ? byte 2 0x00 0xn18a receive sonet path ? interrupt status register ? byte 1 0x00 0xn18b receive sonet path ? interrupt status register ? byte 0 0x00 0xn18c reserved 0x00 0xn18d receive sonet path ? interrupt enable register ? byte 2 0x00 0xn18e receive sonet path ? interrupt enable register ? byte 1 0x00 0xn18f receive sonet path ? interrupt enable register ? byte 0 0x00 0xn190 ? 0xn192 reserved 0x00 0xn193 receive sonet path ? sonet receive rdi-p register 0x00 0xn194, 0xn195 reserved 0x00 0xn196 receive sonet path ? received path label byte (c2) register 0x00 0xn197 receive sonet path ? expected path label byte (c2) register 0x00 0xn198 receive sonet path ? b3 byte error count register ? byte 3 0x00 0xn199 receive sonet path ? b3 byte error count register ? byte 2 0x00 0xn19a receive sonet path ? b3 byte error count register ? byte 1 0x00 0xn19b receive sonet path ? b3 byte error count register ? byte 0 0x00 0xn19c receive sonet path ? rei-p event count register ? byte 3 0x00 0xn19d receive sonet path ? rei-p event count register ? byte 2 0x00 0xn19e receive sonet path ? rei-p event count register ? byte 1 0x00 0xn19f receive sonet path ? rei-p event count register ? byte 0 0x00 0xn1a0 ? 0xn1a2 reserved 0x00 0xn1a3 receive sonet path ? receiver j1 byte control register 0x00 0xn1a4, 0xn1a5 reserved 0xn1a6 receive sonet path ? pointer value register? byte 1 0x00
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 368 a ddress l ocation r egister n ame d efault v alues 0xn1a7 receive sonet path ? pointer value register ? byte 0 0x00 0xn1a8 ? 0xn1ba reserved 0x00 0xn1bb receive sonet path ? auto ais control register 0x00 0xn1bc ? 0xn1be reserved 0x00 0xn1bf receive sonet path ? serial port control register 0x00 0xn1c0 ? 0xn1c2 reserved 0x00 0xn1c3 receive sonet path ? sonet receiv e auto alarm register ? byte 0 0x00 0xn1c4 ? 0xn1d2 reserved 0x00 0xn1d3 receive sonet path ? receive j1 byte capture register 0x00 0xn1d4 ? 0xn1d6 reserved 0x00 0xn1d7 receive sonet path ? receive b3 byte capture register 0x00 0xn1d8 ? 0xn1da reserved 0x00 0xn1db receive sonet path ? receive c2 byte capture register 0x00 0xn1dc ? 0xn1de reserved 0x00 0xn1df receive sonet path ? receive g1 byte capture register 0x00 0xn1e0 ? 0xn1e2 reserved 0x00 0xn1e3 receive sonet path ? receive f2 byte capture register 0x00 0xn1e4 ? 0xn1e6 reserved 0x00 0xn1e7 receive sonet path ? receive h4 byte capture register 0x00 0xn1e8 ? 0xn1ea reserved 0x00 0xn1eb receive sonet path ? receive z3 byte capture register 0x00 0xn1ec ? 0xn1ee reserved 0x00 0xn1ef receive sonet path ? receive z4 (k3) byte capture register 0x00 0xn1f0 ? 0xn1f2 reserved 0x00 0xn1f3 receive sonet path ? receive z5 byte capture register 0x00 0xn1f4 ? 0xn1ff reserved 0x00
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 369 1.9.1 r eceive sonet poh p rocessor b lock r egister d escription table 255: receive sonet path ? control register ? byte 1 (address location= 0xn182, where n ranges in value from 0x02 to 0x04) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 unused ds3 ais upon async pdi-p or ais-p r/o r/o r/o r/o r/o r/o r/o r/w 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 ? 1 unused r/o 0 ds3 ais upon async pdi-p or ais-p r/w ds3 ais upon async pdi-p or ais-p: this read/write bit-field permits the user to configure the receive sonet poh processor block to automatically command the ds3/e3 framer block to transmit the ds3 ais indicator (to downstream circuitry) whenever (and for the duration that) it (the rece ive sonet poh processor block) declares the async pdi-p or ais-p defect condition within the incoming sts-1 spe data-stream. 0 ? configures the receive sonet poh processor block to not automatically command the ds3/e3 framer block to automatically transmit the ds3 ais indicator (via the egress direction) upon de claration of either the ais-p or the async pdi-p defect conditions. 1 ? configures the receive sonet po h processor block to automatically command the ds3/e3 framer block to automatically transmit the ds3 ais indicator whenever (and for the duration that) it declares either the ais-p or the pdi-p defect condition. note: note: this register bit is only valid if the incoming sts-1 signal is transporting an asynchronous ds3 signal; and if the corresponding channel (on the ?low-speed? side of the chip) is configured to operate in the ds3 mode. whenever an sts-1 signal is transporting an asynchronously-mapped ds3 signal, then a given pte will recognize and declare the pdi-p defect condition whenever it ?accepts? the c2 byte to the value ?0xfc?.
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 370 table 256: receive sonet path ? control register ? byte 0 (address location= 0xn183, where n ranges in value from 0x02 to 0x04) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 unused check stuff rdi-p type rei-p error type b3 error type r/o r/o r/o r/o r/w r/w r/w r/w 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 ? 4 unused r/o 3 check stuff r/w check (pointer adjustment) stuff select: this read/write bit-field permits the user to enable/disable the sonet standard recommendation that a pointer increment or decrement operation, detected within 3 sonet frames of a pr evious pointer adjustment operation (e.g., negative stuff, positive stuff) is ignored. 0 ? disables this sonet standard implemen tation. in this mode, all pointer- adjustment operations that are detected will be accepted. 1 ? enables this ?sonet standard? implementation. in this mode, all pointer-adjustment operat ions that are detected within 3 sonet frame periods of a previous pointer-adjus tment operation, will be ignored. 2 rdi-p type r/w path ? remote defect indicator type select: this read/write bit-field permits the user to configure the receive sonet poh processor block to support either the ?single-bit? or the ?enhanced? rdi-p form of signaling, as described below. 0 ? configures the receive sonet poh processor block to support the single-bit rdi-p. in this mode, t he receive sonet poh processor block will only monitor bit 5, within the g1 byte (of incoming spe data), in order to declare and clear the rdi-p defect condition. 1 ? configures the receive sonet poh processor block to support the enhanced rdi-p (erdi-p). in th is mode, the receive sonet poh processor block will monitor bits 5, 6 and 7, within the g1 byte, in order to declare and clear the rdi-p defect condition. 1 rei-p error type r/w rei-p error type: this read/write bit-field permits the user to specify how the ?receive sonet poh processor block will count (or tally) rei-p events, for performance monitoring purposes. t he user can configure the receive sonet poh processor block to increment rei-p events on either a ?per-bit? or ?per-frame? basis. if the user configures the receive sonet poh processor block to increment rei-p events on a ?per-bit? basis, then it will increment the ?receive sonet path re i-p event count? register by the value of the lower nibble within the g1 byte of the incoming sts-1 data- stream. if the user configures the receiv e sonet poh processor block to increment rei-p events on a ?per-frame? basis, then it will increment the ?receive sonet path rei-p event count? register each time it receives an sts-1 frame, in which the lower nibble of the g1 byte (bits 1 through 4) are set to a ?non-zero? value. 0 ? configures the receive sonet poh processor block to count or tally rei-p events on a per-bit basis. 1 ? confi g ures the receive sonet poh proc essor block to count or tall y
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 371 rei-p events on a per-bit basis. 0 b3 error type r/w b3 error type: this read/write bit-field permits the user to specify how the ?receive sonet poh processor block will count (or tally) b3 byte errors, for performance monitoring purposes. t he user can configure the receive sonet poh processor block to increment b3 byte errors on either a ?per- bit? or ?per-frame? basis. if the us er configures the receive sonet poh processor block to increment b3 byte errors on a ?per-bit? basis, then it will increment the ?receive sonet path b3 byte error count? register by the number of bits (within the b3 byte va lue of the incoming sts-1 data-stream) that is in error. if the user configures the receiv e sonet poh processor block to increment b3 byte errors on a ?per-frame? basis, then it will increment the ?receive sonet path ? b3 byte error count? register each time it receives an sts-1 spe that contains an erred b3 byte. 0 ? configures the receive sonet poh processor block to count b3 byte errors on a ?per-bit? basis. 1 ? configures the receive sonet poh processor block to count b3 byte errors on a ?per-frame? basis.
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 372 table 257: receive sonet path ? control register ? byte 0 (address location= 0xn186, where n ranges in value from 0x02 to 0x04) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 unused ds3 async pdi-p defect declared path trace message unstable defect declared r/o r/o r/o r/o r/o r/o r/o r/o 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 ? 2 unused r/o 1 ds3 async pdi-p defect declared r/o asynchronously-mapped ds3 pdi-p (payload defect indicator) defect declared: this read-only bit-field indicates wh ether or not the receive sonet poh processor block is currently declaring the ?asynchronous ds3 pdi-p defect condition. the receive sonet poh processor will de clare the ?asynchronous ds3 pdi-p? defect condition for the durati on that it has ?accepted? the c2 byte value of ?0xfc?. 0 ? indicates that the receive sonet poh processor block is not currently declaring the ?asynchronous ds3 pdi-p? defect condition. 1 ? indicates that the rece ive sonet poh processor block is currently declaring the ?asynchronous ds3 pdi-p? defect condition. notes: this register bit is only valid if the incoming sts-1 signal is transporting an asynchronously-mapped ds3 signal; and if the corresponding channel (on the ?low-speed? side of the chip) is c onfigured to operate in the ds3 mode. 0 path trace message unstable defect declared r/o path trace message unstable defect declared: this read-only bit-field indicates wh ether or not the receive sonet poh processor block is currently declaring the path trace message unstable defect condition. the receive sonet poh proc essor block will declare the path trace message unstable defect condition, whenever the ?path trace message unstable? counter reaches the value ?8 ?. the receive sonet poh processor block will increment the ?path trace message unstable? counter each time that it receives a path trace message that differs from the previously received message. the receive sonet poh processor bloc k will clear the ?path trace message unstable? counter whenever it has received a given path trace message 3 (or 5) consecutive times. 0 ? indicates that the receive sonet poh processor block is not currently declaring the ?path trace mess age unstable? defect condition. 1 ? indicates that the rece ive sonet poh processor block is currently declaring the path trace message un stable defect condition.
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 373 table 258: receive sonet path ? sonet receive po h status ? byte 0 (address location= 0xn187, where n ranges in value from 0x02 to 0x04) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 tim-p defect declared c2 byte unstable defect declared uneq-p defect declared plm-p defect declared rdi-p defect declared rdi-p unstable condition lop-p defect declared ais-p defect declared r/o r/o r/o r/o r/o r/o r/o r/o 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 tim-p defect declared r/o trace identification mismatch (tim-p) defect indicator: this read-only bit-field indicates whether or not the receive sonet poh processor block is currently declaring the ?path trace identification mismatch? (tim-p) defect condition. the receive sonet poh processor blo ck will declare the ?tim-p? defect condition, when none of the path trace message bytes within the most recently path trace message (received via the incoming sts-1 data-stream) matches the contents of the ?expected? path trace message. the receive sonet poh processor bl ock will clear the ?tim-p? defect condition, when at least 80% of the re ceived path trace message bytes (within the most recently received path trac e message) matches the contents of the ?expected? path trace message. 0 ? indicates that the receive sonet poh processor block is not currently declaring the tim-p defect condition. 1 ? indicates that the receive sone t poh processor block is currently declaring the tim-p defect condition. 6 c2 byte unstable defect declared r/o c2 byte (path signal label byte) unstable indicator: this read-only bit-field indicates whether or not the receive sonet poh processor block is currently declaring the ?c2 byte unstable? defect condition. the receive sonet poh processor block will declare the ?c2 byte unstable? defect condition, whenever the ?c2 byte unstable? counter reaches the value of ?5?. the receive sonet poh processor block will increment the ?c2 unstable? counter each time that it rece ives an spe with a c2 byte value that differs from the previously received c2 byte value. the receive sonet poh processor block will clear the contents of the ?c2 unstable? counter to ?0? whenever it has received 3 (or 5) consec utive spes of the same c2 byte value. 0 ? indicates that the receive sonet poh processor block is not currently declaring the c2 (path signal label byte) unstable defect condition is not declared. 1 ? indicates that the receive sone t poh processor block is currently declaring the c2 (path signal label byte) unstable defect condition. 5 uneq-p defect declared r/o path ? unequipped (uneq-p) defect declared: this read-only bit-field indicates whether or not the receive sonet poh processor block is currently declari ng the uneq-p defect condition. the receive sonet poh processor bl ock will declare the uneq-p defect condition, anytime that it, unexpectedly receives at least five (5) consecutive sts-1 frames, in which the c2 byte was set to the value ?0x00? (which indicates that the spe is ?unequipped?). the receive sonet poh processor block will clear the uneq-p defect
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 374 condition, if it receives at least five (5) consecutive sts-1 frames, in which the c2 byte was set to a value other than 0x00. 0 ? indicates that the receive sonet poh processor block is not declaring the uneq-p defect condition. 1 ? indicates that the receive sone t poh processor block is currently declaring the uneq-p defect condition. note: the receive sonet poh processor block will not declare the uneq- p defect condition if it configured to expect to receive sonet frames with c2 bytes being set to ?0x00? (e .g., if the ?receive sonet path ? expected path label value? register ?address location= 0xn197) is set to ?0x00?. 4 plm-p defect declared r/o path payload mismatch (plm-p) defect declared: this read-only bit-field indicates whether or not the receive sonet poh processor block is currently decl aring the plm-p defect condition. the receive sonet poh processor block will declare the plm-p defect condition, if it receives at least five (5) consecutive sts-1 frames, in which the c2 byte was set to a value other than that which it is expecting to receive. whenever the receive sonet poh processor block is checking in order to determine whether or not it should decla re the plm-p defect, it will check the contents of the following two registers. ? the ?receive sonet path ? received path label value? register (address location= 0xn196). ? the ?receive sonet path ? expected path label value? register (address location= 0xn197). the ?receive sonet path ? expected path label value? register contains the value of the c2 bytes, that the receive sonet po h processor blocks expects to receive. the ?receive sonet path ? received path label value? register contains the value of the c2 byte, that the receiv e sonet poh processor block has most recently ?accepted? or ?validated? (by receiving this same c2 byte in five consecutive sonet frames). the receive sonet poh processor block will declare a plm-p defect condition; if the contents of these two register do not match. the receive sonet poh processor block will clear t he plm-p defect condition if whenever the contents of these two registers do match. 0 ? indicates that the receive sonet poh processor block is not currently declaring the plm-p defect condition. 1 ? indicates that the receive sone t poh processor block is currently declaring the plm-p defect condition. notes: 1. the receive sonet poh processor block will clear the plm-p defect condition, upon declaring the uneq-p defect condition. 2. if the receive sonet poh proce ssor block unexpectedly accepts the c2 byte value of ?0x00?, then it will not declare the plm-p defect condition. in this case, the re ceive sonet poh processor block will declare the uneq-p defect condition 3 rdi-p defect declared r/o path remote defect indicator (rdi-p) defect declared: this read-only bit-field indicates whether or not the receive sonet poh processor block is currently declaring the rdi-p defect condition. if the receive sonet poh processor block is configured to support the ?sin g le-bit rdi-p? function, then it will decl are the rdi-p defect condition if bit 5
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 375 (within the g1 byte of the incoming sts-1 frame) is set to ?1? for ?rdi-p_thrd? number of incoming consecutive sts-1 spes. if the receive sonet poh processor block is configured to support the enhanced rdi-p? (erdi-p) function, then it will declare the rdi-p defect condition if bits 5, 6 and 7 (within the g1 byte of the incoming sts-1 frame) are set to either [0, 1, 0], [1, 0, 1] or [1, 1, 0] for ?rdi-p_thrd? number of consecutive sts-1 frames. 0 ? indicates that the receive sonet poh processor block is not declaring the rdi-p defect condition. 1 ? indicates that the receive sone t poh processor block is currently declaring the rdi-p defect condition. note: the user can specify the value for ?rdi-p_thrd? by writing the appropriate data into bits 3 through 0 (rdi-p thrd) within the ?receive sonet path ? sonet receive rdi-p register (address location= 0xn193). 2 rdi-p unstable defect declared r/o rdi-p (path ? remote defect indicator) unstable defect declared: this read-only bit-field indicates whether or not the receive sonet poh processor block is currently declaring t he ?rdi-p unstable? defect condition. the receive sonet poh processor bloc k will declare the ?rdi-p unstable? defect condition whenever the ?rdi-p unstable counter? reaches the value ?rdi-p thrd?. the receive sonet poh processor block will increment the ?rdi-p unstable? counter each time that it receives an rdi-p value that differs from that of the previous sts-1 fram e. the receive sonet poh processor block will clear the ?rdi-p unstable? counter to ?0? whenever it has received the same rdi-p value is received in ? rdi-p_thrd? consecutive sts-1 frames. 0 ? indicates that the receive sonet poh processor block is not currently declaring the rdi-p unstable defect condition. 1 ? indicates that the receive sone t poh processor block is currently declaring the rdi-p unstable defect condition. note: the user can specify the value for ?rdi-p_thrd? by writing the appropriate data into bits 3 through 0 (rdi-p thrd) within the ?receive sonet path ? sonet receive rdi-p register (address location= 0xn193). 1 lop-p defect declared r/o loss of pointerdefect indicator (lop-p) defect declared: this read-only bit-field indicates whether or not the receive sonet poh processor block is currently declaring the lop-p (loss of pointer) defect condition. the receive sonet poh processor bl ock will declare the lop-p defect condition, if it c annot detect a valid pointer (h1 and h2 bytes, within the toh) within 8 to 10 consecutive sonet frames. further, the receive sonet poh processor block will declare the lop-p defe ct condition, if it detects 8 to 10 consecutive ndf events. the receive sonet poh processor block will clear the lop-p defect condition, whenever it detects valid poi nter bytes (e.g., the h1 and h2 bytes, within the toh) and normal ndf value for three consecutive incoming sonet frames. 0 ? indicates that the receive sonet poh processor block is not currently declaring the lop-p defect condition. 1 ? indicates that the receive sone t poh processor block is currently declaring the lop-p defect condition. 0 ais-p defect declared r/o path ais (ais-p) defect declared: this read-only bit-field indicates whether or not the receive sonet poh processor block is currentl y declarin g the ais-p defect condition. the receive
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 376 sonet poh processor block will declare t he ais-p defect condition if it detects all of the following conditions within three consecutive incoming sts-1 frames. ? the h1, h2 and h3 bytes are set to an ?all ones? pattern. ? the entire spe is set to an ?all ones? pattern. the receive sonet poh processor block will clear the ais-p defect condition whenever it detects a valid sts-1 point er (h1 and h2 bytes) and a ?set? of ?normal? ndf for three consecutive sts-1 frames. 0 ? indicates that the receive sonet poh processor block is not currently declaring the ais-p defect condition. 1 ? indicates that the receive sone t poh processor block s currently declaring the ais-p defect condition. note: the receive sonet poh processor block will not declare the lop- p defect condition if it detects an ?a ll ones? pattern in the h1, h2 and h3 bytes. it will, instead, decl are the ais-p defect condition.
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 377 table 259: receive sonet path ? sonet receive pa th interrupt status ? byte 2 (address location= 0xn189, where n ranges in value from 0x02 to 0x04) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 change in pdi-p defect condition interrupt status unused detection of ais pointer interrupt status detection of pointer change interrupt status poh capture interrupt status change in tim-p defect condition interrupt status change in path trace message unstable defect condition interrupt status rur r/o r/o rur rur rur rur rur 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 change in pdi-p defect condition interrupt status: rur change in pdi-p defect condition interrupt status: this reset-upon-read bit-field indicates whether or not the ?change in pdi-p defect condition? interrupt co ndition has occurred since the last read of this register. if this interrupt is enabled, then t he receive sonet poh processor block will generate an interrupt in response to either of the following conditions. ? whenever the receive sonet poh processor block declares the ds3 asynchronous pdi-p defect condition (e.g., whenever the receive sonet poh processor block accepts? a c2 byte value of ?0xfc?). ? whenever the receive sonet poh processor block clears the ds3 asynchronous pdi-p defect condition (e.g., whenever the receive sonet poh processor block has ?removed? the c2 byte value of ?0xfc? by accepting a di fferent c2 by te value). 0 ? indicates that the ?change in pdi-p defect condition? interrupt has not occurred since the last read of this register. 1 ? indicates that the ?change in pdi-p defect condition? interrupt has occurred since the last read of this register. notes: 1. this register bit is only valid if the incoming sts-1 signal is transporting an asynchronous ds3 signal; and if the corresponding channel (on the ?low-speed? side of the XRT94L33 device) is configured to operate in the ds3 mode. 2. the user can determine whether or not the receive sonet poh processor block is current ly declaring the pdi-p defect condition by reading out the stat e of bit 1 (ds3 asynch pdi-p defect declared) within the ?receive sonet path ? control register ? byte 0? (address = 0xn186). 6 - 5 unused r/o 4 detection of ais pointer interrupt status rur detection of ais pointer interrupt status: this reset-upon-read bit-field indicates whether or not the ?detection of ais pointer? interrupt has occurred si nce the last read of this register. if this interrupt is enabled, then t he receive sonet poh processor block will g enerate this interru p t an y time it detects an ?ais pointer? in the
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 378 incoming sts-1 data stream. note: an ?ais pointer? is defined as a condition in which both the h1 and h2 bytes (within the toh) are each set to an ?all ones? pattern. 0 ? indicates that the ?detection of ais pointer? interrupt has not occurred since the last read of this register. 1 ? indicates that the ?detection of ais pointer? interrupt has occurred since the last read of this register. 3 detection of pointer change interrupt status rur detection of pointer change interrupt status: this reset-upon-read bit-field indicates whether or not the ?detection of pointer change? interrupt has occurred since the last read of this register. if this interrupt is enabled, then t he receive sonet poh processor block will generate an interrupt anytime it accepts a new pointer value (e.g., h1 and h2 bytes, in the toh bytes). 0 ? indicates that the ?detection of pointer change? interrupt has not occurred since the last read of this register. 1 ? indicates that the ?detection of pointer change? interrupt has occurred since the last read of this register. 2 poh capture interrupt status rur path overhead data capture interrupt status: this reset-upon-read bit-field indicates whether or not the ?poh capture? interrupt has occurred sinc e the last read of this register. if this interrupt is enabled, then t he receive sonet poh processor block will generate an interrupt once the z5 byte (e.g., the last poh byte) has been loaded into the poh capture bu ffer. the contents of the poh capture buffer will remain intact for one sonet frame period. afterwards, the poh data, for the next spe will be loaded into the ?poh capture? buffer. 0 ? indicates that the ?poh capture? interrupt has not occurred since the last read of this register. 1 ? indicates that the ?poh capture? interrupt has occurred since the last read of this register. note: the user can obtain the contents of the poh, within the most recently received spe by reading out the contents of address locations ?0xn0d3? through ?0xn0f3?). 1 change in tim-p defect condition interrupt status rur change in tim-p (trace identification mismatch) defect condition interrupt. this reset-upon-read bit-field indicates whether or not the ?change in tim-p? defect condition interrupt has occurred since the last read of this register. if this interrupt is enabled, then t he receive sonet poh processor block will generate an interrupt in response to either of the following events. ? whenever the receive sonet poh processor block declares the tim- p defect condition. ? whenever the receive sonet poh processor block clears the tim-p defect condition. 0 ? indicates that the ?change in ti m-p defect condition? interrupt has not occurred since the last read of this register. 1 ? indicates that the ?change in ti m-p defect condition? interrupt has occurred since the last read of this register.
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 379 note: the user can determine whether or not the receive sonet poh processor block is currently declaring the tim-p defect condition by reading out the state of bit 7 (tim-p defect declared) within the ?receive sonet path ? receive sonet poh stat us register ? byte 0 (address = 0xn187). 0 change in path trace message unstable defect condition interrupt status rur change in path trace identification message unstable defect condition? interrupt status: this reset-upon-read bit-field indicates whether or not the ?change in path trace identification message un stable defect condition? interrupt has occurred since the last read of this register. if this interrupt is enabled, then t he receive sonet poh processor block will generate an interrupt in response to either of the following events. ? whenever the receive sonet poh processor block declare the ?path trace message unstable? defect condition. ? whenever the receive sonet poh processor block clears the ?path trace message unstable? defect condition. 0 ? indicates that the ?change in path trace message unstable defect condition? interrupt has not occurred si nce the last read of this register. 1 ? indicates that the ?change in path trace message unstable defect condition? interrupt has occurred sinc e the last read of this register.
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 380 table 260: receive sonet path ? sonet receive pa th interrupt status ? byte 1 (address location= 0xn18a, where n ranges in value from 0x02 to 0x04) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 new path trace message interrupt status detection of rei-p event interrupt status change in uneq-p defect condition interrupt status change in plm-p defect condition interrupt status new c2 byte interrupt status change in c2 byte unstable defect condition interrupt status change in rdi-p unstable defect condition interrupt status new rdi-p value interrupt status rur rur rur rur rur rur rur rur 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 new path trace message interrupt status rur new path trace message interrupt status: this reset-upon-read bit-field indicates whether or not the ?new path trace message? interrupt has occurred si nce the last read of this register. if this interrupt is enabled, then the receive sonet poh processor block will generate an interrupt anytime it has accepted (or validated) and new path trace message. 0 ? indicates that the ?new path trace message? interrupt has not occurred since the last read of this register. 1 ? indicates that the ?new path trace message? interrupt has occurred since the last read of this register. 6 detection of rei- p event interrupt status rur detection of rei-p event interrupt status: this reset-upon-read bit-field indicates whether or not the ?detection of rei-p event? interrupt has occurred sinc e the last read of this register. if this interrupt is enabled, then the receive sonet poh processor block will generate an interrupt anytime it detects an rei-p event within the incoming sts-1 data-stream. 0 ? indicates that the ?d etection of rei-p event? interrupt has not occurred since the last read of this register. 1 ? indicates that the ?detection of rei-p event? interr upt has occurred since the last read of this register. 5 change in uneq-p defect condition interrupt status rur change in uneq-p (path ? unequipped) defect condition interrupt status: this reset-upon-read bit-field indicates whether or not the ?change in uneq-p defect condition? interrupt has occurred since the last read of this register. if this interrupt is enabled, then the receive sonet poh processor block will generate an interrupt in response to either of the following conditions. ? whenever the receive sonet poh processor block declares the uneq-p defect condition. ? whenever the receive sonet poh processor block clears the uneq-p defect condition. 0 ? indicates that the ?change in uneq -p defect condition? interrupt has not occurred since the last read of this register. 1 ? indicates that the ?chan g e in uneq-p defect condition? interru p t has
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 381 occurred since the last read of this register. note: the user can determine if the receive sonet poh processor block is currently declaring the uneq-p defect condition by reading out the state of bit 5 (une q-p defect declared) within the ?receive sonet path ? sonet receive poh status ? byte 0? register (address location= 0xn187). 4 change in plm- p defect condition interrupt status rur change in plm-p (path ? payload mismatch) defect condition interrupt status: this reset-upon-read bit indicates whether or not the ?change in plm-p defect condition? interrupt has occurred since the last read of this register. if this interrupt is enabled, then the receive sonet poh processor block will generate an interrupt in response to either of the following conditions. ? whenever the receive sonet poh processor block declares the ?plm- p? defect condition. ? whenever the receive sonet poh processor block clears the ?plm-p? defect condition. 0 ? indicates that the ?change in pl m-p defect condition? interrupt has not occurred since the last read of this register. 1 ? indicates that the ?change in pl m-p defect condition? interrupt has occurred since the last read of this register. note: the user can determine if t he receive sonet poh processor block is currently declaring the plm-p defect condition by reading out the state of bit 4 (plm-p defect declared) within the ?receive sonet path ? sonet receive poh status ? byte 0? register (address location = 0xn187). 3 new c2 byte interrupt status rur new c2 byte interrupt status: this reset-upon-read bit-field indicates whether or not the ?new c2 byte? interrupt has occurred since the last read of this register. if this interrupt is enabled, then the receive sonet poh processor block will generate an interrupt anytime it has accepted a new c2 byte. 0 ? indicates that the ?new c2 byte? interrupt has not occurred since the last read of this register. 1 ? indicates that the ?new c2 byte? interrupt has occurred since the last read of this register. note: once the receive sonet poh processor block has ?accepted? a new c2 byte value, it will load the value of this byte into the ?receive sonet path ? receive path label value? register (address = 0xn196). 2 change in c2 byte unstable defect condition interrupt status rur change in c2 byte unstable defect condition interrupt status: this reset-upon-read bit-field indicates whether or not the ?change in c2 byte unstable defect condition? interrupt has occurred since the last read of this register. if this interrupt is enabled, then the receive sonet poh processor block will generate an interrupt in response to either of the following events. ? whenever the receive sonet poh processor block declares the ?c2 byte unstable? defect condition. ? whenever the receive sonet poh processor block clears the ?c2 byte unstable? defect condition. 0 ? indicates that the ?change in c2 byte unstable defect condition? interrupt has not occurred since the last read of this register. 1 ? indicates that the ?chan g e in c2 b y te unstable defect condition?
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 382 interrupt has occurred since the last read of this register. note: the user can determine whether or not the receive sonet poh processor block is currently declaring the ?c2 byte unstable defect condition? by reading out the state of bit 6 (c2 byte unstable defect declared) within the ?receive sonet path ? sonet receive poh status ? byte 0? register (address location= 0xn187). 1 change in rdi-p unstable defect condition interrupt status rur change in rdi-p unstable defect condition interrupt status: this reset-upon-read bit-field indicates whether or not the ?change in rdi-p unstable defect condition? interru pt has occurred since the last read of this register. if this interrupt is enabled, then the receive sonet poh processor block will generate an interrupt in response to either of the following conditions. ? whenever the receive sonet poh processor block declares the ?rdi-p unstable? defect condition. ? when the receive sonet poh processor block clears the ?rdi-p unstable? defect condition. 0 ? indicates that the ?change in rdi-p unstable defect condition? interrupt has not occurred since the la st read of this register. 1 ? indicates that the ?change in rdi-p unstable defect condition? interrupt has occurred since the last read of this register. note: the user can determine whether or not the receive sonet poh processor block is currnelty declar ing the ?rdi-p unstable defect condition? by reading out the stat e of bit 2 (rdi-p unstable defect condition) within the ?receive sonet path ? sonet receive poh status ? byte 0? register (address location= 0xn187). 0 new rdi-p value interrupt status rur new rdi-p value interrupt status: this reset-upon-read bit-field indicates whether or not the ?new rdi-p value? interrupt has occurred since the last read of this register. if this interrupt is enabled, then the receive sonet poh processor block will generate this interrupt anytime it receives and ?validates? a new rdi-p value. 0 ? indicates that the ?new rdi-p value? interrupt has not occurred since the last read of this register. 1 ? indicates that the ?new rdi-p value? interrupt has occurred since the last read of this register. note: the user can obtain the ?new rdi -p value? by reading out the contents of the ?rdi-p accept[2:0]? bit-fields. these bit-fields are located in bits 6 through 4, within the ?receive sonet path ? sonet receive rdi-p register? (address location=0xn193).
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 383 table 261: receive sonet path ? sonet receive pa th interrupt status ? byte 0 (address location= 0xn18b, where n ranges in value from 0x02 to 0x04) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 detection of b3 byte error interrupt status detection of new pointer interrupt status detection of unknown pointer interrupt status detection of pointer decrement interrupt status detection of pointer increment interrupt status detection of ndf pointer interrupt status change of lop-p defect condition interrupt status change of ais-p defect condition interrupt status rur rur rur rur rur rur rur rur 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 detection of b3 byte error interrupt status rur detection of b3 byte error interrupt status: this reset-upon-read bit-field indicates whether or not the ?detection of b3 byte error? interrupt has occurred si nce the last read of this register. if this interrupt is enabled, then the receive sonet poh processor block will generate an interrupt anytime it detects a b3 byte error in the incoming sts-1 data stream. 0 ? indicates that the ?detection of b3 byte error? interrupt has not occurred since the last read of this interrupt. 1 ? indicates that the ?d etection of b3 byte error? interrupt has occurred since the last read of this interrupt. 6 detection of new pointer interrupt status rur detection of new pointer interrupt status: this reset-upon-read indicates whether the ?detection of new pointer? interrupt has occurred since the last read of this register. if the user enables this interrupt, then the receive sonet poh processor block will generate an interrupt anytime it detects a new pointer value in the incoming sts-1 frame. note: pointer adjustments with ndf will not generate this interrupt. 0 ? indicates that the ?detection of new pointer? interrupt has not occurred since the last read of this register. 1 ? indicates that the ?detection of new pointer? interrupt has occurred since the last read of this register. 5 detection of unknown pointer interrupt status rur detection of unknown pointer interrupt status: this reset-upon-read bit-field indicates whether or not the ?detection of unknown pointer? interrupt has occurred since the last read of this register. if the user enables this interrupt, then the receive sonet poh processor block will generate an interrupt anytime t hat it detects a ? pointer? that does not fit into any of the following categories. ? an increment pointer ? a decrement pointer ? an ndf pointer ? an ais (e.g., all ones) pointer ? new pointer 0 ? indicates that the ?detection of unknown pointer? interru p t has not
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 384 occurred since the last read of this register. 1 ? indicates that the ?detection of unknown pointer? in terrupt has occurred since the last read of this register. 4 detection of pointer decrement interrupt status rur detection of pointer decrement interrupt status: this reset-upon-read bit-field indicates whether or not the ?detection of pointer decrement? interrupt has occurred since the last read of this register. if this interrupt is enabled, then the receive sonet poh processor block will generate an interrupt anytime it detects a ?pointer decrement? event. 0 ? indicates that the ?d etection of pointer decrement? interrupt has not occurred since the last read of this register. 1 ? indicates that the ?detection of pointer decrement? interrupt has occurred since the last read of this register. 3 detection of pointer increment interrupt status rur detection of pointer increment interrupt status: this reset-upon-read bit-field indicates whether or not the ?detection of pointer increment? interrupt has occurred since the last read of this register. if this interrupt is enabled, then the receive sonet poh processor block will generate an interrupt anytime it detects a ?pointer increment? event. 0 ? indicates that the ?d etection of pointer incr ement? interrupt has not occurred since the last read of this register. 1 ? indicates that the ?detection of pointer increment? interrupt has occurred since the last read of this register. 2 detection of ndf pointer interrupt status rur detection of ndf pointer interrupt status: this reset-upon-read bit-field indicates whether or not the ?detection of ndf pointer? interrupt has occurred since the last read of this register. if the user enables this interrupt, t hen the receive sonet poh processor block will generate an interrupt anytime it detects an ndf pointer event. 0 ? indicates that the ?detection of ndf pointer? interrupt has not occurred since the last read of this register. 1 ? indicates that the ?detection of ndf pointer? interrupt has occurred since the last read of this register. 1 change of lop- p defect condition interrupt status rur change of lop-p defect condition interrupt status: this reset-upon-read bit-field indicates whether or not the ?change in lop-p defect condition? interrupt has occurred since the last read of this register. if the user enables this interrupt, then the receive sonet poh processor block will generate an interrupt in response to either of the following events. ? whenever the receive sonet poh processor block declares the lop-p defect condition. ? whenever the receive ?sonet poh processor? block clears the lop-p defect condition. 0 ? indicates that the ?change in lo p-p defect condition? interrupt has not occurred since the last read of this register. 1 ? indicates that the ?change in lo p-p defect condition? interrupt has occurred since the last read of this register. note: the user can determine if the receive sonet poh processor block is currently declaring the lo p-p defect condition by reading out the state of bit 1 ( lop - p defect declared ) within the ?receive
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 385 sonet path ? sonet receive poh status ? byte 0? register (address location= 0xn187). 0 change of ais-p defect condition interrupt status rur change of ais-p defect condition interrupt status: this reset-upon-read bit-field indicates whether or not the ?change of ais-p defect condition? interrupt has occurred since the last read of this register. if this interrupt is enabled, then the receive sonet poh processor block will generate an interrupt in response to either of the following events. ? whenever the receive sonet poh processor block declares the ais-p defect condition. ? whenever the receive sonet poh processor block clears the ais-p defect condition. 0 ? indicates that the ?change of ai s-p defect condition? interrupt has not occurred since the last read of this register. 1 ? indicates that the ?change of ai s-p defect condition? interrupt has occurred since the last read of this register. note: the user can determine if the receive sonet poh processor block is currently declaring the ais-p defect condition by reading out the state of bit 0 (ais-p defect declared) within the ?receive sonet path ? sonet receive poh status ? byte 0? register (address location= 0xn187).
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 386 table 262: receive sonet path ? sonet receive path interrupt enable ? byte 2 (address location= 0xn18d, where n ranges in value from 0x02 to 0x04) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 change in pdi-p defect condition interrupt enable unused detection of ais pointer interrupt enable detection of pointer change interrupt enable poh capture interrupt enable change in tim-p defect condition interrupt enable change in path trace message unstable defect condition interrupt enable r/w r/o r/o r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 change in pdi-p defect condition interrupt enable r/w change in pdi-p condition interrupt enable: this read/write bit-field permits the user to either enable or disable the ?change in pdi-p defect condition? in terrupt. if this interrupt is enabled, then the receive sonet poh processor block will generate an interrupt in response to either of the following conditions. ? whenever the receive sonet poh processor block declares the ds3 asynchronous pdi-p defect condition (e.g, whenever it accepts a c2 byte value of ?0xfc?). ? whenever the receive sonet poh processor block clears the ds3 asychronous pdi-p defect condition (e.g., whenever it has ?removed? the c2 byte value of ?0xfc? by accepting a different c2 byte value). 0 ? disables the ?change in pdi-p defect condition? interrupt. 1 ? enables the ?change in pdi-p defect condition? interrupt. notes: 1. this register bit is only valid if the incoming sts-1 signal is transporting an asynchronously-mapped ds3 signal; and if the corresponding channel (on the ?low-speed? side of the XRT94L33 device) is configured to operate in the ds3 mode. 2. the user can determine whether or not the receive sonet poh processor block is currently declaring the pdi-p defect condition by reading out the st ate of bit 1 (ds3 async pdi-p defect declared) within the receive sonet path ? control register ? byte 0 (address = 0xn186). 6 - 5 unused r/o 4 detection of ais pointer interrupt enable r/w detection of ais pointer interrupt enable: this read/write bit-field permits the user to either enable or disable the ?detection of ais pointer? interrupt. if the user enables this interrupt, then the receive sonet poh processor block will generate an interrupt anytime it detects an ?ais pointer?, in the incoming sts-1 data stream. note: an ?ais pointer? is defined as a condition in which both the h1 and h2 bytes (within the toh) are each set to an ?all ones? pattern. 0 ? disables the ?detection of ais pointer? interrupt.
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 387 1 ? enables the ?detection of ais pointer? interrupt. 3 detection of pointer change interrupt enable r/w detection of pointer change interrupt enable: this read/write bit-field permits the user to either enable or disable the ?detection of pointer change? interrupt. if this interrupt is enabled, then t he receive sonet poh processor block will generate an interrupt anytime it has accepted a new pointer value. 0 ? disables the ?detection of pointer chan ge? interrupt. 1 ? enables the ?detection of pointer change? interrupt. 2 poh capture interrupt enable r/w path overhead data capture interrupt enable: this read/write bit-field permits the user to either enable or disable the ?poh capture? interrupt. if this interrupt is enabled, then t he receive sonet poh processor block will generate an interrupt once the z5 byte (e.g., the la st poh byte) has been loaded into the poh capture bu ffer. the contents of the poh capture buffer will remain intact for one sonet frame period. afterwards, the poh data for the next spe will be loaded into the ?poh capture? buffer. 0 ? disables the ?poh capture? interrupt 1 ? enables the ?poh capture? interrupt. 1 change in tim-p defect condition interrupt enable r/w change in tim-p (trace identification mismatch) defect condition interrupt: this read/write bit-field permits the user to either enable or disable the ?change in tim-p defect condition? interrupt. if this interrupt is enabled, then t he receive sonet poh processor block will generate an interrupt in response to either of the following events. ? whenever the receive sonet poh processor block declares the tim- p defect condition. ? whenever the receive sonet poh processor block clears the tim-p defect condition. 0 ? disables the ?change in tim-p defect condition? interrupt. 1 ? enables the ?change in tim-p defect condition? interrupt. note: the user can determine whether or not the receive sonet poh processor block is currently declaring the tim-p defect condition by reading out the state of bit 7 (tim-p defect declared) within the ?receive sonet path ? receive sonet poh st atus register ? byte 0 (address = 0xn187). 0 change in path trace message unstable condition interrupt enable r/w change in ?path trace message unstable defect condition? interrupt status: this read/write bit-field permits the user to either enable or disable the ?change in path trace message unstable defect condition? interrupt. if this interrupt is enabled, then t he receive sonet poh processor block will generate an interrupt in response to either of the following events. ? whenever the receive sonet po h processor block declares the ?path trace message unst able? defect condition. ? whenever the receive sonet poh processor block clears the ?path trace message unstable? defect condition. 0 ? disables the ?change in path trace message unstable defect condition? interrupt.
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 388 1 ? enables the ?change in path trace message unstable defect condition? interrupt.
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 389 table 263: receive sonet path ? sonet receive path interrupt enable ? byte 1 (address location= 0xn18e, where n ranges in value from 0x02 to 0x04) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 new path trace message interrupt enable detection of rei-p event interrupt enable change in uneq-p defect condition interrupt enable change in plm-p defect condition interrupt enable new c2 byte interrupt enable change in c2 byte unstable defect condition interrupt enable change in rdi-p unstable defect condition interrupt enable new rdi-p value interrupt enable r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 new path trace message interrupt enable r/w new path trace message interrupt enable: this read/write bit-field permits the user to either enable or disable the ?new path trace message? interrupt. if this interrupt is enabled, then the receive sonet poh processor block will generate an interrupt anytime it has accepted (or validated) and new path trace message. 0 ? disables the ?new path trace message? interrupt. 1 ? enables the ?new path trace message? interrupt. 6 detection of rei-p event interrupt enable r/w detection of rei-p event interrupt enable: this read/write bit-field permits the user to either enable or disable the ?detection of rei-p event? interrupt. if this interrupt is enabled, then he receive sonet poh processor block will generate an interrupt anytime it detects an rei-p event within the coming sts-1 data-stream. 0 ? disables the ?detection of rei-p event? interrupt. 1 ? enables the ?detection of rei-p event? interrupt. 5 change in uneq-p defect condition interrupt enable r/w change in uneq-p (path ? unequipped) defect condition interrupt enable: this read/write bit-field permits the user to either enable or disable the ?change in uneq-p defect condition? interrupt. if this interrupt is enabled, then the receive sonet poh processor block will generate an interrupt in response to either of the following conditions. ? whenever the receive sonet poh processor block declares the uneq-p defect condition. ? whenever the receive sonet poh processor block clears the uneq-p defect condition. 0 ? disables the ?change in uneq-p defect condition? interrupt. 1 ? enables the ?change in uneq-p defect condition? interrupt. 4 change in plm-p defect condition interrupt enable r/w change in plm-p (path ? payload label mismatch) defect condition interrupt enable: this read/write bit permits the user to either enable or disable the ?change in plm-p defect condition? interrupt.
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 390 if this interrupt is enabled, then the receive sonet poh processor block will generate an interrupt in response to either of the following conditions. ? whenever the receive sonet poh processor block declares the ?plm-p? defect condition. ? whenever the receive sonet poh processor block clears the ?plm- p? defect condition. 0 ? disables the ?change in plm-p defect condition? interrupt. 1 ? enables the ?change in plm-p defect condition? interrupt. 3 new c2 byte interrupt enable r/w new c2 byte interrupt enable: this read/write bit-field permits the user to either enable or disable the ?new c2 byte? interrupt. if this interrupt is enabled, then the receive sonet poh processor block will generate an interrupt anytime it has accepted a new c2 byte. 0 ? disables the ?new c2 byte? interrupt. 1 ? enables the ?new c2 byte? interrupt. note: the user can obtain the value of this ?new c2? byte by reading the contents of the ?receive sonet path ? received path label value? register (address location= 0xn196). 2 change in c2 byte unstable defect condition interrupt enable r/w change in c2 byte unstable defect condition interrupt enable: this read/write bit-field permits the user to either enable or disable the ?change in c2 byte unstable defect condition? interrupt. if this interrupt is enabled, then the receive sonet poh processor block will generate an interrupt in response to either of the following events. ? whenever the receive sonet poh processor block declares the ?c2 byte unstable? defect condition. ? whenever the receive sonet poh processor block clears the ?c2 byte unstable? defect condition. 0 ? disables the ?change in c2 byte unstable defect condition? interrupt. 1 ? enables the ?change in c2 byte unstable defect condition? interrupt. 1 change in rdi-p unstable defect condition interrupt enable r/w change in rdi-p unstable defect condition interrupt enable: this read/write bit-field permits the user to either enable or disable the ?change in rdi-p unstable defect condition? interrupt. if this interrupt is enabled, then the receive sonet poh processor block will generate an interrupt in response to either of the following conditions. ? whenever the receive sonet poh processor block declares the ?rdi-p unstable? defect condition. ? whenever the receive sonet poh processor block clears the ?rdi-p unstable? defect condition. 0 ? disables the ?change in rdi-p unstable defect condition? interrupt. 1 ? enables the ?change in rdi-p unstable defect condition? interrupt. 0 new rdi-p value interrupt enable r/w new rdi-p value interrupt enable: this read/write bit-field permits the user to either enable or disable the ?new rdi-p value? interrupt. if this inter r u p t is enabled, then the receive sonet poh processor
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 391 block will generate this interrupt anyt ime it receives and ?validates? a new rdi-p value. 0 ? disables the ?new rdi-p value? interrupt. 1 ? enable the ?new rdi-p value? interrupt.
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 392 table 264: receive sonet path ? sonet receive path interrupt enable ? byte 0 (address location= 0xn18f, where n ranges in value from 0x02 to 0x04) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 detection of b3 byte error interrupt enable detection of new pointer interrupt enable detection of unknown pointer interrupt enable detection of pointer decrement interrupt enable detection of pointer increment interrupt enable detection of ndf pointer interrupt enable change of lop-p defect condition interrupt enable change of ais-p defect condition interrupt enable r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 detection of b3 byte error interrupt enable r/w detection of b3 byte error interrupt enable: this read/write bit-field permits the user to either enable or disable the ?detection of b3 byte error? interrupt. if the user enables this interrupt, then the receive sonet poh processor block will g enerate an interrupt anytime it detects a b3-byte error in the incoming sts-1 data-stream. 0 ? disables the ?detection of b3 byte e rror? interrupt. 1 ? enables the ?detection of b3 byte error? interrupt. 6 detection of new pointer interrupt enable r/w detection of new pointer interrupt enable: this read/write bit-field permits the user to either enable or disable the ?detection of new pointer? interrupt. if the user enables this interrupt, then the receive sonet poh processor block will g enerate an interrupt anytime it detects a new pointer value in the incoming sts-1 frame. note: pointer adjustments with ndf will not generate this interrupt. 0 ? disables the ?detection of new pointer? interrupt. 1 ? enables the ?detection of new pointer? interrupt. 5 detection of unknown pointer interrupt enable r/w detection of unknown pointer interrupt enable: this read/write bit-field permits the user to either enable or disable the ?detection of unknown pointer? interrupt. if the user enables this interrupt, then the receive sonet poh processor block will g enerate an interrupt anytime it detects a ?pointer adjustment? that does not fit into any of the following categories. ? an increment pointer. ? a decrement pointer ? an ndf pointer ? ais pointer ? new pointer. 0 ? disables the ?detection of unknown pointer? interrupt. 1 ? enables the ?detection of unknown pointer? interrupt. 4 detection of pointer decrement interrupt enable r/w detection of pointer decr ement interrupt enable: this read/write bit-field permits the user to enable or disable the ?detection of pointer decrement? interrupt. if the user enables this interrupt, then the receive sonet poh processor block will generate an interrupt anytime it detects a ?pointer-decrement? event. 0 ? disables the ?detection of pointer decrement? interrupt.
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 393 1 ? enables the ?detection of pointer decrement? interrupt. 3 detection of pointer increment interrupt enable r/w detection of pointer increment interrupt enable: this read/write bit-field permits the user to either enable or disable the ?detection of pointer increment? interrupt. if the user enables this interrupt, then the receive sonet poh processor block will g enerate an interrupt anytime it detects a ?pointer increment? event. 0 ? disables the ?detection of pointer increment? interrupt. 1 ? enables the ?detection of pointer increment? interrupt. 2 detection of ndf pointer interrupt enable r/w detection of ndf pointer interrupt enable: this read/write bit-field permits the user to either enable or disable the ?detection of ndf pointer? interrupt. if the user enables this interrupt, then the receive sonet poh processor block will generate an interrupt anytime it detects an ndf pointer event. 0 ? disables the ?detection of ndf pointer? interrupt. 1 ? enables the ?detection of ndf pointer? interrupt. 1 change of lop-p defect condition interrupt enable r/w change of lop-p defect condition interrupt enable: this read/write bit-field permits the user to either enable or disable the ?change in lop (loss of pointer)? defect conditi on interrupt. if the user enables this interrupt, then the receive sonet poh pr ocessor will generate an interrupt in response to either of the following events. ? whenever the receive sonet poh pr ocessor block declares the lop-p defect condition. ? whenever the receive sonet poh proce ssor block clears the lop-p defect condition. 0 ? disable the ?change of lop-p defect condition? interrupt. 1 ? enables the ?change of lop-p defect condition? interrupt. note: the user can determine if the rece ive sonet poh processor block is currently declaring the lop-p defect co ndition by reading out the contents of bit 1 (lop-p defect declared) within the ?receive sts-1 path ? sonet receive poh status ? byte 0? (address location= 0xn187). 0 change of ais-p defect condition interrupt enable r/w change of ais-p defect condition interrupt enable: this read/write bit-field permits the user to either enable or disable the ?change of ais-p (path ais)? defect condition inte rrupt. if the user enables this interrupt, then the receive sonet poh processor bl ock will generate an interrupt in response to either of the following events. ? whenever the receive sonet poh processor block declares the ?ais-p? defect condition. ? whenever the receive sonet poh processor block clears the ?ais-p? defect condition. 0 ? disables the ?change of ais-p defect condition? interrupt. 1 ? enables the ?change of ais-p defect condition? interrupt. note: the user can determine if the rece ive sonet poh processor block is currently declaring the ais-p defect co ndition by reading out the contents of bit 0 (ais-p defect declared) within the ?receive sonet path ? sonet receive poh status ? byte 0? (address location= 0xn187).
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 394 table 265: receive sonet path ? sonet receive rdi-p register (address location= 0xn193, where n ranges in value from 0x05 to 0x07) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 unused rdi-p_accept[2:0] rdi-p threshold[3:0] r/o r/o r/o r/o r/w r/w r/w r/w 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 unused r/o 6 ? 4 rdi-p_accept[2:0] r/o accepted rdi-p value: these read-only bit-fields contain the rdi-p (e.g., bits 5, 6 and 7 within the g1 byte) value that has been most recently accepted by the receive sonet poh processor block. note: a given rdi-p value will be ?accepted? by the receive sonet poh processor block, if this rdi-p value has been consistently received in ?rdi-p threshold[3:0]? number of sonet frames. 3 ? 0 rdi-p threshold[3:0] r/w rdi-p threshold[3:0]: these read/write bit-fields permit the user to defined the ?rdi-p acceptance threshold? for the receive sonet poh processor block. the ?rdi-p acceptance threshold? is the number of consecutive sonet frames, in which the receive sonet poh processor block must receive a given rdi-p value, bef ore it ?accepts? or ?validates? it. the most recently ?accepted? rdi-p value is written into the ?rdi-p accept[2:0]? bit-fields, within this register.
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 395 table 266: receive sonet path ? received path label value (address location= = 0xn196, where n ranges in value from 0x02 to 0x04) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 received_c2_byte_value[7:0] r/o r/o r/o r/o r/o r/o r/o r/o 1 1 1 1 1 1 1 1 b it n umber n ame t ype d escription 7 ? 0 received c2 byte value[7:0] r/o received ?filtered? c2 byte value: these read-only bit-fields contain the value of the most recently ?accepted? c2 byte, via the receive sonet poh processor block. the receive sonet poh processor block will ?accept? a c2 byte value (and load it into these bit-fields) if it has received a consistent c2 byte, in five (5) consecutive sonet frames. note: the receive sonet poh processor block uses this register, along the ?receive sonet path ? expected path label value? register (address location= 0xn197), when declaring or clearing the uneq-p and plm-p defect conditions.
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 396 table 267: receive sonet path ? expected path label value (address location= 0xn197, where n ranges in value from 0x02 to 0x04) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 expected_c2_byte_value[7:0] r/w r/w r/w r/w r/w r/w r/w r/w 1 1 1 1 1 1 1 1 b it n umber n ame t ype d escription 7 ? 0 expected c2 byte value[7:0] r/w expected c2 byte value: these read/write bit-fields permits the user to specify the c2 (path label byte) value, that the receive sonet poh processor block should expect when declaring or clearing the uneq-p and plm-p defect conditions. if the contents of the ?received c2 byte value[7:0]? (see ?receive sonet path ? received path label value? register) matches the contents in these register, then the receive sonet poh will not declare the plm-p nor the uneq-p defect conditions. table 268: receive sonet path ? b3 byte error count register ? byte 3 (address location= 0xn198, where n ranges in value from 0x02 to 0x04) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 b3_byte_error_count[31:24] rur rur rur rur rur rur rur rur 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 ? 0 b3_byte_error_count[31:24] rur b3 byte error count ? msb: this reset-upon-read register, along with ?receive sonet path ? b3 byte error count register ? bytes 2 through 0; function as a 32 bit counter, which is incremented anytime the receive sonet poh processor block detects a b3 byte error. note: 1. if the receive sonet poh proc essor block is configured to count b3 byte errors on a ?per-bit? basis, then it will increment this 32 bit counter by the number of bits, within the b3 byte (of each incoming sts-1 spe) that are in error. 2. if the receive sonet poh proc essor block is configured to count b3 byte errors on a ?per-f rame? basis, then it will increment this 32 bit counter each time that it receives an sts-1 spe that contains an erred b3 byte.
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 397 table 269: receive sonet path ? b3 byte error count register ? byte 2 (address location= 0xn199, where n ranges in value from 0x02 to 0x04) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 b3_byte_error_count[23:16] rur rur rur rur rur rur rur rur 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 ? 0 b3_byte_error_count[23:16] rur b3 byte error count (bits 23 through 16): this reset-upon-read register, along with ?receive sonet path ? b3 byte error count register ? bytes 3, 1 and 0; function as a 32 bit counter, which is incremented anytime the receive sonet poh processor block detects a b3 byte error. note: 1. if the receive sonet poh processor block is configured to count b3 byte errors on a ?per-bit? basis, then it will increment this 32 bit counter by the number of bits, within the b3 byte (of each incoming sts-1 spe) that are in error. 2. if the receive sonet poh processor block is configured to count b3 byte errors on a ?per-f rame? basis, then it will increment this 32 bit counter each time that it receives an sts-1 spe that contains an erred b3 byte.
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 398 table 270: receive sonet path ? b3 byte error c ount register ? byte 1 (address location= 0xn19a, where n ranges in value from 0x02 to 0x04) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 b3_byte_error_count[15:8] rur rur rur rur rur rur rur rur 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 ? 0 b3_byte_error_count[15:8] rur b3 byte error count ? (bits 15 through 8): this reset-upon-read register, along with ?receive sonet path ? b3 byte error count register ? bytes 3, 2 and 0; function as a 32 bit counter, which is increment ed anytime the receive sonet poh processor block detects a b3 byte error. note: 1. if the receive sonet poh processo r block is configured to count b3 byte errors on a ?per-bit? basis, then it will increment this 32 bit counter by the number of bits, with in the b3 byte (of each incoming sts-1 spe) that are in error. 2. if the receive sonet poh processo r block is configured to count b3 byte errors on a ?per-frame? basis, then it will increment this 32 bit counter each time that it receives an sts-1 spe that contains an erred b3 byte.
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 399 table 271: receive sonet path ? b3 byte error c ount register ? byte 0 (address location= 0xn19b, where n ranges in value from 0x02 to 0x04) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 b3_byte_error_count[7:0] rur rur rur rur rur rur rur rur 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 ? 0 b3_byte_error_count[7:0] rur b3 byte error count ? lsb: this reset-upon-read register, along with ?receive sonet path ? b3 byte error count register ? bytes 3 through 1; function as a 32 bit counter, which is incremented anytime the receive sonet poh processor block detects a b3 byte error. note: 1. if the receive sonet poh proces sor block is configured to count b3 byte errors on a ?per-bit? basis, then it will increment this 32 bit counter by the number of bits, with in the b3 byte (of each incoming sts-1 spe) that are in error. 2. if the receive sonet poh proces sor block is configured to count b3 byte errors on a ?per-frame? basis, then it will increment this 32 bit counter each time that it receiv es an sts-1 spe that contains an erred b3 byte.
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 400 table 272: receive sonet path ? rei-p event count register ? byte 3 (address location= 0xn19c, where n ranges in value from 0x02 to 0x04) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 rei-p_event_count[31:24] rur rur rur rur rur rur rur rur 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 ? 0 rei-p event_count[31:24] rur rei-p event count ? msb: this reset-upon-read register, along with ?receive sonet path ? rei-p event count register ? bytes 2 through 0; function as a 32 bit counter, which is incremented anytime the receive sonet poh processor block detects a path ? remote error indicator event within the incoming sts-1 spe data-stream. note: 1. if the receive sonet poh proc essor block is configured to count rei-p events on a ?per-bit? bas is, then it will increment this 32-bit counter by the nibble-value within the rei-p field of the incoming g1 byte within each incoming sts-1 spe. 2. if the receive sonet poh proc essor block is configured to count rei-p events on a ?per-frame? basis, then it will increment this 32-bit counter each time that it receives an sts-1 spe that contains a ?non-zero? rei-p value.
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 401 table 273: receive sonet path ? rei-p event count register ? byte 2 (address location= 0xn19d, where n ranges in value from 0x02 to 0x04) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 rei-p_event_count[23:16] rur rur rur rur rur rur rur rur 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 ? 0 rei-p event_count[23:16] rur rei-p event count (bits 23 through 16): this reset-upon-read register, along with ?receive sonet path ? rei-p event count register ? bytes 3, 1 and 0; function as a 32 bit counter, which is incremented anytime the receive sonet poh processor block detects a path ? remote error indicator event within the incoming sts-1 spe data-stream. note: notes: 1. if the receive sonet poh processor block is configured to count rei-p events on a ?per-bit? basis, then it will increment this 32-bit counter by the nibble-value within the rei-p field of the incoming g1 byte within each incoming sts-1 frame. 2. if the receive sonet poh pr ocessor block is configured to count rei-p events on a ?per-frame ? basis, then it will increment this 32-bit counter each tiem that it receives an sts-1 spe that contains a ?non-zero? rei-p value.
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 402 table 274: receive sonet path ? rei-p event count register ? byte 1 (address location=0xn19e, where n ranges in value from 0x02 to 0x04) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 rei-p_event_count[15:8] rur rur rur rur rur rur rur rur 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 ? 0 rei-p event_count[15:8] rur rei-p event count ? (bits 15 through 8) this reset-upon-read register, along with ?receive sonet path ? rei-p event count register ? bytes 3, 2 and 0; function as a 32 bit counter, which is incremented anytime the receive sonet poh processor block detects a path ?remote error indicator event within the incoming sts-1 spe data-stream. note: 1. if the receive sonet poh proc essor block is configured to count rei-p events on a ?per-bit? bas is, then it will increment this 32-bit counter by the nibble-value within the rei-p field of the incoming g1 byte within each incoming sts-1 spe. 2. if the receive sonet poh pr ocessor block is configured to count rei-p events on a ?per-frame ? basis, then it will increment this 32-bit counter each time that it receives an sts-1 spe that contains a non-zero rei-p value.
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 403 table 275: receive sonet path ? rei-p event count register ? byte 0 (address location= 0xn19f, where n ranges in value from 0x02 to 0x04) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 rei-p_event_count[7:0] rur rur rur rur rur rur rur rur 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 ? 0 rei-p event_count[7:0] rur rei-p event count ? lsb: this reset-upon-read register, along with ?receive sonet path ? rei-p event count register ? bytes 3 through 1; function as a 32 bit counter, which is incremented anytime the receive sonet poh processor block detects a path ? remote error indicator event within the incoming sts-1 spe data-stream. note: 1. if the receive sonet poh proce ssor block is configured to count rei-p events on a ?per-bit? basis, then it will increment this 32-bit counter by the nibble-value within the rei-p field of the incoming g1 byte within each incoming sts-1 frame. 2. if the receive sonet poh proce ssor block is configured to count rei-p events on a ?per-frame? basis, then it will increment this 32-bit counter each time that it receives an sts-1 spe that contains a ?non- zero? rei-p value.
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 404 table 276: receive sonet path ? receive path trace message buffer control register (address location=0xn1a3, where n ranges in value from 0x02 to 0x04) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 unused receive path trace message buffer read select receive path trace message accept threshold path trace message alignment message type receive path trace message length[1:0] r/o r/o r/o r/w r/w r/w r/o r/o 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 ? 5 unused r/o 4 received path trace message buffer read select r/w receive path trace message buffer read selection: this read/write bit-field permits a user to specify which of the following receive path trace me ssage buffer segments that the microprocessor will read out, whenever it reads out the contents of the receive path trace message buffer. m. the ?actual? receive path trace message buffer. the ?actual? receive path trace message buffer contains the contents of t he most recently received (and accepted) path trace message via the incoming sts-1 data-stream. n. the ?expected? receive path trace message buffer. the ?expected? receive path trace message buffer contains the contents of t he path trace message that the user ?expects? to receive from the remote pte. the contents of particular buffer are usually specified by the user. 0 ? executing a read to the receive path trace message buffer, will return the contents within the ?actual? receive path trace message? buffer. 1 ? executing a read to the receive path trace message buffer will return the contents with in the ?expected receive path trace message buffer?. note: in the case of the receive sonet poh processor block, the ?receive path trace message buffer? is located at address location 0xn500 through 0xn53f, where n ranges in value from 0x02 to 0x04. 3 path trace message accept threshold r/w path trace message accept threshold: this read/write bit-field permits a user to select the number of consecutive times that th e receive sonet poh processor block must receive a given receive path trace message, before it is accepted and loaded into t he ?actual? receive path trace message buffer, as described below. 0 ? configures the receive sonet poh processor block to accept the incoming path trace message after it has received it the third time in succession. 1 ? configures the receive sonet poh processor block to acce p t the incomin g path trace messa g e after it has received in
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 405 the fifth time in succession. 2 path trace message alignment type r/o path trace message alignment type: this read/write bit-field permits a user to specify how the receive sonet poh processor block will locate the boundary of the incoming path trace message (within the incoming sts-1 data-stream), as indicated below. 0 ? configures the receive sonet poh processor block to expect the path trace message boundary to be denoted by a ?line feed? character. 1 ? configures the receive sonet poh processor block to expect the path trace message boundary to be denoted by the presence of a ?1? in the msb (most significant byte) of the very first byte (within the incoming path trace message). in this caes, all of the remaining bytes (within the incoming path trace message) will each have a ?0? within their msbs. 1 ? 0 receive path trace message length[1:0] r/w receive path trace message length[1:0]: these read/write bit-fields permit the user to specify the length of the receive path trace message that the receive sonet poh processor block will accept and load into the ?actual? receive path trace message buffer. the relationship between the content of these bit-fields and the corresponding receive path trace message length is presented below. receive path trace message length[1:0] resulting path trace message length (in terms of bytes) 00 1 byte 01 16 bytes 10/11 64 bytes
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 406 table 277: receive sonet path ? pointer value ? byte 1 (address location= 0xn1a6, where n ranges in value from 0x02 to 0x04) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 unused current_pointer value msb[9:8] r/o r/o r/o r/o r/o r/o r/o r/o 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 - 2 unused r/o 1 ? 0 current_pointer_value_msb[1:0] r/o current pointer value ? msb: these read-only bit-fields, along with that from the ?receive sonet path ? pointer value ? byte 0? register combine to reflect the current value of the pointer that the ?receive sonet poh processor? block is using to locate the spe within the incoming sonet data stream. note: these register bits comprise the two-most significant bits of the pointer value. table 278: receive sonet path ? pointer value ? byte 0 (address location=0xn1a7, where n ranges in value from 0x02 to 0x04) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 current_pointer_value_lsb[7:0] r/o r/o r/o r/o r/o r/o r/o r/o 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 ? 0 current_pointer_value_lsb[7:0] r/o current pointer value ? lsb: these read-only bit-fields, along with that from the ?receive sonet path ? pointer value ? byte 1? register combine to reflect the current value of the pointer that the ?receive sonet poh processor? block is using to locate the spe within the incoming sonet data stream. note: these register bits comprise the lower byte value of the pointer value.
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 407 table 279: receive sonet path ? auto ais control register (address location= 0xn1bb, where n ranges in value from 0x02 to 0x04) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 unused transmit ais-p (down- stream) upon c2 byte unstable transmit ais-p (down- stream) upon uneq-p transmit ais-p (down- stream) upon plm- p transmit ais-p (down- stream) upon path trace message unstable transmit ais-p (down- stream) upon tim-p transmit ais-p (down- stream) upon lop-p transmit ais-p (down- stream) enable r/o r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 unused r/o 6 transmit ais-p (downstream) upon c2 byte unstable r/w transmit path ais (downstream, towards the corresponding transmit sts-1 poh processor or ds3/e3 mapper block) upon declaration of the unstable c2 byte defect condition: this read/write bit-field permits the user to configure the receive sonet poh processor block to automatic ally transmit the path ais (ais- p) indicator via the ?downstream? tra ffic (e.g., towards the corresponding transmit sts-1 poh processor or ds3/ e3 mapper blocks), anytime (and for the duration that) it declares t he unstable c2 byte defect condition within the ?incoming? sts-1 data-stream. 0 ? does not configure the receiv e sonet poh processor block to automatically transmit the ais-p indicator (via the ?downstream? traffic, towards the corresponding transmit sts-1 poh processor or ds3/e3 mapper block) whenever it declares the ?unstable c2 byte? defect condition. 1 ? configures the receive sonet poh processor block to automatically transmit the ais-p indica tor (via the ?downstrea m? traffic, towards the corresponding transmit sts-1 poh proc essor or ds3/e3 mapper block) whenever (and for the duration that) it declares the ?unstable c2 byte? defect condition. note: the user must also set bit 0 (transmit ais-p enable) to ?1? to configure the receive sonet poh processor block to automatically transmit the ais-p indicator, in response to this defect condition. 5 transmit ais-p (downstream) upon uneq-p r/w transmit path ais (downstream, towards the corresponding transmit sts-1 poh processor or ds3/e3 ma pper blocks) upon declaration of the uneq-p (path ? unequipped) defect condition: this read/write bit-field permits the user to configure the receive sonet poh processor block to automatic ally transmit the path ais (ais- p) indicator via the ?downstream? tra ffic (e.g., towards the corresponding transmit sts-1 poh processor or ds3/e3 mapper block), anytime (and for the duration that) it declare s the uneq-p defect condition. 0 ? does not configure the receiv e sonet poh processor block to automatically transmit the ais-p indicator (via the ?downstream? traffic, towards the corresponding transmit sts-1 poh processor or ds3/e3 mapper block) whenever it declares the uneq-p defect condition. 1 ? configures the receive sonet poh processor block to automatically transmit the ai s-p indicator ( via the ?downstream? traffic, towards the
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 408 corresponding transmit sts-1 poh proc essor or ds3/e3 mapper block) whenever (and for the duration t hat) it declares the uneq-p defect condition. note: the user must also set bit 0 (transmit ais-p enable) to ?1? to configure the receive sonet poh processor block to automatically transmit the ais-p indicator, in response to this defect condition. 4 transmit ais-p (downstream) upon plm-p r/w transmit path ais (downstream, towards the corresponding transmit sts-1 poh processor or ds3/e3 mapper block) upon declaration of plm-p (path ? payload label mismatch) defect condition: this read/write bit-field permits the user to configure the receive sonet poh processor block to automatic ally transmit the path ais (ais- p) indicator via the ?downstream? tra ffic (e.g., towards the corresponding transmit sts-1 poh processor or ds3/e3 mapper block), anytime (and for the duration that) it decla res the plm-p defect condition. 0 ? does not configure the receiv e sonet poh processor block to automatically transmit the ais-p indicator (via the ?downstream? traffic, towards the corresponding transmit sts-1 poh processor or ds3/e3 mapper block) whenever it decla res the plm-p defect condition. 1 ? configures the receive sonet poh processor block to automatically transmit the ais-p indica tor (via the ?downstrea m? traffic, towards the corresponding transmit sts-1 poh proc essor or ds3/e3 mapper block) whenever (and for the duration that) it declares the plm-p defect condition. note: the user must also set bit 0 (transmit ais-p enable) to ?1? to configure the receive sonet poh processor block to automatically transmit the ais-p indicator, in response to this defect condition. 3 transmit ais-p (downstream) upon path trace message unstable r/w transmit path ais (downstream, towards the corresponding transmit sts-1 poh processor or ds3/e3 mapper block) upon declaration of the path trace message unst able defect condition: this read/write bit-field permits the user to configure the receive sonet poh processor block to automatic ally transmit the path ais (ais- p) indicator via the ?downstream? tra ffic (e.g., towards the corresponding transmit sts-1 poh processor or ds3/e3 mapper block), anytime (and for the duration that) it declares the path trace message unstable defect condition within the ?inc oming? sts-1 data-stream. 0 ? does not configure the receiv e sonet poh processor block to automatically transmit the ais-p indicator (via the ?downstream? traffic, towards the corresponding transmit sts-1 poh processor or ds3/e3 mapper block) whenever (and for the duration that) it declares the path trace message unstable defect condition within the ?incoming? sts-1 data-stream. 1 ? configures the receive sonet poh processor block to automatically automatically transmit the ais-p indicator (via the ?downstream? traffic, towards the corresponding transmit sts-1 poh processor or ds3/e3 mapper block) whenever (and for the duration that) it declares the path trace message unstable defect condition. note: the user must also set bit 0 (transmit ais-p enable) to ?1? to configure the receive sonet poh processor block to automatically transmit the ais-p indicator, in response to this defect condition. 2 transmit ais-p (downstream) upon tim-p r/w transmit path ais (downstream towards the corresponding transmit sts-1 poh processor or ds3/e3 mapper block) upon declaration o the tim-p (path trace identification message mismatch) defect condition:
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 409 this read/write bit-field permits the user to configure the receive sonet poh processor block to automatic ally transmit the path ais (ais- p) indicator via the ?downstream? tra ffic (e.g., towards the corresponding transmit sts-1 poh processor or ds3/e3 mapper block), anytime (and for the duration that) it declares th e tim-p defect condition within the incoming sts-1 data-stream. 0 ? does not configure the receiv e sonet poh processor block to automatically transmit the ais-p indicator (via the ?downstream? traffic towards the corresponding transmit sts-1 poh processor or ds3/e3 mapper block) whenever it decla res the tim-p defect condition. 1 ? configures the receive sonet poh processor block to automatically transmit the ais-p indica tor (via the ?downstrea m? traffic, towards the corresponding transmit sts-1 poh proc essor or ds3/e3 mapper block) whenever (and for the duration that) it declares the tim-p defect condition. note: the user must also set bit 0 (transmit ais-p enable) to ?1? to configure the receive sonet poh processor block to automatically transmit the ais-p indicator, in response to this defect condition. 1 transmit ais-p (downstream) upon lop-p r/w transmit path ais (downstream, towards the corresponding transmit sts-1 poh processor or ds3/e3 mapper block) upon declaration of the loss of pointer (lop-p) defect condition: this read/write bit-field permits the user to configure the receive sonet poh processor block to automatic ally transmit the path ais (ais- p) indicator via the ?downstream? tra ffic (e.g., towards the corresponding transmit sts-1 poh processor or ds3/e3 mapper block), anytime (and for the duration that) it declares t he lop-p defect condition within the incoming sts-1 data-stream. 0 ? does not configure the receiv e sonet poh processor block to automatically transmit the ais-p indicator (via the ?downstream? traffic, towards the corresponding transmit sts-1 poh processor or ds3/e3 mapper block) whenever it decla res the lop-p defect condition. 1 ? configures the receive sonet poh processor block to automatically transmit the ais-p indica tor (via the ?downstrea m? traffic, towards the corresponding transmit sts-1 poh processor or ds3/e3 mapper block)) whenever (and for the duration that) it declares the lop-p defect condition. note: the user must also set bit 0 (transmit ais-p enable) to ?1? to configure the receive sonet poh processor block to automatically transmit the ais-p indicator, in response to this defect condition. 0 transmit ais-p (downstream) enable r/w automatic transmission of ais-p enable: this read/write bit-field serves two purposes. it permits the user to configure t he receive sonet poh processor block to automatically transmit the path ais (ais-p) indicator, via the down- stream traffic (e.g., towards the corresponding transmit sts-1 poh processor or ds3/e3 mapper block), upon declaration of either the uneq- p, plm-p, tim-p, lop-p or the path trace message unstable defect conditions. it also permits the user to configure the receive sonet poh processor block to automatically transmit a path (ais-p) indicator via the ?downstream? traffic (e.g ., towards the corresponding transmit sts-1 poh processor or ds3/e3 mapper block) anytime (and for the duration that) it declares the ais-p defect condition within the ?incoming ? sts-1 data- stream. 0 ? configures the receive sone t poh processor block to not automatically transmit the ais-p indicator (via the ?downstream? traffic, towards the corres p ondin g transmit sts-1 poh processor or ds3/e3
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 410 mapper block) whenever it declares any of the ?above-mentioned? defect conditions. 1 ? configures the receive sonet poh processor block to automatically transmit the ais-p indica tor (via the ?downstrea m? traffic, towards the corresponding transmit sts-1 poh proc essor or ds3/e3 mapp;er block) whenver (and for the duration that) it declares any of the ?above- mentioned? condition. note: the user must also set the corresponding bit-fields (within this register) to ?1? in order to configure the receive sonet poh processor block to automatically transmit the ais-p indicator upon detection of a giv en alarm/defect condition.
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 411 table 280: receive sonet path ? serial port control register (address location= 0xn1bf) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 unused rxpoh_clock_speed[7:0] r/o r/o r/o r/o r/w r/w r/w r/w 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 - 4 unused r/o 3 - 0 rxpoh_clock_speed[7:0] r/w rxpohclk output clock signal speed: these read/write bit-fields permit the user to specify the frequency of the ?rxpohclk output clock signal. the formula that relates the contents of these register bits to the ?rxpohclk? frequency is presented below. freq = 19.44 /[2 * (r xpoh_clock_speed + 1) notes: for sts-3/stm-1 applications, the frequency of the rxpohclk output signal must be in the range of 0.304mhz to 9.72mhz
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 412 table 281: receive sonet path ? sonet receive au to alarm register ? byte 0 (address location= 0xn1c3, where n ranges in value from 0x02 to 0x04) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 transmit ais-p or ds3/e3 ais (via downstream sts-1s or ds3/e3s) upon lop-p unused transmit ais-p or ds3/e3 ais (via downstream sts-1s or ds3/e3s) upon plm-p unused transmit ais-p or ds3/e3 ais (via downstream sts-1s or ds3/e3s) upon uneq-p transmit ais-p or ds3/e3 ais (via downstream sts-1s or ds3/e3s) upon tim-p transmit ais-p or ds3/e3 ais (via downstream sts-1s or ds3/e3s) upon ais-p transmit ds3 ais (via downstream ds3/e3) upon pdi-p r/w r/o r/w r/o r/w r/w r/w r/w 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 transmit ais-p or ds3/e3 ais (via downstream sts- 1s or ds3/e3s) upon lop- p r/w transmit ais-p or ds3/e3 ais (via downstream sts-1s or ds3/e3 signals) upon declaration of the lop-p defect condition: the exact function of this register bit-field depends upon whether the channel has been configured to operate in the sts-1 or ds3/e3 mode, as described below. if the channel has been configured to operate in the sts-1 mode: this read/write bit-field permits the user to configure the transmit sts-1 poh processor block (within the corresponding channel) to automatically transmit t he ais-p (path ais) indicator via the ?downstream? sts-1 signal, anyt ime (and for the duration that) the receive sonet poh processor block declares the lop-p defect condition. if the channel has been configured to operate in the ds3/e3 mode: this read/write bit-field permits the user to configure the ds3/e3 framer block (within the corresponding channel) to automatically transmit the ds3/e3 ais indicator via the ?downstream? ds3/e3 signal, anytime (and for the durati on that) the receive sonet poh processor block declares t he lop-p defect condition. 0 ? does not configure the corresponding transmit sts-1 poh processor (or ds3/e3 framer) block to automatically transmit the ais-p (or ds3/e3 ais) indicator via the ?downstream? sts-1 (or ds3/e3) signal, anytime the receive sonet poh processor block declares the lop-p defect condition. 1 ? configures the corresponding transmit sts-1 poh processor (or ds3/e3 framer) block to autom atically transmit the ais-p (or ds3/e3 ais) indicator via the ?downstream? sts-1 (or ds3/e3) signal, anytime (and for the durati on that) the receive sonet poh processor block declares t he lop-p defect condition. 6 unused r/o 5 transmit ais-p or ds3/e3 ais (via downstream sts- 1s or ds3/e3s) upon plm- p r/w transmit ais-p or ds3/e3 ais (via downstream sts-1s or ds3/e3 signals) upon declaration of the plm-p defect condition: the exact function of this re g ister bit-field de p ends u p on whether the
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 413 channel has been configured to operate in the sts-1 or ds3/e3 mode, as described below. if the channel has been configured to operate in the sts-1 mode: this read/write bit-field permits the user to configure the transmit sts-1 poh processor block (within the corresponding channel) to automatically transmit t he ais-p (path ais) indicator via the ?downstream? sts-1 signal, anyt ime (and for the duration that) the receive sonet poh processor block declares the plm-p defect condition. if the channel has been configured to operate in the ds3/e3 mode: this read/write bit-field permits the user to configure the ds3/e3 framer block (within the corresponding channel) to automatically transmit the ds3/e3 ais indicator via the ?downstream? ds3/e3 signal, anytime (and for the durati on that) the receive sonet poh processor block declares the plm-p defect condition. 0 ? does not configure the corresponding transmit sts-1 poh processor (or ds3/e3 framer) bloc k to automatically transmit the ais-p (or ds3/e3 ais) indicator via the ?downstream? sts-1 (or ds3/e3) signals, anytime the receive sonet poh processor block declares the plm-p defect condition. 1 ? configures the corresponding transmit sts-1 poh processor (or ds3/e3 framer) block to autom atically transmit the ais-p (or ds3/e3 ais) indicator via the ?downstream? sts-1 (or ds3/e3) signal, anytime (and for the durati on that) the receive sonet poh processor block declares the plm-p defect condition. 4 unused r/o 3 transmit ais-p or ds3/e3 ais (via downstream sts- 1s or ds3/e3s) upon uneq-p r/w transmit ais-p or ds3/e3 ais (via downstream sts-1s or ds3/e3 signals) upon declaration of the uneq-p defect condition: the exact function of this register bit-field depends upon whether the channel has been configured to operate in the sts-1 or ds3/e3 mode, as described below. if the channel has been configured to operate in the sts-1 mode: this read/write bit-field permits the user to configure the transmit sts-1 poh processor block (within the corresponding channel) to automatically transmit t he ais-p (path ais) indicator via the ?downstream? sts-1 signal, anyt ime (and for the duration that) the receive sonet poh processor block declares the uneq-p defect condition. if the channel has been configured to operate in the ds3/e3 mode: this read/write bit-field permits the user to configure the ds3/e3 framer block (within the corresponding channel) to automatically transmit the ds3/e3 ais indicator via the ?downstream? ds3/e3 signal, anytime (and for the durati on that) the receive sonet poh processor block declares the uneq-p defect condition. 0 ? does not configure the corresponding transmit sts-1 poh processor (or ds3/e3 framer) bloc k to automatically transmit the ais-p (or ds3/e3 ais) indicator via the ?downstream? sts-1 (or ds3/e3) signal, anytime the receive sonet poh processor block declares the uneq-p defect condition.
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 414 1 ? configures the corresponding transmit sts-1 poh processor (or ds3/e3 framer) block to autom atically transmit the ais-p (or ds3/e3 ais) indicator via the ?downstream? sts-1 (or ds3/e3) signal, anytime (and for the durati on that) the receive sonet poh processor block declares the uneq-p defect condition. 2 transmit ais-p or ds3/e3 (via downstream sts-1s) upon tim-p r/w transmit ais-p or ds3/e3 ais (via downstream sts-1s or ds3/e3 signals) upon declaration of the tim-p defect condition: the exact function of this register bit-field depends upon whether the channel has been configured to operate in the sts-1 or ds3/e3 mode, as described below. if the channel has been configured to operate in the sts-1 mode: this read/write bit-field permits the user to configure the transmit sts-1 poh processor block (within the corresponding channel) to automatically transmit t he ais-p (path ais) indicator via the ?downstream? sts-1 signal, anyt ime (and for the duration that) the receive sonet poh processor block declares the tim-p defect condition. if the channel has been configured to operate in the ds3/e3 mode: this read/write bit-field permits the user to configure the ds3/e3 framer block (within the corresponding channel) to automatically transmit the ds3/e3 ais indicator via the ?downstream? ds3/e3 signal, anytime (and for the durati on that) the receive sonet poh processor block declares the tim-p defect condition. 0 ? does not configure the corresponding transmit sts-1 poh processor (or ds3/e3 framer) block to automatically transmit the ais-p (or ds3/e3 ais) indicator via the ?downstream? sts-1 (or ds3/e3) signals, anytime the receive sonet poh processor block declares the tim-p defect condition. 1 ? configures the corresponding transmit sts-1 poh processor (or ds3/e3 framer) block to autom atically transmit the ais-p (or ds3/e3 ais) indicator via the ?downstream? sts-1 (or ds3/e3) signal, anytime (and for the durati on that) the receive sonet poh processor block declares the tim-p defect condition. 1 transmit ais-p or ds3/e3 ais (via downstream sts- 1s or ds3/e3s) upon ais- p r/w transmit ais-p or ds3/e3 ais (via downstream sts-1s or ds3/e3 signals) upon declaration of the ais-p defect condition: the exact function of this register bit-field depends upon whether the channel has been configured to operate in the sts-1 or ds3/e3 mode, as described below. if the channel has been configured to operate in the sts-1 mode: this read/write bit-field permits the user to configure the transmit sts-1 poh processor block (within the corresponding channel) to automatically transmit t he ais-p (path ais) indicator via the ?downstream? sts-1 signal, anyt ime (and for the duration that) the receive sonet poh processo r block declares the ais-p defect condition. if the channel has been configured to operate in the ds3/e3 mode: this read/write bit-field permits the user to configure the ds3/e3 framer block (within the corresponding channel) to automatically transmit the ds3/e3 ais indicator via the ?downstream? ds3/e3 si g nal, an y time ( and for the duration that ) the receive sonet poh
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 415 processor block declares t he ais-p defect condition. 0 ? does not configure the corresponding transmit sts-1 poh processor (or ds3/e3 framer) bloc k to automatically transmit the ais-p (or ds3/e3 ais) indicator via the ?downstream? sts-1 (or ds3/e3) signals, anytime the receive sonet poh processor block declares the ais-p defect condition. 1 ? configures the corresponding transmit sts-1 poh processor (or ds3/e3 framer) block to autom atically transmit the ais-p (or ds3/e3 ais) indicator via the ?downstream? sts-1 (or ds3/e3) signal, anytime (and for the durati on that) the receive sonet poh processor block declares t he ais-p defect condition. 0 transmit ds3 ais (via downstream ds3s) upon pdi-p r/w transmit ds3 ais upon pdi-p or ais-p: this read/write bit-field permits the user to configure the receive sonet poh processor block to automatically command the ds3/e3 framer block to transmi t an ais signal (to downstream circuitry) whenever it (the re ceive sonet poh processor block) detects an async pdi-p or an ais-p condition, in the incoming sts- 1 spe data-stream. 0 ? configures the receive sone t poh processor block to not command the ds3/e3 framer block to automatically transmit an ais signal upon detection of an ais-p or a pdi-p condition. 1 ? configures the receive sonet poh processor block to command the ds3/e3 framer block to automatically transmit an ais signal upon detection of an ais-p or pdi-p. note: note: this register bit is only valid if the incoming sts-1 signal is transporting an asynchronous ds3 signal; and if the corresponding channel is configured to operate in the ds3 mode. when an asynchronous ds3 signal is being transported by a sonet signal, the pdi-p condition is indicated by setting the c2 byte to the value ?0xfc?.
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 416 table 282: receive sonet path ? receive j1 byte capture register (address location= 0xn1d3, where n ranges in value from 0x02 to 0x04) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 j1_byte_captur ed_value[7:0] r/o r/o r/o r/o r/o r/o r/o r/o 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 ? 0 j1_byte_captured_value[7:0] r/o j1 byte captured value[7:0] these read-only bit-fields contain the value of the j1 byte, within the most recently received sonet frame. this particular value is stored in this register for one sonet frame period. during the next sonet frame period, this value will be overridden with a new j1 byte value. table 283: receive sonet path ? receive b3 byte capture register (address location= 0xn1d7, where n ranges in value from 0x02 to 0x04) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 b3_byte_captur ed_value[7:0] r/o r/o r/o r/o r/o r/o r/o r/o 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 ? 0 b3_byte_captured_value[7:0] r/o b3 byte captured value[7:0] these read-only bit-fields cont ain the value of the b3 byte, within the most recently received sonet frame. this particular value is stored in this register for one sonet frame period. during the next sonet frame period, this value will be overridden with a new b3 byte value.
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 417 table 284: receive sonet path ? receive c2 byte capture register (address location= 0xn1db, where n ranges in value from 0x02 to 0x04) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 c2_byte_captured_value[7:0] r/o r/o r/o r/o r/o r/o r/o r/o 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 ? 0 c2_byte_captured_value[7:0] r/o c2 byte captured value[7:0] these read-only bit-fields contain the value of the c2 byte, within the most recently received sonet frame. this particular value is stored in this register for one sonet frame period. during the next sonet frame period, this value will be overridden with a new c2 byte value. table 285: receive sonet path ? receive g1 byte capture register (address location= 0xn1df, where n ranges in value from 0x02 to 0x04) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 g1_byte_captured_value[7:0] r/o r/o r/o r/o r/o r/o r/o r/o 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 ? 0 g1_byte_captured_value[7:0] r/o g1 byte captured value[7:0] these read-only bit-fields contain the value of the g1 byte, within the most recently received sonet frame. this particular value is stored in this register for one sonet frame period. during the next sonet frame period, this value will be overridden with a new g1 byte value.
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 418 table 286: receive sonet path ? receive f2 byte capture register (address location=0xn1e3, where n ranges in value from 0x02 to 0x04) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 f2_byte_captured_value[7:0] r/o r/o r/o r/o r/o r/o r/o r/o 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 ? 0 f2_byte_captured_value[7:0] r/o f2 byte captured value[7:0] these read-only bit-fields cont ain the value of the f2 byte, within the most recently received sonet frame. this particular value is stored in this register for one sonet frame period. during the next sonet frame period, this value will be overridden with a new f2 byte value. table 287: receive sonet path ? receive h4 byte capture register (address location= 0xn1e7, where n ranges in value from 0x02 to 0x04) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 h4_byte_captured_value[7:0] r/o r/o r/o r/o r/o r/o r/o r/o 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 ? 0 h4_byte_captured_value[7:0] r/o h4 byte captured value[7:0] these read-only bit-fields contain the value of the h4 byte, within the most recently received sonet frame. this particular value is stored in this register for one sonet frame period. during the next sonet frame period, this value will be overridden with a new h4 byte value.
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 419 table 288: receive sonet path ? receive z3 byte capture register (address location= 0xn1eb, where n ranges in value from 0x02 to 0x04) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 z3_byte_captured_value[7:0] r/o r/o r/o r/o r/o r/o r/o r/o 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 ? 0 z3_byte_captured_value[7:0] r/o z3 byte captured value[7:0] these read-only bit-fields cont ain the value of the z3 byte, within the most recently received sonet frame. this particular value is stored in this register for one sonet frame period. during the next sonet frame period, this value will be overridden with a new z3 byte value. table 289: receive sonet path ? receive z4 (k3) byte capture register (address location= 0xn1ef, where n ranges in value from 0x02 to 0x04) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 z4(k3)_byte_capt ured_value[7:0] r/o r/o r/o r/o r/o r/o r/o r/o 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 ? 0 z4(k3)_byte_captured_value [7:0] r/o z4 (k3) byte captured value[7:0] these read-only bit-fields cont ain the value of the z4 (k3) byte, within the most recently received sonet frame. this particular value is stored in this register for one sonet frame period. during the next sonet frame period, this value will be overridden with a new z4 (k3) byte value.
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 420 table 290: receive sonet path ? receive z5 capt ure register (address location= 0xn1f3, where n ranges in value from 0x02 to 0x04) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 z5_byte_captured_value[7:0] r/o r/o r/o r/o r/o r/o r/o r/o 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 ? 0 z5_byte_captured_value[7:0] r/o z5 byte captured value[7:0] these read-only bit-fields cont ain the value of the z5 byte, within the most recently received sonet frame. this particular value is stored in this register for one sonet frame period. during the next sonet frame period, this value will be overridden with a new z5 byte value.
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 421 1.10 ds3/e3 framer block the register map for the ds3/e3 framer block is pr esented in the table below. additionally, a detailed description of each of the ?ds3/e3 frame r? block registers is presented below. in order to provide some orientation for the reader, an illustration of the functional block diagram for the XRT94L33, with the ?ds3/e3 framer block ?highlighted? is presented below in figure 7. figure 7: illustration of the functi onal block diagram of the XRT94L33 (whenever it has been configured to operate in the 3-channel ds3/sts-1 to sts-3 mode), with the ds3/e3 framer block ?highlighted ds3/e3 framer block ds3/e3 framer block rx sts-1 pointer justification block rx sts-1 pointer justification block rx sts-1 poh block rx sts-1 poh block tx sts-1 poh block tx sts-1 poh block tx sts-1 pointer justification block tx sts-1 pointer justification block tx sts-1 toh block tx sts-1 toh block rx sts-1 toh block rx sts-1 toh block ds3/e3 jitter attenuator block ds3/e3 jitter attenuator block ds3/e3 mapper block ds3/e3 mapper block tx sonet poh processor block tx sonet poh processor block tx sts-3 toh processor block tx sts-3 toh processor block sts-3 telecom bus block sts-3 telecom bus block tx/rx line i/f block (primary) tx/rx line i/f block (primary) tx/rx line i/f block (aps) tx/rx line i/f block (aps) clock synthesizer block clock synthesizer block channel 1 to channels 2 ? 3 microprocessor interface microprocessor interface jtag test port jtag test port rx sonet poh processor block rx sonet poh processor block rx sts-3 toh processor block rx sts-3 toh processor block from channels 2 ? 3 rx sts-3 toh processor block (primary) rx sts-3 toh processor block (primary)
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 422 ds3/e3 framer block register table 291: ds3/e3 framer bl ock control register map a ddress l ocation r egister n ame d efault v alues 0xn300 operating mode register 0x23 0xn301 i/o control register 0xa0 0xn302, 0xn303 reserved 0x00 0xn304 block interrupt enable register 0x00 0xn305 block interrupt status register 0x00 0xn306 ? 0xn30b reserved 0x00 0xn30c test register 0x00 0xn30d ? 0xn30f payload hdlc control register 0x00 0xn30e ? 0xn30f reserved 0x00 0xn310 rxds3 configuration an d status register rxe3 configuration and st atus register # 1 ? g.832 rxe3 configuration and st atus register # 1 ? g.751 0x02 0xn311 rxds3 status register rxe3 configuration and st atus register # 2 ? g.832 rxe3 configuration and st atus register # 2 ? g.751 0x67 0xn312 rxds3 interrupt enable register rxe3 interrupt enable register # 1 ? g.832 rxe3 interrupt enable register # 1 ? g.751 0x00 0xn313 rxds3 interrupt status register rxe3 interrupt enable register # 2 ? g.832 rxe3 interrupt enable register # 2 ? g.751 0x00 0xn314 rxds3 sync detect enable register rxe3 interrupt status register # 1 ? g.832 rxe3 interrupt status register # 1 ? g.751 0x00 0xn315 rxe3 interrupt status register # 2 ? g.832 rxe3 interrupt status register # 2 ? g.751 0x00 0xn316 rxds3 feac register 0x7e 0xn317 rxds3 feac interrupt en able/status register 0x00 0xn318 rxds3 lapd control register rxe3 lapd control register 0x00 0xn319 rxds3 lapd status register rxe3 lapd status register 0x00
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 423 a ddress l ocation r egister n ame d efault v alues 0xn31a rxe3 nr byte register ? g.832 rxe3 service bit register ? g.751 0x00 0xn31b rxe3 gc byte register ? g.832 0x00 0xn31c rxe3 ttb-0 register ? g.832 0x00 0xn31d rxe3 ttb-1 register ? g.832 0x00 0xn31e rxe3 ttb-2 register ? g.832 0x00 0xn31f rxe3 ttb-3 register ? g.832 0x00 0xn320 rxe3 ttb-4 register ? g.832 0x00 0xn321 rxe3 ttb-5 register ? g.832 0x00 0xn322 rxe3 ttb-6 register ? g.832 0x00 0xn323 rxe3 ttb-7 register ? g.832 0x00 0xn324 rxe3 ttb-8 register ? g.832 0x00 0xn325 rxe3 ttb-9 register ? g.832 0x00 0xn326 rxe3 ttb-10 register ? g.832 0x00 0xn327 rxe3 ttb-11 register ? g.832 0x00 0xn328 rxe3 ttb-12 register ? g.832 0x00 0xn329 rxe3 ttb-13 register ? g.832 0x00 0xn32a rxe3 ttb-14 register ? g.832 0x00 0xn32b rxe3 ttb-15 register ? g.832 0x00 0xn32c rxe3 ssm register ? g.832 0x00 0xn32d ? 0xn32e reserved 0x00 0xn32f rxds3 pattern register 0x0c 0xn330 txds3 configuration register txe3 configuration register ? g.832 txe3 configuration register ? g.751 0x00 0xn331 txds3 feac configurati on and status register 0x00 0xn332 txds3 feac register 0x7e 0xn333 txds3 lapd configuration register txe3 lapd configuration register 0x08 0xn334 txds3 lapd status/interrupt register txe3 lapd status/interrupt register 0x00 0xn335 txds3 m-bit mask register txe3 gc byte register ? g.832 txe3 service bits register ? g.751 0x00
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 424 a ddress l ocation r egister n ame d efault v alues 0xn336 txds3 f-bit mask # 1 register txe3 ma byte register ? g.832 0x00 0xn337 txds3 f-bit mask # 2 register txe3 nr byte register ? g.832 0x00 0xn338 txds3 f-bit mask # 3 register txe3 ttb-0 register ? g.832 0x00 0xn339 txds3 f-bit mask # 4 register txe3 ttb-1 register ? g.832 0x00 0xn33a txe3 ttb-2 register ? g.832 0x00 0xn33b txe3 ttb-3 register ? g.832 0x00 0xn33c txe3 ttb-4 register ? g.832 0x00 0xn33d txe3 ttb-5 register ? g.832 0x00 0xn33e txe3 ttb-6 register ? g.832 0x00 0xn33f txe3 ttb-7 register ? g.832 0x00 0xn340 txe3 ttb-8 register ? g.832 0x00 0xn341 txe3 ttb-9 register ? g.832 0x00 0xn342 txe3 ttb-10 register ? g.832 0x00 0xn343 txe3 ttb-11 register ? g.832 0x00 0xn344 txe3 ttb-12 register ? g.832 0x00 0xn345 txe3 ttb-13 register ? g.832 0x00 0xn346 txe3 ttb-14 register ? g.832 0x00 0xn347 txe3 ttb-15 register ? g.832 0x00 0xn348 txe3 fa1 error mask register ? g.832 txe3 fas error mask upper register ? g.751 0x00 0xn349 txe3 fa2 error mask register ? g.832 txe3 fas error mask lower register ? g.751 0x00 0xn34a txe3 bip-8 mask register ? g.832 txe3 bip-4 mask register ? g.751 0x00 0xn34b tx ssm register ? g.832 0x00 0xn34c txds3 pattern register 0x0c 0xn34d receive ds3/e3 ais/pdi-p alarm enable register 0x00 0xn34e pmon excessive zero count register - msb 0x00 0xn34f pmon excessive zero count register - lsb 0x00 0xn350 pmon lcv event count register - msb 0x00
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 425 a ddress l ocation r egister n ame d efault v alues 0xn351 pmon lcv event count register - lsb 0x00 0xn352 pmon framing bit/byte error count register - msb 0x00 0xn353 pmon framing bit/byte error count register - lsb 0x00 0xn354 pmon parity error event count register - msb 0x00 0xn355 pmon parity error event count register - lsb 0x00 0xn356 pmon febe event count register - msb 0x00 0xn357 pmon febe event count register - lsb 0x00 0xn358 pmon cp-bit error count register - msb 0x00 0xn359 pmon cp-bit error count register - lsb 0x00 0xn35a ? 0xn367 reserved 0x00 0xn368 pmon prbs bit error count register - msb 0x00 0xn369 pmon prbs bit error count register - lsb 0x00 0xn36a ? 0xn36b reserved 0x00 0xn36c pmon holding register 0x00 0xn36d one second error status register 0x00 0xn36e one second ? lcv count accumulator register - msb 0x00 0xn36f one second ? lcv count accumulator register - lsb 0x00 0xn370 one second ? parity error accumulator register - msb 0x00 0xn371 one second ? parity error accumulator register - lsb 0x00 0xn372 one second ? cp bit error accumulator register - msb 0x00 0xn373 one second ? cp bit error accumulator register ? lsb 0x00 0xn374 ? 0xn37f reserved 0x00 0xn380 line interface drive register 0x00 0xn381 ? 0xn382 reserved 0x00 0xn383 txlapd byte count register 0x00 0xn384 rxlapd byte count register 0x00 0xn385 ? 0xn3af reserved 0x00 0xn3b0 transmit lapd memory indirect address register 0x00 0xn3b1 transmit lapd memory indirect data register 0x00 0xn3b2 receive lapd memory indirect address register 0x00 0xn3b3 receive lapd memory indirect data register 0x00 0xn3b4 ? 0xn3ef reserved 0x00
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 426 a ddress l ocation r egister n ame d efault v alues 0xn3f0 receive ds3/e3 configuration register ? secondary frame synchronizer block ? byte 1 0x10 0xn3f1 receive ds3/e3 configuration register ? secondary frame synchronizer block ? byte 0 0x10 0xn3f2 receive ds3/e3 ais/pdi-p alarm enable register ? secondary frame synchronizer block 0x00 0xn3f3 ? 0xn3f7 reserved 0x00 0xn3f8 receive ds3/e3 interrupt enable register ? secondary frame synchronizer block 0x00 0xn3f9 receive ds3/e3 interrupt status register ? secondary frame synchronizer block 0x00 0xn3fa ? 0xn3ff reserved 0x00
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 427 1.10.1 ds3/e3 framer block register description table 292: operating mode register (address location= 0xn300, where n ranges from 0x02 to 0x04) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 framer local loop back isds3 internal los enable software reset unused frame format timrefsel[1:0] r/w r/w r/w r/w r/o r/w r/w r/w 0 0 1 0 0 0 1 1 b it n umber n ame t ype d escription 7 framer local loop back r/w framer block local loop-back mode: this read/write bit field configures the corresponding ds3/e3 framer block to operate in the framer local loop-back mode. if the ds3/e3 framer block has been configured to operate in the framer local loop-back mode, then the output of the fram e generator block will be internally looped back into the input of the primar y frame synchronizer block. 0 ? configures the ds3/e3 framer block to to operate in the normal operating (e.g., non-framer local loop-back) mode 1 ? configures the ds3/e3 framer blo ck to operate in the framer local loop- back mode 6 isds3 r/w is ds3 mode: this read/write bit-field, along with bit 2 (frame format), permits the user to configure the frame generator, t he primary frame synchronizer and the secondary frame synchronizer blocks to operate in the appropriate framing format. the relationship between the state of this bit-field, bit 2 and the resulting framing format is presented below. bit 6 (isds3) bit 2 (frame format) framing format 0 0 e3, itu-t g.751 0 1 e3, itu-t g.832 1 0 ds3, c-bit parity 1 1 ds3, m13 note: these bit settings apply to all th ree (3) sub-blocks within the ds3/e3 framer block (e.g., the primary frame synchronizer block, the secondary frame synchronizer block and the frame generator block). 5 internal los enable r/w internal los enable: this read/write bit-field permits the us er to enable or disable the ?internal los detector?, within both the primary and secondary frame synchronizer blocks. if the user enables the ?int ernal los detector?, then the primary and/or secondary frame synchronizer block will be configured to check the incoming ds3/e3 signal for a sufficient number of ?consecutive? all-zeros bits and it will declare and clear the lo s defect condition based upon the ?1s? density and the number of consecutive ?0? bits within the incoming ds3/e3 data-stream. if the user disables the ?internal lo s detector? then the primary and/or secondary frame synchronizer block will not be configured to check the incomin g ds3/e3 si g nal for a sufficient number of ?consecutive? 0 bits, and it
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 428 will not declare nor clear the los def ect condition based upon the ?1s? density and the number of consecutive ?0? bits within the incoming ds3/e3 data-stream. 0 ? internal los detector is disabled. 1 ? internal los detector is enabled. note: 1. the internal los detector can only be enabled if the channel is configured to operate in the dual-rail mode. if the channel is configured to operate in the single-rail mode, then the internal los detector will be disabled. 2. the primary frame synchronizer block or the secondary frame synchronizer block (depending upon which block is configured to operate in the i ngress path) will automatically declare the los defect condition anytime an off-chip liu device asserts the corresponding ?ext_los_n? input pin, independent of the setting of this register bit. 4 reset r/w software reset input: a ?0? to ?1? transition in this bit-field commands a software reset to each of the following blocks within the channel. ? the primary frame synchronizer block ? the secondary frame synchronizer block ? the ingress direction mapper block ? the egress direction mapper block once the user executes a software rese t to the channel, all of the internal state machines (within each of these blocks) will be reset; and the primary and secondary frame synchronizer blocks will execute a ?reframe? operation. note: for a software reset, the contents of the command registers within the corresponding ds3/e3 framer block will not be reset to their default values. 3 unused r/o 2 frame format r/w frame format: this read/write bit-field, along with bit 6 (isds3), permits the user to configure the frame gener ator, the primary frame synchronizer and the secondary frame synchronizer blocks to operate in the appropriate framing format. the relationship between the state of this bit-field, bit 2 and the resulting framing format is presented below. bit 6 (isds3) bit 2 (frame format) framing format 0 0 e3, itu-t g.751 0 1 e3, itu-t g.832 1 0 ds3, c-bit parity 1 1 ds3, m13 1 - 0 timrefsel[1:0] r/w time reference select: these two read/write bit-fields permit the user to define both the timing source and the framin g -ali g nment source for the frame generator block, as
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 429 presented below. timrefsel[1:0] timing reference framing reference 00 loop-timing (timing is taken from the primary frame synchronizer block) asynchronous (the frame generator block will initiate the generation of a new ds3 or e3 frame, asynchronous to any signals within the viper device). 01 the clock source originating from traffic that is ?up-stream? from the frame generator block. framing alignment information from either the primary or secondary frame synchronizer block (the frame generator block will initialte the generation of a new ds3 or e3 frame based upon framing alignment information originating from either the primary frame synchronizer block or the secondary frame synchronizer block, depending upon which block is upstream from the frame generator block). 10 the clock source originating from traffic that is ?up-stream? from the frame generator block. asynchronous (the frame generator block will initiate the generation of a new ds3 or e3 frame, asynchronous to any signals within the viper device). 11 the clock source originating from traffic that is ?up-stream? from the frame generator block. asynchronous (the frame generator block will initiate the generation of a new ds3 or e3 frame, asynchronous to any signals within the viper device). note: if the user has selected a frame generator/frame synchronizer configuration, in which the fram e generator block is down-stream from either the primary frame synchronizer block or the secondary frame synchronizer block, then the user is strongly advised to set these bit-fields to ?[0, 1]?.
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 430 table 293: i/o control register (address location= 0xn301, where n ranges from 0x02 to 0x04) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 disable txloc loc disable rxloc ami/zero- suppression primary frame - single rail/dual rail* select frame generator block - ds3/e3 clock output invert: ds3/e3 clk_in invert: reframe r/w r/o r/w r/w r/o r/o r/o r/w 1 0 1 0 1 0 0 0 b it n umber n ame t ype d escription 7 disable txloc r/w disable transmit loss of clock feature: this read/write bit-field permits the user to either enable or disable the ?transmit loss of clock? feature. if this feature is enabled, then the ds3/e3 framer block will enable some circuitry that will terminate the current read or write access (to the microprocessor interface), if a ?loss of transmit (or fram e generator) clock event were to occur. the intent behind this feature is to prevent any read/write accesses (to the ds3/e3 framer block) from ?hanging? in the event of a ?loss of clock? event. 0 ? enables the ?transmit loss of clock? feature. 1 - disables the ?transmit loss of clock? feature. 6 loc r/o loss of clock indicator: this read-only bit-field indicates that the channel has experiences a loss of clock event. 5 disable rxloc r/w disable receive loss of clock feature this read/write bit-field permits the user to either enable or disable the ?receive loss of clock? feature. if this feature is enabled, then the ds3/e3 framer block will enable some circuitry that will terminate the current read or write access (to the microprocessor interface), if a ?loss of receiver (or frame synchronizer) clock event were to occur. the intent behind this feature is to prevent any read/write accesses (to the ds3/e3 framer block) from ?hanging? in the event of a ?loss of clock? event. 0 ? enables the ?receive loss of clock? feature. 1 ? disables the ?receive loss of clock? feature. 4 ami/zero- suppressi on r/w ami/zero-suppression line code select - primary frame synchronizer block input/ frame generator block output: this read/write bit-field permits the user to configure the ds3/e3 framer block (associated with channel n) to operate in either the ami or b3zs/hdb3 line code; as described below. 0 ? configures the ds3/e3 framer chann el to operate in the b3zs/hdb3 line code. 1- configures the ds3/e3 framer ch annel to operate in the ami line code. 3 primary frame - sin g le r/w primary frame synchronizer block input/frame generator block output - single-rail/dual-rail select:
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 431 rail/dual rail select this read/write bit-field permits the user to implement either of the following options. 1. to configure the primary frame sync honizer block to accept the ingress ds3/e3 data (from the ds3/e3 liu ic) in either the single-rail or dual- rail manner. 2. to configure the ds3/e3 frame g enerator block to output the egress ds3/e3 data (to the ds3/e3 liu ic) in either rthe single-rail or dual-rail manner. more specifically, if the user configures the primary frame synchronizer and the frame generator blocks to operate in the single-rail mode, then the following will happen. ? the primary frame synchronizer block will accept data (from the liu ic) in a single-rail manner. ? the frame generator block will output data (to the liu ic) in a single-rail manner. if the user configures the primary frame synchronizer and frame generator blocks to operate in the dual-rail mode, then the following will happen. ? the primary frame synchronizer block will accept data (from the liu ic) in a dual-rail manner. ? the frame generator block will output da ta (to the liu ic) in a dual-rail manner. 0 ? configures the primary frame synchronizer/frame generator blocks to operate in the dual-rail mode. 1 ? configures the primary frame synchronizer/frame generator blocks to operate in the single-rail mode. note: this bit-field is only valid if the primary frame synchronizer block has been configured to operate in the ingress direction, and if the frame generator block has been configured to operate in the egress direction. 2 frame generator block - ds3/e3_ clk_out invert: frame generator block - ds3/e3_clk_out invert: this read/write bit-field permits the user to configure the ds3/e3 frame generator block (of channel n), within the XRT94L33, to update the ?txds3pos_n? and ?txds3neg_n? output pins (pin b18, g24, ag9) upon either the rising or falling edge of ?txds3lineclk_n? (pin c17, e25, af10) 0 ? ?txds3pos_n/txds3neg_n? is upd ated upon the rising edge of ?txds3lineclk_n?. the user should insure that the liu ic will sample ?txds3pos_n? upon the falling edge of ?txds3lineclk_n?. 1 ? ?txds3pos_n/txds3neg_n? is updated upon the falling edge of ?txds3lineclk_n?. the user should insure that the liu ic will sample ?txds3pos_n/txds3neg_n? pins upon the rising edge of ?txds3lineclk_n?. note: this bit-field is only active if the frame generator block has been configured to operate in the egress path. 1 ds3/e3_ clock input - invert r/o ds3/e3_clock input - invert: this read/write bit-field permits the us er to configure either the primary or secondary frame synchronizer block (depending upon which synchronizer block is operating in the ingress path), within the XRT94L33; to sample and latch the ?rxds3pos_n? input pins (pin b14. c21. ag15)? upon either the rising or falling edge of ?rxds3lineclk_n? (pin d14, a24, af14).. 0 ? configures the ds3/e3 framer block circuitry to sample the ?rxds3pos_n/rxds3neg_n? input pins upon the falling edge of the ?rxds3lineclk_n? input signal. 1 ? confi g ures the ds3/e3 framer block circuitr y to sam p le the
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 432 ?rxds3pos_n/rxds3neg_n? input pins upon the rising edge of ?rxds3lineclk_n?. note: this register bit-field applies to either the primary or secondary frame synchronizer block (depending upon which bl ock is operating in the ingress path). 0 reframe r/w primary ds3/e3 frame synchronizer block ? reframe command: a ?0? to ?1? transition, within this bit-field commands the primary ds3/e3 frame synchronizer block (within channel n) to exit the frame maintenance mode, and go back and enter the frame acquisition mode. note: the user should go back and set this bit-field to ?0? following execution of the ?reframe? command.
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 433 table 294: block interrupt enable register (address location= 0xn304, where n ranges from 0x02 to 0x04) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 primary and/or secondary ds3/e3 frame synchronizer block interrupt enable unused ds3/e3 frame generator block interrupt enable one second interrupt r/w r/o r/o r/o r/o r/o r/w r/w 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 primary and/or secondary ds3/e3 frame synch block interrupt enable r/w primary and/or secondary ds3/e3 frame synchronizer block interrupt enable: this read/write bit-field permits the user to enable or disable both the primary and secondary frame synchronizer blocks for interrupt generation. if the user enables the primary and secondary frame synchronizer blocks (for interrupt generation) at the block level, the user still needs to enable the interrupts at the ?source? level, as well; in order for these interrupts to be enabled. however, if the user disables the primary and secondary frame synchronizer block (for interrupt generation) at the block level, then all frame synchronizer-related blocks are disabled. 0 ? both the primary and secondary frame synchronizer blocks are disabled for interrupt generation. 1 ? both the primary and secondary frame synchronizer blocks are enabled (at the block level) for interrupt generation. 6 ? 2 unused r/o 1 ds3/e3 frame generator block interrupt enable r/w ds3/e3 frame generator block interrupt enable: this read/write bit-field permits the user to enable or disable the frame generator block for interr upt generation. if the user enables the frame generator block (for interr upt generation) at the blo ck level, the user still needs to enable the interrupts at the ?source? level, as well; in order for these interrupts to be enabled. however, if the user disables the frame generator block (for interrupt generation) at the block level, then all frame generator-related blocks are disabled. 0 ? frame generator block is disabled for interrupt generation. 1 ? frame generator block is enabled (at the block level) for interrupt generation. 0 one second interrupt r/w one second interrupt enable: this read/write bit-field permits the user to enable or disable the one- second interrupt, with in channel n. if the user enables this interrupt, then channel n will generate an interrupt at one second intervals. 0 ? one second interrupt is disabled. 1 ? one second interrupt is enabled.
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 434 table 295: block interrupt status register (address location= 0xn305, where n ranges from 0x02 to 0x04) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 primary and/or secondary ds3/e3 frame sync block interrupt status unused ds3/e3 frame generator block interrupt status one second interrupt r/o r/o r/o r/o r/o r/o r/o rur 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 primary and/or secondary ds3/e3 frame synch block interrupt status r/o primary and/or secondary ds3/e3 frame synchronizer block interrupt status: this read-only bit-field indicates whether or not a ?primary or secondary ds3/e3 frame synchronizer block?-rela ted interrupt (within channel n) is requesting interrupt service. 0 ? indicates that neither the prim ary nor the secondary ds3/e3 frame synchronizer block (within channel n) is not requesting any interrupt service. 1 ? indicates that either the prim ary or the secondary ds3/e3 frame synchronizer block (within channel n) is requesting interrupt service. 6 - 2 unused r/o 1 ds3/e3 frame generator block interrupt status r/o ds3/e3 frame generator block interrupt status: this read-only bit-field indicates whether or not a ?ds3/e3 frame generator? ?related interrupt (within channe l n) is requesting interrupt service. 0 ? the ds3/e3 frame generator block (within channel n) is not requesting any interrupt service. 1 ? the ds3/e3 frame synchronizer block (within channel n) is requesting interrupt service. 0 one second interrupt status rur one second interrupt status this reset-upon-read bit-field indicates whether or not a ?one second? interrupt (from channel n) has occurred since the last read of this register. 0 ? the one second interrupt has not occurred since the last read of this register. 1 ? the one second interrupt has occurred since the last read of this register.
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 435 table 296: test register (address location= 0xn30c, where n ranges from 0x02 to 0x04) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 txohsrc unused rxprbs lock rxprbs enable txprbs enable unused r/w r/o r/o r/o r/w r/w r/o r/o 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 txohsrc r/w transmit overhead bit source: this read/write bit-field permits the user to configure the ds3/e3 frame generator block to accept and insert over head bits/bytes which are input via the ?transmit payload data input interface? block, as indicated below. 0 ? no overhbead bit insertion will occur. overhead bits/bytes are internally generated by the ds3/e3 frame generator block. 1 ? overhead bit insertion will occur. in this case, the overhead bits/byte data is accepted from the transmit paylo ad data input interface block. note: this register bit applies to all frami ng formats that are supported by the frame generator block. 6 - 5 unused r/o 4 rxprbs lock r/o prbs lock indicator: this read-only bit-field indicates whether or not the prbs receiver (within the primary frame synchronizer block) has acquired ?prbs lock? with the payload data of the incoming ds3 or e3 data stream, as described below. 0 ? indicates that the prbs receiver does not have prbs lock with the incoming data stream. 1 ? indicates that the prbs receiver does have prbs lock with the incoming data stream. note: this bit-field is not valid if the prbs re ceiver is disabled, or if the primary frame synchronizer block is bypassed. 3 rxprbs enable r/w receive prbs enable: this read/write bit-field permits the us er to either enable or disable the prbs receiver within the primary frame synchroni zer block. once the user enables the prbs receiver, then it will proceed to atte mpt to acquire and maintain pattern (or prbs lock) within the payload bits, within the incoming ds3 or e3 data stream. 0 ? disables the prbs receiver. 1 ? enables the prbs receiver. note: this bit-field is ignored if the fram e synchronizer block is by-passed. 2 txprbs enable r/w transmit prbs enable: this read/write bit-field permits the us er to either enable or disable the prbs generator within the ds3/e3 frame generator block. once the user enables the prbs generator block, then it will proceed to insert a prbs pattern into the payload bits, within the outbound ds3 or e3 data stream. 0 ? disables the prbs generator. 1 ? enables the prbs generator. note: this bit-field is ignored if the fr ame generator block is by-passed.
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 436 1 - 0 unused r/o
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 437 1.10.2 r eceive ds3 r elated r egisters table 297: rxds3 configuration and status register (address location= 0xn310, where n ranges from 0x02 to 0x04) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 ds3 ais defect declared ds3 los defect declared ds3 idle condition declared oof defect declared unused framing with valid p- bits f-sync algo m-sync algo r/o r/o r/o r/o r/o r/w r/w r/w 0 0 0 1 0 0 1 0 b it n umber n ame t ype d escription 7 ds3 ais defect declared r/o ds3 ais defect declared indicator ? primary frame synchronizer block: this read-only bit-field indicates whether or not the primary frame synchronizer block is currently decl aring the ais defect condition in its incoming path, as described below. 0 ? indicates that the primary frame synchronizer block is not currently declaring the ds3 ais defect condition. 1 ? indicates that the prim ary frame synchronizer block is currently declaring the ds3 ais defect condition. 6 los defect declared r/o los defect condition declared indi cator ? primary frame synchronizer block: this read-only bit-field indicates whether or not the primary frame synchronizer block is currently decl aring the los defect condition, in its incoming path, as described below. 0 ? indicates that the primary frame synchronizer block is not currently declaring the los defect condition in its incoming path. 1 ? indicates that the prim ary frame synchronizer block is currently declaring the los defect condition in its incoming path. 5 ds3 idle condition declared r/o ds3 idle signal pattern detected ? primary frame synchronizer block: this read-only bit-field indicates whether or not the primary frame synchronizer block is currently detecting the ds3 idle pattern, in its incoming path. 0 ? indicates that the primary frame synchronizer block is not currently detecting the ds3 idle pattern, in its incoming path. 1 ? indicates that the prim ary frame synchronizer block is currently detecting the ds3 idle pattern in its incoming path. note: this bit-field is only valid of the ds3/e3 framer block has been configured to operat e in the ds3 mode. 4 oof defect condition declared r/o oof (out of frame) defect condition declared indicator ? primary frame synchronizer block: this read-only bit-field indicates whether or not the primary frame synchronizer block is currently declaring the oof (out of frame) defect condition, as described below. 0 ? indicates that the primary frame synchronizer block is not currently declaring the oof defect condition. 1 ? indicates that the prim ary frame synchronizer block is currently declaring the oof defect condition.
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 438 3 unused r/o 2 framing with valid p bits r/w framing with valid p-bit select: this read/write bit-field permits the user to choose between two different sets of ds3 frame acquisition/mainten ance criteria that the primary frame synchronizer block will use to (1) acquire and declare frame synchronization, and (2) to declare the oof defect condition. 0 ? normal framing acquisition/maintena nce criteria (without p-bit checking) in this mode, the primary frame synchron izer block will declare the ?in-frame? state, one it has successfully completed both the ?f-bit search? and the ?m-bit search? states. 1 ? framing acquisition/maintenance with p-bit checking in this mode, the primary frame synchronizer block will (in addition to passing through the ?f-bit search? and ?m-bit search? states) al so verify valid p-bits, prior to declaring the ?in-frame? state. note: this bit-field is ignored if the ds3/e3 framer block is configured to operate in the e3 mode, or if the primary frame synchronizer block is by-passed. 1 f-sync algo r/w f-bit search state criteria select: this read/write bit-field permits the user to choose between two different sets of ds3 out of frame (oof) declaration criteria. 0 ? configures the primary frame sy nchronizer block to declare the oof defect condition anytime it determines that 6 out of the last 15 f-bits are erred. 1 ? configures the primary frame synchr onizer block to declare the oof is defect condition anytime it determines that 3 out of the last 15 f-bits are erred. note: this bit-field is ignored if t he ds3/e3 framer block has been configured to operate in the e3 mode, or if the primary frame synchronizer block is by-passed. 0 m-sync algo r/w m-bit search state criteria select: this read/write bit-field permits the user to choose between two different sets of ds3 out of frame (oof) declaration criteria. 0 ? configures the primary frame sy nchronizer block to not declare the oof defect condition, due to m-bit errors. 1 ? configures the primary frame sy nchronizer block to declare the oof defect condition anytime it determines that the m-bits within 3 out of 4 consecutive ds3 frames are in error. note: this bit-field is ignored if the ds3/e3 framer block has been configured to operate in the e3 mode.
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 439 table 298: rxds3 status register (address location= 0xn311, where n ranges from 0x02 to 0x04) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 unused ferf/rdi defect declared rxaic rxfebe[2:0] r/o r/o r/o r/o r/o r/o r/o r/o 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 - 5 unused r/o 4 ferf/rdi defect declared r/o ferf/rdi (far-end receive failure/remote defect indicator) defect declared indicator: this read-only bit-field indicates whether or not the primaryframe synchronizer block is currently decl aring the ferf/rdi defect condition as described below. 0 ? the primary frame synchronizer bl ock is not currently declaring the ferf/rdi defect condition. 1 ? the primary frame synchronizer block is currently declaring the ferf/rdi defect condition. note: this bit-field is not valid if the primary frame synchronizer block has been by-passed. 3 rxaic r/o receive aic state: this read-only bit-field indicates the cu rrent state of the ai c bit-field within the incoming ds3 data-stream. 0 ? indicates that the frame synchronizer block has received at least 2 consecutive m-frames that have the aic bit-field set to ?0?. 1 ? indicates that the frame synchronizer block has received at least 63 consecutive m-frames that have t he aic bit-field set to ?1?. note: this bit-field is only active if the ds3/e3 framer block has been configured to operat e in the ds3 mode. 2 ? 0 rxfebe[2:0] r/o receive febe (far-end block error) value: these read-only bit-fields reflect the febe value within the most recently received ds3 frame. rxfebe[2:0] = [1, 1, 1] indicates a nor mal condition. all other values for rxfebe[2:0] indicates an er red condition at the remo te terminal equipment. note: 1. this bit-field is not valid if t he primary frame synchronizer block has been by-passed. 2. this bit-field is only valid if the primary frame synchronizer block has been configured to operate in the ds3, c-bit parity framing format.
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 440 table 299: rxds3 interrupt enable register (address location= 0xn312, where n ranges from 0x02 to 0x04) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 detection of cp bit error interrupt enable change of los defect condition interrupt enable change of ais defect condition interrupt enable change of idle condition interrupt enable change of ferf/rdi defect condition interrupt enable change of aic state interrupt enable change of oof defect condition interrupt enable detection of p-bit error interrupt enable r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 detection of cp bit error interrupt enable r/w detection of cp-bit error interrupt enable: this read/write bit-field permits the user to either enable or disable the ?detection of cp-bit error? interrupt, wi thin the channel. if the user enables this interrupt, then the primary frame synchronizer block will generate an interrupt anytime it detects cp bit errors. 0 ? disables the ?detection of cp bit error? interrupt. 1 ? enables the ?detection of cp-bit error? interrupt. note: this bit-field is only active if the ds3/e3 framer block has been configured to operate in the ds3, c-bit parity framing format. 6 change of los defect condition interrupt enable r/w change in los defect condition interrupt enable: this read/write bit-field permits the user to either enable or disable the ?change in los (loss of signal) defect condition? interrupt, within the channel. if the user enables this interrupt, then the primary frame synchronizer block will generate an interrupt in response to either of the following conditions. ? the instant that the primary fram e synchronizer block declares an los defect condition. ? the instant that the primary frame synchronizer block clears the los defect condition. 0 ? disables the ?change in los defect condition? interrupt. 1 ? enables the ?change in los defect condition? interrupt. note: this configuration setting only applies to the primary frame synchronizer block. this config uration setting does not apply to the secondary frame synchronizer block. 5 change of ais defect condition interrupt enable r/w change in ais defect condition interrupt enable: this read/write bit-field permits the user to either enable or disable the ?change in ais (alarm indication signal) defect condition? interrupt, within the channel. if the user enables this interrupt, then the primary frame synchronizer block will generate an interrupt in response to either of the following conditions. ? the instant that the primary fram e synchronizer block declares an ais defect condition. ? the instant that the primary frame synchronizer block clears the ais defect condition. 0 ? disables the ?change in ais defect condition? interrupt.
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 441 1 ? enables the ?change in ais defect condition? interrupt. note: this bit-field is ignored if the prim ary frame synchronizer block is by- passed. 4 change of ds3 idle condition interrupt enable r/w change in ds3 idle condition interrupt enable: this read/write bit-field permits the user to either enable or disable the ?change in ds3 idle condition? interrupt, within the channel. if the user enables this interrupt, then the primary frame synchronizer block will generate an interrupt in response to either of the following conditions. ? the instant that the primary fram e synchronizer block declares the ds3 idle condition. ? the instant that the pr imary frame synchronizer block clears the ds3 idle condition. 0 ? disables the ?change in ds3 idle condition? interrupt. 1 ? enables the ?change in ds3 idle condition? interrupt. note: this bit-field is ignored if the prim ary frame synchronizer block is by- passed. 3 change of ferf/rdi defect condition interrupt enable r/w change in ferf/rdi defect condition interrupt enable: this read/write bit-field permits the user to either enable or disable the ?change in ferf/rdi (far-end receive failure/remote defect indicator) condition? interrupt, within the channel. if the user enables this interrupt, then the primary frame synchronizer block wi ll generate an interrupt in response to either of the following conditions. ? the instant that the primary fram e synchronizer block declares the ferf/rdi defect condition. ? the instant that the primary frame synchronizer block clears the ferf/rdi defect condition. 0 ? disables the ?change in ferf/rdi defect condition? interrupt. 1 ? enables the ?change in ferf/rdi defect condition? interrupt. note: this bit-field is ignored if the prim ary frame synchronizer block is by- passed. 2 change of aic state interrupt enable r/w change in aic state interrupt enable: this read/write bit-field permits the user to either enable or disable the ?change in aic state? interrupt, within t he channel. if the user enables this interrupt, then the primary frame synchronizer block will generate an interrupt in response to it detecting a change in the aic bit-field, within the incoming ds3 data stream. 0 ? disables the ?change in aic state? interrupt. 1 ? enables the ?change in aic state? interrupt. note: this bit-field is ignored if the prim ary frame synchronizer block is by- passed. 1 change of oof defect condition interrupt enable r/w change in oof defect condition interrupt enable: this read/write bit-field permits the user to either enable or disable the ?change in oof (out of frame) defect condition? interrupt, within the channel. if the user enables this interrupt, then the primary frame synchronizer block will generate an interrupt in response to either of the following conditions. ? the instant that the primary frame synchronizer block declares the oof defect condition.
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 442 ? the instant that the primary frame synchronizer block clears the oof defect condition. 0 ? disables the ?change in oof defect condition? interrupt. 1 ? enables the ?change in oof defect condition? interrupt. note: this bit-field is ignored if the prim ary frame synchronizer block is by- passed. 0 detection of p- bit error interrupt enable r/w detection of p-bit error interrupt enable: this read/write bit-field permits the user to either enable or disable the ?detection of p-bit error? interrupt, within the channel. if the user enables this interrupt, then the primary frame synchronizer block will generate an interrupt anytime it detects p bit errors. 0 ? disables the ?detection of p bit error? interrupt. 1 ? enables the ?detection of p-bit error? interrupt. note: this bit-field is ignored if the prim ary frame synchronizer block is by- passed.
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 443 table 300: rxds3 interrupt status register (addr ess location= 0xn313, where n ranges from 0x02 to 0x04) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 detection of cp bit error interrupt status change of los defect condition interrupt status change of ais defect condition interrupt status change of ds3 idle condition interrupt status change of ferf/rdi condition interrupt status change of aic state interrupt status change of oof defect condition interrupt status detection of p-bit error interrupt status rur rur rur rur rur rur rur rur 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 detection of cp bit error interrupt status rur detection of cp-bit error interrupt status: this reset-upon-read bit-field indicates whether or not the ?detection of cp-bit error? interrupt has occurred sinc e the last read of this register. 0 ? the ?detection of cp-bit error? inte rrupt has not occurred since the last read of this register. 1 ? the ?detection of cp-bit error? inte rrupt has occurred since the last read of this register. note: this bit-field is only active if the ds3/e3 framer block has been configured to operae in the ds3, c-bit parity framing format. this bit field is also ignored if the primary frame synchronizer block is by-passed. 6 change of los defect condition interrupt status rur change in los defect condition interrupt status: this reset-upon-read register indica tes whether or not the ?change in los defect condition? interrupt has occurred since the last read of this register. 0 ? the ?change in los defect condition? interrupt has not occurred since the last read of this register. 1 ? the ?change in los defect condition? interrupt has occurred since the last read of this register. note: this bit-field is ignored if the pr imary frame synchronizer block is by-passed. 5 change of ais defect condition interrupt status rur change in ais defect condition interrupt status this reset-upon-read register indica tes whether or not the ?change in ais defect condition? interrupt has occurred since the last read of this register. 0 ? the ?change in ais defect condition? interrupt has not occurred since the last read of this register. 1 ? the ?change in ais defect condit ion? interrupt has occurred since the last read of this register. note: this bit-field is ignored if the pr imary frame synchronizer block is by-passed. 4 change of ds3 idle condition interrupt status rur change in ds3 idle condition interrupt status: this reset-upon-read register indica tes whether or not the ?change in ds3 idle condition? interrupt has occurred since the last read of this register. 0 ? the ?chan g e in ds3 idle condition? interru p t has not occurred since the
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 444 last read of this register. 1 ? the ?change in ds3 idle condition? interrupt has occurred since the last read of this register. note: this bit-field is ignored if the pr imary frame synchronizer block is by-passed. 3 change of ferf/rdi defect condition interrupt status rur change in ferf/rdi defect condition interrupt status: this reset-upon-read register indica tes whether or not the ?change in ferf/rdi defect condition? interrupt has occurred since the last read of this register. 0 ? the ?change in ferf/rdi defect condition? interrupt has not occurred since the last read of this register. 1 ? the ?change in ferf/rdi defect condition? interrupt has occurred since the last read of this register. note: this bit-field is ignored if the pr imary frame synchronizer block is by-passed. 2 change of aic state interrupt status rur change in aic state interrupt status: this reset-upon-read register bit indicates whether or not the ?change in aic state? interrupt has occurred si nce the last read of this register. 0 ? the ?change in aic state? interrupt has not occurred since the last read of this register. 1 ? the ?change in aic state? interrupt has occurred since the last read of this register. note: this bit-field is ignored if the pr imary frame synchronizer block is by-passed. 1 change of oof defect condition interrupt status rur change in oof defect condition interrupt status: this reset-upon-read register indica tes whether or not the ?change in oof defect condition? interrupt has occurred since the last read of this register. 0 ? the ?change in oof defect condition? interrupt has not occurred since the last read of this register. 1 ? the ?change in oof defect condition? interrupt has occurred since the last read of this register. note: this bit-field is ignored if the pr imary frame synchronizer block is by-passed. 0 detection of p-bit error interrupt status rur detection of p-bit error interrupt status: this reset-upon-read bit-field indicates whether or not the ?detection of p-bit error? interrupt has occurred since the last read of this register. 0 ? the ?detection of p-bit error? interrupt has not occurred since the last read of this register. 1 ? the ?detection of p-bit error? interrupt has occurred since the last read of this register. note: this bit-field is ignored if the pr imary frame synchronizer block is by-passed.
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 445 table 301: rxds3 sync detect register (address location= 0xn314, where n ranges from 0x02 to 0x04) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 unused p-bit correct f algorithm one and only r/o r/o r/o r/o r/o r/w r/w r/w 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 2 p-bit correct r/w p-bit correct: this read/write bit-field permits the user to enable or disable the ?p-bit correct? feature within the primary fram e synchronizer block. if the user enables this feature, then the pr imary frame synchronizer block will automatically invert the state of any p-bits, whenever it detects ?p-bit errors? within the incoming ds3 data-stream. 0 ? disables the ?p-bit correct? feature. 1 ? enables the ?p-bit correct? feature 1 f algorithm r/w f-bit search algorithm select: this read/write bit-field permits the us er to select the ?f-bit acquisition? criteria that the primary frame synchron izer block will use whenever it is operating in the ?f-bit search? state, as depicted below. 0 ? configures the primary frame sync hronizer block will move on to the ?m-bit search? state, when ever it has properly lo cated 10 consecutive f- bits within the incoming ds3 data-stream. 1 ? primary frame synchronizer block will move on to the ?m-bit search? state, when it has properly located 16 consecutive f-bits within the incoming ds3 data-stream. note: this bit-field is only active if the user has configured the ds3/e3 framer block to operate in the ds3 mode. 0 one and only r/w f-bit search/mimic-handling algorithm select: this read/write bit-field permits the us er to select the ?f-bit acquisition? criteria that the primary frame synchron izer block will use whenever it is operating in the ?f-bit search? state. 0 ? configures the primary frame sync hronizer block to move on to the ?m-bit search? state, when it has properly located 10 (or 16) consecutive f- bits (as configured in bit 1 of this register). 1 ? configures the primary frame sync hronizer block to move on to the ?m-bit search? state, when (1) it has properly located 10 (or 16) consecutive f-bits; and (2) when it has located and identified only one viable ?f-bit alignment? candidate. note: if this bit is set to ?1?, then the primary frame synchronizer block will not transition into the ?m-bit search? state, as long as at least two viable candidate set of bits appear to function as the f- bits.
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 446 table 302: rxds3 feac register (address location= 0xn316, where n ranges from 0x02 to 0x04) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 unused rxfeaccode[5:0] unused r/o r/o r/o r/o r/o r/o r/o r/o 0 1 1 1 1 1 1 0 b it n umber n ame t ype d escription 7 unused r/o 6 - 1 rxfeac_code[5:0] r/o receive feac code word: these read-only bit-fields contain the value of the most recently ?validated? feac code word. note: these bit-fields are only active if the ds3/e3 framer block has been configured to operate in the ds3, c-bit parity framing format. 0 unused r/o
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 447 table 303: rxds3 feac interrupt enable/status register (address location= 0xn317, where n ranges from 0x02 to 0x04) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 unused feac valid rxfeac remove interrupt enable rxfeac remove interrupt status rxfeac valid interrupt enable rxfeac valid interrupt status r/o r/o r/o r/o r/w rur r/w rur 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 - 5 unused r/o please set to ?0? (the default value) for normal operation. 4 feac valid r/o feac message validation indicator: this read-only bit-field indicates that the feac code (which resides within the ?rxds3 feac? register) has been validated by the receive feac controller block. the receive feac controller block will validate a feac codeword if it has received this code word in 8 out of the last 10 feac messages. polled systems can monitor this bit-field, when checking for a newly validated feac codeword. 0 ? feac message is not (or no longer) validated. 1 ? feac message has been validated. note: this bit-field is only active if the ds3/e3 framer block has been configured to operate in the ds3, c-bit parity framing format. 3 rxfeac remove interrupt enable r/w feac message remove interrupt enable: this read/write bit-field permits the us er to either enable or disable the ?receive feac remove interrupt?. if the user enables this interrupt, then the primary framer synchronizer block will generate an interrupt anytime the most recently validated feac message has been removed. the receive feac controller sub-block will remove a validated feac codeword, if it has received a different codeword in 3 out of the last 10 feac messages. 0 ? receive feac remove interrupt is disabled. 1 ? receive feac remove interrupt is enabled. note: this bit-field is only active if the ds3/e3 framer block has been configured to operate in the ds3, c-bit parity framing format. further, this bit-field is ignored if the primary frame synchronizer block is by-passed. 2 rxfeac remove interrupt status rur feac message remove interrupt status: this reset-upon-read bit-field indicates whether or not the ?feac message remove interrupt? has occurred since t he last read of this register. 0 ? feac message remove interrupt has not occurred since the last read of this register. 1 ? feac message remove interrupt has occurred since the last read of this register. note: this bit-field is only active if the ds3/e3 framer block has been configured to operate in the ds3, c-bit parity framing format. 1 rxfeac valid interrupt r/w feac message validation interrupt enable: this read/write bit-field p ermits the user to either enable or disable the
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 448 interrupt enable feac message validation interrupt. if t he user enables this interrupt, then the primary frame synchronizer block wi ll generate an interrupt anytime a new feac codeword has been validated by the receive feac controller sub-block. 0 ? feac message validation interrupt is not enabled. 1 ? feac message validation interrupt is enabled. note: this bit-field is only active if the ds3/e3 framer block has been configured to operate in the ds3, c-bit parity framing format. 0 rxfeac valid interrupt status rur feac message validation interrupt status: this reset-upon-read bit-field indicates whether or not the ?feac message validation? interrupt has occurred sinc e the last read of this register. 0 ? feac message validation interrupt has not occurred since the last read of this register. 1 ? feac message validation interrupt has occurred since the last read of this register. note: this bit-field is only active if the ds3/e3 framer block has been configured to operate in the ds3, c-bit parity framing format.
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 449 table 304: rxds3 lapd control register (address location= 0xn318, where n ranges from 0x02 to 0x04) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 rxlapd any unused receive lapd enable receive lapd interrupt enable receive lapd interrupt status r/w r/o r/o r/o r/o r/w r/w rur 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 rxlapd any r/w receive lapd ? any kind: this read/write bit-field permits the user to configure the receive lapd controller sub-block (within the primary frame synchronizer block) to receive any kind of lapd message (or hdlc message) with a size of 82 bytes or less. if the user implements this option, then the receive lapd controller sub-block will be capable of receiving any kind of hdlc message (with any value of header bytes). the only restriction is t hat the size of the hdlc message must not exceed 82 bytes. 0 ? does not invoke this ?any kind of hd lc message? feature. in this case, the receive lapd controller sub-block will only receive hdlc messages that contains the bellcore gr-499-core values for sapi and tei. invokes this ?any kind of hdlc message? feature. in this case, the receive lapd controller sub-block will be able to receive hdlc messages that contain any header byte values. note: this bit-field is ignored if the primary frame synchronizer block is by-passed. the user can determine the size (or byte -count) of the most recently received lapd/pmdl message, by reading the contents of the ?rxlapd byte count? register (address location= 0xn384) 6 ? 3 unused r/o 2 receive lapd enable r/w receive lapd controller sub-block enable: this read/write bit-field permits the user to either enable or disable the receive lapd controller sub-block within the primary frame synchronizer block. if the user enables the receive la pd controller sub-block, then it will immediately begin extracting out and m onitoring the data (being carried via the ?dl? bits) within the incoming ds3 data stream. 0 ? enables the receive lapd controller sub-block. 1 ? disables the receive lapd controller sub-block. note: this bit-field is ignored if the primary frame synchronizer block is by- passed. 1 receive lapd interrupt enable r/w receive lapd message interrupt enable: this read/write bit-field permits the user to either enable or disable the ?receive lapd message? interrupt. if the user enables this interrupt, then the channel will generate an interrupt, anyt ime the receive lapd controller sub- block receives a new pmdl message. 0 ? disables the ?receive lapd message? interrupt. 1 ? enables the ?receive lapd message? interrupt.
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 450 note: this bit-field is only active if the ds3/e3 framer block has been configured to operate in the ds3, c-bit parity framing format. this bit-field is ignored if the primar y frame synchronizer block is by- passed. 0 receive lapd interrupt status rur receive lapd message interrupt status: this reset-upon-read bit-field indicates whether or not the ?receive lapd message? interrupt has occurred since t he last read of this register. 0 ? ?receive lapd message? interrupt has not occurred since the last read of this register. 1 ? ?receive lapd message? interrupt has occurred since the last read of this register. note: this bit-field is only active if the ds3/e3 framer block has been configured to operate in the ds3, c-bit parity framing format. this bit-field is ignored if the primar y frame synchronizer block is by- passed.
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 451 table 305: rxds3 lapd status register (address location= 0xn319, where n ranges from 0x02 to 0x04) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 unused rxabort rxlapdtype[1:0] rxcr type rxfcs error end of message flag present r/o r/o r/o r/o r/o r/o r/o r/o 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 unused r/o 6 rxabort r/o receive abort sequence indicator: this read-only bit-field indicates that the receive lapd controller sub-block has received an abort sequence (e.g., a string of seven consecutive ?0s?). 0 ? indicates that the receive l apd controller sub-block has not received an abort sequence. 1 - indicates that the receive lapd controller sub-block has received an abort sequence. note: once the receive lapd contro ller sub-block receives an abort sequence, it will set this bit-field ?high?, until it receives another lapd messages. 5 ? 4 rxlapdtype[1:0] r/o receive lapd message type indicator: these two read-only bits indicate the type of lapd message that is residing within the receive lapd message buffer. the relationship between the content of these two bit-fields and the corresponding message type is presented below. rxlapdtype[1:0] message type 0 0 cl path identification 0 1 idle signal identification 1 0 test signal identification 1 1 itu-t path identification 3 rxcr type r/o received c/r value: this read-only bit-field indicates the value of the c/r bit (within one of the header bytes) of the most recently received lapd message. note: this bit-field is only active if the ds3/e3 framer block has been configured to operate in the ds3, c-bit parity framing format. 2 rxfcs error r/o receive frame check sequence (fcs) error indicator: this read-only bit-field indicates whether or not the most recently received lapd message frame contained an fcs error. 0 ? the most recently received l apd message frame does not contain an fcs error. 1 ? the most recentl y received lapd messa g e frame does contain an
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 452 fcs error. note: this bit-field is only active if the ds3/e3 framer block has been configured to operate in the ds3, c-bit parity framing format. 1 end of message r/o end of message indicator this read-only bit-field indicates whether or not the receive lapd controller sub-block has received a complete lapd message, as described below. 0 ? the receive lapd controller sub-block is currently receiving a lapd message, but has not received the complete message. 1 ? the receive lapd controller sub-block has received a completed lapd message. note: once the receive lapd controller sub-block sets this bit-field ?high?, this bit-field will remain high, until the receive lapd controller sub-block begins to receive a new lapd message. 0 flag present r/o receive flag sequence indicator: this read-only bit-field indicates whether or not the receive lapd controller sub-block is currently receiving the flag sequence (e.g., a continuous stream of 0x7e octets within the data link channel), as described below. 0 ? indicates that the receive la pd controller sub-block is not currently receiving the flag sequence octet. 1 ? indicates that the receive lapd controller sub-block is currently receiving the flag sequence octet.
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 453 table 306: rxds3 pattern register (address location= 0xn32f, where n ranges from 0x02 to 0x04) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 ds3 ais unframed all ones ds3 ais non stuck stuff unused receive los pattern receive ds3 idle pattern[3:0] r/w r/w r/o r/w r/w r/w r/w r/w 0 0 0 0 1 1 0 0 b it n umber n ame t ype d escription 7 ds3 ais unframed all ones r/w ds3 ais - unframed all ones ? ais pattern this read/write bit-field, (along with the ?non-stuck-stuff? bit) permits the user specify the ?ais declaratio n? criteria for the primary frame synchronizer block, as described below. 0 ? configures the primary frame sy nchronizer block to declare the ais defect condition, when receiving a ds3 signal carrying a ?framed 1010..? pattern. 1 ? configures the primary frame sy nchronizer block to declare the ais defect condition, when receiving either an unframed, all ones pattern or a ?framed 1010..? pattern. 6 ds3 ais non-stuck stuff r/w ds3 ais - non-stuck-stu ff option ? ais pattern this read/write bit-field (along with the ?unframed all ones ? ais pattern bit-field) permits the user to define the ?ais defect declaration? criteria for the primary frame synchronizer block, as described below. 0 ? configures the primary frame synchr onizer block to require that all ?c? bits are set to ?0? before it will declare the ais defect condition. 1 ? configures the primary frame sync hronizer block to not require that all ?c? bits are set to ?0? before it will declare the ais defect condition. in this mode, no attention will be paid to the state of the ?c? bits within the incoming ds3 data-stream. 5 unused r/o 4 receive los pattern r/w receive los pattern: this read/write bit-field permits the user to define the ?los defect declaration? criteria for the primary fr ame synchronizer block, as described below. 0 ? configures the primary frame sync hronizer block to declare the los defect condition if it receives a string of a specific length of consecutive zeros. 1 ? configures the primary frame sync hronizer block to declare the los defect condition if it receives a string (of a specific length) of consecutive ones. note: this bit-field is only enabled if the ?internal los enable? feature has been enabled within the primary frame synchronizer block. 3 ? 0 receive ds3 idle pattern[3:0] r/w receive ds3 idle pattern: these read/write bit-fields permit the user to specify the pattern in which the primary frame synchronizer will recognize as the ?ds3 idle pattern?. note: the bellcore gr-499-core specified value for the idle pattern is a framed repeating ?1, 1, 0, 0?? pa ttern. therefore, if the user wishes to confi g ure the ?primar y frame s y nchronizer? to declare
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 454 an ?idle pattern? when it receives this pattern, then he/she write the value [1100] into these bit-fields.
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 455 1.10.3 r eceive e3, itu-t g.751 r elated r egisters table 307: rxe3 configuration and status register # 1 - g.751 (address location= 0xn310, where n ranges from 0x02 to 0x04) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 unused rxferf algo unused rxbip-4 enable r/o r/o r/o r/w r/o r/o r/o r/w 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 ? 5 unused r/o 4 rxferf algo r/w receive ferf algorithm select: this read/write bit-field permits the user to select the ?ferf declaration? and ?clearance? criteria that will be us ed by the primary frame synchronizer block. 0 ? the primary frame synchronizer block declares the ferf/rdi defect condition if the ?a? bit-field (within the incoming e3 data-stream) is set to ?1? for 3 consecutive frames. the primary fr ame synchronizer block will clear the ferf/rdi defect condition if the ?a? bit- field is set to ?0? for 3 consecutive frames. 1 ? the primary frame synchronizer block declares the ferf/rdi defect condition if the ?a? bit-field (within the incoming e3 data-stream) is set to ?1? for 5 consecutive frames. the primary frame synchonizer block will clear the ferf/rdi defect condition if the ?a? bit- field is set to ?0? for 5 consecutive frames. note: this bit-field is only valid if the ds3/e3 framer block has been configured to operate in the e3, itu-t g.751 framing format. 3 ? 1 unused r/o 0 rxbip4 enable r/w enable bip-4 verification: this read/write bit-field permits the user to configure the primary frame synchronizer block to compute and verify the bip-4 value, within the incoming e3 data-stream. 0 ? bip-4 verification is not performed. 1 ? bip-4 verification is performed.
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 456 table 308: rxe3 configuration and status regist er # 2 - g.751 (address location= 0xn311, where n ranges from 0x02 to 0x04) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 rxlof algo lof defect condition declared oof defect condition declared los defect condition declared ais defect condition declared unused ferf/rdi defect condition declared r/w r/o r/o r/o r/o r/o r/o r/o 0 1 1 0 0 0 0 1 b it n umber n ame t ype d escription 7 rxlof algo r/w receive lof (loss of frame) defect declaration/clearance criteria select: this read/write bit-field permits the us er to select the loss of frame (lof) declaration and clearance cr iteria that the primary frame synchronizer block will use. 0 ? the primary frame synchronizer block will declare the lof defect condition if the primary frame synchronizer block resides within the oof (out-of-frame) state for 24 e3 frame periods. the primary frame synchronizer block will clear the lo f defect condition once it (the primary frame synchronizer block) resides within the ?in-frame? state for 24 e3 frame period. 1 ? the primary frame synchronizer block will declare the lof defect condition if the primary frame synchronizer block resides within the oof state for 8 e3 frame periods. the primary frame synchronizer block will clear the lof defect condition once it (the primary frame synchronizer block) resides within the ?in-frame? state for 8 e3 frame periods. 6 lof defect condition declared r/o lof (loss of frame) defect declared indicator this read-only bit-field indicates whether or not the primary frame synchronizer block is currently decl aring the lof defect condition, as described below. 0 ? indicates that the primary frame synchronizer block is not currently declaring the lof defect condition within the incoming data stream. 1 ? indicates that the prim ary frame synchronizer block is currently declaring the lof defect condition within the incoming data stream. note: this bit-field is not valid if the primary frame synchronizer block is by-passed. 5 oof defect condition declared r/o oof (out of frame) defect condition indicator this read-only bit-field indicates whether or not the primary frame synchronizer block is currently declaring the oof defect condition, as depicted below. 0 ? indicates that the primary frame synchronizer block is not currently declaring the oof defect condition with the incoming data stream. 1 ? indicates that the prim ary frame synchronizer block is currently declaring the oof defect condition with the incoming data stream. note: this bit-field is not valid if the primary frame synchronizer block is by-passed. 4 los defect condition declared r/o los (loss of signal) defect condition indicator this read-only bit-field indicates whether or not the primar y frame
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 457 declared synchronizer block is currently declaring the los defect condition, as described below. 0 ? indicates that the pr imary frame synchronizer/channel is not currently declaring the los defect condition in the incoming data stream. 1 ? indicates that the primary fram e synchronizer/channel is currently declaring the los defect condition in the incoming data stream. 3 ais defect condition declared r/o ais defect condition indicator: this read-only bit-field indicates whether or not the primary frame synchronizer block is currently declaring the ais defect condition within the incoming e3 data-stream, as described below. 0 ? indicates that the primary frame synchronizer block is not currently declaring the ais defect condition with the incoming data stream. 1 ? indicates that the prim ary frame synchronizer block is currently declaring the ais defect condition with the incoming data stream. note: this bit-field is not valid if the primary frame synchronizer block is by-passed. 2 ? 1 unused r/o 0 ferf/rdi defect condition declared r/o ferf/rdi (far-end-receive failure/remote defect indicator) defect condition indicator: this read-only bit-field indicates whether or not the primary frame synchronizer block is currently decl aring the ferf/rdi defect condition as described below. 0 ? indicates that the primary frame synchronizer block is not currently declaring the ferf/rdi defect condition. 1 ? indicates that the prim ary frame synchronizer block is currently declaring the ferf/rdi def ect condition. note: this bit-field is ignored if the prim ary frame synchronizer block is by- passed or if the user has configured the primary frame synchronizer block to compute and verify the bip-4 within the incoming e3 data-stream.
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 458 table 309: rxe3 interrupt enable register # 1 ? g.751 (address location= 0xn312, where n ranges from 0x02 to 0x04) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 unused cofa interrupt enable change in oof defect condition interrupt enable change in lof defect condition interrupt enable change in los defect condition interrupt enable change in ais defect condition interrupt enable r/o r/o r/o r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 - 5 unused r/o 4 cofa interrupt enable r/w change of framing alignment interrupt enable : this read/write bit-field permits the user to either enable or disable the ?change of framing alignment? interrupt, within the channel. if the user enables this interrupt, then the primary frame synchronizer block will generate an interrupt anyt ime it detects a change in frame alignment (e.g., the fas bits have appeared to move to a different location in the e3 data stream). 0 ? disables the ?change of framing alignment? interrupt 1 ? enables the ?change of framing alignment? interrupt 3 change in oof defect condition interrupt enable r/w change in oof defect condition interrupt enable this read/write bit-field permits the user to either enable or disable the ?change in oof (out of frame) defect condition? interrupt, within the channel. if the user enables this interrupt, then the primary frame synchronizer block will generate an interrupt in response to either of the following conditions. ? the instant that the primary frame synchronizer block declares the oof defect condition. ? the instant that the primary frame synchronizer block clears the oof defect condition. 0 ? disables the ?change in oof defect condition? interrupt. 1 ? enables the ?change in oof defect condition? interrupt. note: this bit-field is ignored if the prim ary frame synchronizer block is by- passed. 2 change in lof defect condition interrupt enable r/w change in lof defect condition interrupt enable: this read/write bit-field permits the user to either enable or disable the ?change in lof (loss of frame) defect condition? interrupt, within the channel. if the user enables this interrupt, then the primary frame synchronizer block will generate an interrupt in response to either of the following conditions. ? the instant that the primary fram e synchronizer block declares the lof defect condition. ? the instant that the primary fram e synchronizer block clears the lof defect condition. 0 ? disables the ?change in lof defect condition? interrupt. 1 ? enables the ?change in lof defect condition? interrupt.
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 459 note: this bit-field is ignored if the prim ary frame synchronizer block is by- passed. 1 change in los defect condition interrupt enable r/w change in los defect condition interrupt enable: this read/write bit-field permits the user to either enable or disable the ?change in los (loss of signal) defect condition? interrupt, within the channel. if the user enables this interrupt, then the primary frame synchronizer block will generate an interrupt in response to either of the following conditions. ? the instant that the primary fram e synchronizer block declares an los defect condition. ? the instant that the primary frame synchronizer block clears the los defect condition. 0 ? disables the ?change in los defect condition? interrupt. 1 ? enables the ?change in los defect condition? interrupt. 0 change in ais defect condition interrupt enable r/w change in ais defect condition interrupt enable: this read/write bit-field permits the user to either enable or disable the ?change in ais (alarm indication signal) defect condition? interrupt, within the channel. if the user enables this interrupt, then the primary frame synchronizer block will generate an interrupt in response to either of the following conditions. ? the instant that the primary frame synchronizer block declares the ais defect condition. ? the instant that the primary frame synchronizer block clears the ais defect condition. the ?change in ais defect condition? interrupt can be enabled or disabled, as described below. 0 ? disables the ?change in ais defect condition? interrupt. 1 ? enables the ?change in ais defect condition? interrupt. note: this bit-field is ignored if the prim ary frame synchronizer block is by- passed.
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 460 table 310: rxe3 interrupt enable register # 2 ? g.751 (address location= 0xn313, where n ranges from 0x02 to 0x04) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 unused change in ferf/rdi defect condition interrupt enable detection of bip-4 error interrupt enable detection of fas bit error interrupt enable reserved r/o r/o r/o r/o r/w r/w r/w r/o 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 - 4 unused r/o please set to ?0? (the default value) for normal operation 3 change in ferf/rdi defect condition interrupt enable r/w change in ferf/rdi defect condition interrupt enable: this read/write bit-field permits the user to either enable or disable the ?change in ferf/rdi defect condition? interrupt. if the user enables this interrupt, then the primary frame synchronizer block will generate an interrupt in response to either of the following events. ? whenever the primary frame synchr onizer block declares the ferf/rdi defect condition. ? whenever the primary frame sync hronizer block clears the ferf/rdi defect condition. the user can enable or disable this particular interrupt as described below. 0 ? disables the ?change in ferf/rdi defect condition? interrupt. 1 ? enables the ?change in ferf/rdi defect condition? interrupt. note: this bit-field is ignored if the primary frame synchronizer block is configured to verify bip-4 values within each incoming e3 frame. further, this bit-field is ignored anytime the primary frame synchronizer block is by-passed. 2 detection of bip-4 error interrupt enable r/w detection of bip-4 error interrupt enable: this read/write bit-field permits the user to either enable or disable the ?detection of bip-4 error? interrupt. if the user enables this interrupt, then the primary frame synchronizer block will generate an interrupt anytime it detects a bip-4 error, within the incoming e3 data stream. the user can enable or disable this interrupt as described below. 0 ? disables the ?detection of bip-4 error? interrupt. 1 ? enables the ?detection of bip-4 error? interrupt. note: this bit-field is only active if the receive e3 framer block has been configured to compute and verify the bip-4 values within each incoming e3 frame. this bit-field is ignored anytime the primary frame synchronizer block is by-passed. 1 detection of fas bit error interrupt enable r/w detection of fas (framing alignment signal) bit error interrupt enable: this read/write bit-field permits the user to either enable or disable the ?fas bit error? interrupt. if the user enables this interrupt, then the primary frame synchronizer block will generate an interrupt anytime it detects an fas error within the inco ming e3 data stream.
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 461 0 ? disables the ?detection of fas bit error? interrupt. 1 ? enables the ?detection of fas bit error? interrrupt. note: this bit-field is ignored if the prim ary frame synchronizer block is by- passed. 0 unused r/o please set to ?0? (the default value) for normal operation.
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 462 table 311: rxe3 interrupt status register # 1 ? g.751 (address location= 0xn314, where n ranges from 0x02 to 0x04) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 unused cofa interrupt status change in oof defect condition interrupt status change in lof defect condition interrupt status change in los defect condition interrupt status change in ais defect condition interrupt status r/o r/o r/o rur rur rur rur rur 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 - 5 unused r/o 4 cofa interrupt status rur change of framing alignment (cofa) interrupt status: this reset-upon-read bit-field indicates whether or not the ?change of framing alignment (cofa) interrupt has occurred since the last read of this register. 0 ? the ?cofa? interrupt has not occurred since the last read of this register. 1 ? the ?cofa? interrupt has occurred si nce the last read of this register. 3 change in oof defect condition interrupt status rur change of oof (out of frame) defect condition interrupt status: this reset-upon-read bit-field indicates whether or not the ?change of oof defect condition? interrupt has occurred since the last read of this register. if this interrupt is enabled, then the ds3/e3 framer block will generate an interrupt in response to either of the following condition. ? whenever the primary frame synchronizer block declares the oof defect condition. ? whenever the primary frame synchronizer block clears the oof defect condition. 0 ? indicates that the ?change in oof defect condition? interrupt has not occurred since the last read of this register. 1 ? indicates that the ?change in oof defect condition? interrupt has occurred since the last read of this register. note: the user can obtain the current st ate of the oof defect condition within the ds3/e3 framer block by reading out the state of bit 5 (oof defect declared) within the ?rxe3 configuration and status # 2 ? g.751? (address location= 0xn311). 2 change in lof defect condition interrupt status rur change of lof (loss of frame) defect condition interrupt status: this reset-upon-read bit-field indicates whether or not the ?change of lof defect condition? interrupt has occurred since the last read of this register. if this interrupt is enabled, then the ds3/e3 framer block will generate an interrupt in response to either of the following condition. ? whenever the primary frame synchr onizer block declares the lof defect condition. ? whenever the primary frame synchr onizer block clears the lof defect condition. 0 ? indicates that the ?chan g e in lof defect condition? interru p t has not
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 463 occurred since the last read of this register. 1 ? indicates that the ?change in lof de fect condition? interrupt has occurred since the last read of this register. note: the user can obtain the current st ate of the lof defect condition within the ds3/e3 framer block by reading out the state of bit 6 (lof defect declared) within the ?rxe3 configuration and status # 2 ? g.751? (address location= 0xn311). 1 change in los defect condition interrupt status rur change of los (loss of signal) defect condition interrupt status: this reset-upon-read bit-field indicates whether or not the ?change of los defect condition? interrupt has occurred since the last read of this register. if this interrupt is enabled, then the ds3/e3 framer block will generate an interrupt in response to either of the following condition. ? whenever the primary frame synchron izer block declares the los defect condition. ? whenever the primary frame synchron izer block clears the los condition. 0 ? indicates that the ?change of lo s defect condition? interrupt has not occurred since the last read of this register. 1 ? indicates that the ?change of lo s defect condition? interrupt has occurred since the last read of this register. note: the user can obtain the current st ate of the los defect condition within the ds3/e3 framer block by reading out the state of bit 4 (los defect declared) within the ?rxe3 configuration and status # 2 ? g.751? (address location= 0xn311). 0 change in ais defect condition interrupt status rur change of ais defect condition interrupt status: this reset-upon-read bit-field indicates whether or not the ?change of ais defect condition? interrupt has occurred since the last read of this register. if this interrupt is enabled, then the ds3/e3 framer block will generate an interrupt in response to either of the following condition. ? whenever the primary frame synchronizer block declares the ais defect condition. ? whenever the primary frame synchron izer block clears the ais defect condition. 0 ? indicates that the ?change of ais defect condition? interrupt has not occurred since the last read of this register. 1 ? indicates that the ?change of ais de fect condition? interrupt has occurred since the last read of this register. note: the user can obtain the current st ate of the ais defect condition within the ds3/e3 framer block by reading out the state of bit 3 (ais defect declared) within the ?rxe3 configuration and status # 2 ? g.751? (address location= 0xn311).
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 464 table 312: rxe3 interrupt status register # 2 ? g.751 (address location= 0xn315, where n ranges from 0x02 to 0x04) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 unused change of ferf/rdi defect condition interrupt status detection of bip-4 error interrupt status detection of fas bit error interrupt status reserved r/o r/o r/o r/o rur rur rur r/o 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 ? 4 unused r/o 3 change of ferf/rdi defect condition interrupt status rur change of ferf/rdi defect condi tion interrupt ? primary frame synchronizer block: this reset-upon-read bit-field indicates whether or not the ?change in ferf/rdi condition? interrupt has o ccurred since the last read of this register. the primary frame synchronizer block will generate this interrupt in response to either of the following events. ? whenever the primary frame synchron izer block declares the ferf/rdi defect condition. ? whenever the primary frame synchronizer block clears the ferf/rdi defect condition. 0 ? indicates that the ?change in ferf /rdi defect condition? interrupt has not occurred since the last read of this register. 1 ? indicates that the ?change in ferf /rdi defect condition? interrupt has occurred since the last read of this register. 2 detection of bip-4 error interrupt status rur detection of bip-4 error interrupt ? primary frame synchronizer block: this ?reset-upon-read? bit-field indicates whether or not the ?detection of bip-4 error? interrupt has occurred sinc e the last read of this register. the primary frame synchronizer block wi ll generate this interrupt anytime it detects bip-4 errors within the incoming e3 data-stream. 0 ? indicates that the ?detection of bip-4 error? interrupt has not occurred since the last read of this register. 1 ? indicates that the ?detection of bip-4 error? interrupt has occurred since the last read of this register. 1 detection of fas bit error interrupt status rur detection of fas bit error interrupt ? primary frame synchronizer block: this ?reset-upon-read? bit-field indicates whether or not the ?detection of fas bit error? interrupt has occurred since the last read of this register. the primary frame synchronizer block wi ll generate this interrupt anytime it detects fas bit errors within the incoming e3 data-stream. 0 ? indicates that the ?detection of fas bit error? interrupt has not occurred since the last read of this register. 1 ? indicates that the ?detection of fas bit error? interru p t has occurred
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 465 since the last read of this register. 0 unused r/o
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 466 table 313: rxe3 lapd control register ? g.751 (address location= 0xn318, where n ranges from 0x02 to 0x04) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 rxlapd any message check disable unused receive lapd enable receive lapd interrupt enable receive lapd interrupt status r/w r/w r/o r/o r/o r/w r/w rur 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 rxlapd any r/w receive lapd ? any kind: this read/write bit-field permits the user to configure the receive lapd controller sub-block to receive any kind of lapd message (or hdlc message) with a size of 82 bytes or less. if the user implements this option, then the receive lapd controller sub-block will be capable of receiving any kind of hdlc message (with any value of header bytes). the only restriction is that the size of the hdlc messa ge must not exceed 82 bytes. 0 ? does not invoke this ?any kind of hdlc message? feature. in this case, the receive lapd controller sub-block will only receive hdlc messages that contains the bellcore gr-499-core values for sapi and tei. 1 - invokes this ?any kind of hdlc message? feature. in this case, the receive lapd controller sub-block will be able to receive hdlc messages that contain any header byte values. note: this bit-field is ignored if the prim ary frame synchronizer block is by- passed. the user can determine the size (or byte count) of the most recently received lapd/pmdl message, by reading the contents of the ?receive lapd byte count? register (address location= 0xn384). 6 message check disable r/w message check disable: this read/write bit-field permits the user to either enable or disable the new message comparison logic. if the user disables the new message comparison logic, then every message received would generate an interrupt. 0 ? enables the new message comparison logic 1 ? disables the new message comparison logic 5 ? 3 unused r/o 2 receive lapd enable r/w receive lapd controller sub-block enable: this read/write bit-field permits the user to either enable or disable the receive lapd controller sub-block within the channel. if the user enables the receive lapd controller sub-block, then it will immediately begin extracting out and monitoring the data (being carried via the ?n? bits) within the incoming e3 data stream. 0 ? enables the receive lapd controller sub-block. 1 ? disables the receive lapd controller sub-block. note: this bit-field is ignored if the prim ary frame synchronizer block is by- passed. 1 receive lapd interru p t r/w receive lapd message interrupt enable: this read/write bit-field permits the user to either enable or disable the ?r i lapd m ? i t t if th bl thi i t t th th
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 467 enable ?receive lapd message? interrupt. if the user enables this interrupt, then the channel will generate an interrupt, anyt ime the receive lapd controller sub- block receives a new pmdl message. 0 ? disables the ?receive lapd message? interrupt. 1 ? enables the ?receive lapd message? interrupt. note: this bit-field is ignored if the prim ary frame synchronizer block is by- passed. 0 receive lapd interrupt status rur receive lapd message interrupt status: this reset-upon-read bit-field indicates whether or not the ?receive lapd message? interrupt has occurred since t he last read of this register. 0 ? ?receive lapd message? interrupt has not occurred since the last read of this register. 1 ? ?receive lapd message? interrupt has occurred since the last read of this register. note: this bit-field is ignored if the prim ary frame synchronizer block is by- passed.
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 468 table 314: rxe3 lapd status register ? g.751 (address location= 0xn319, where n ranges from 0x02 to 0x04) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 unused rxabort rxlapdtype[1:0] rxcr type rxfcs error end of message flag present r/o r/o r/o r/o r/o r/o r/o r/o 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 unused r/o 6 rxabort r/o receive abort sequence indicator: this read-only bit-field indicates whether or not the receive lapd controller sub-block has received an abort sequence (e.g., a string of seven consecutive ?0s?), as described below. 0 ? indicates that the receive l apd controller sub-block has not received an abort sequence. 1 ? indicates that the receive lapd controller sub-block has received an abort sequence. note: once the receive lapd controlller sub-block receives an abort sequence, it will set this bit-field ?high?, until it receives another lapd messages. 5 ? 4 rxlapdtype[1:0] r/o receive lapd message type indicator: these two read-only bits indicate the type of lapd message that is residing within the receive lapd message buffer. the relationship between the content of these two bit-fields and the corresponding message type is presented below. rxlapdtype[1:0] message type 0 0 cl path identification 0 1 idle signal identification 1 0 test signal identification 1 1 itu-t path identification 3 rxcr type r/o received c/r value: this read-only bit-field indicates the value of the c/r bit (within one of the header bytes) of the most recently received lapd message. 2 rxfcs error r/o receive frame check sequence (fcs) error indicator: this read-only bit-field indicates whether or not the most recently received lapd message frame contained an fcs error. 0 ? indicates that the most rec ently received lapd message frame does not contain an fcs error. 1 ? indicates that the most rec ently received lapd message frame does contain an fcs error. 1 end of message r/o end of message indicator
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 469 this read-only bit-field indicates whether or not the receive lapd controller sub-block has received a complete lapd message, as described below. 0 ? indicates that the receive lapd controller sub-block is currently receiving a lapd message, but has not received the complete message. 1 ? indicates that the receive lapd controller sub-block has received a completed lapd message. note: once the receive lapd controller sub-block sets this bit-field ?high?, this bit-field will remain high, until the receive lapd controller sub-block begins to receive a new lapd message. 0 flag present r/o receive flag sequence indicator: this read-only bit-field indicates whether or not the receive lapd controller sub-block is currently receiving the flag sequence (e.g., a continuous stream of 0x7e octets within the data link channel) as described below. 0 ? indicates that the receive la pd controller sub-block is not currently receiving the flag sequence octet. 1 ? indicates that the receive lapd controller sub-block is currently receiving the flag sequence octet. table 315: rxe3 service bits register ? g.751 (address location= 0xn31a, where n ranges from 0x02 to 0x04) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 unused rxa rxn r/o r/o r/o r/o r/o r/o r/o r/o 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 - 2 unused r/o 1 rxa r/o received a bit value: this read-only bit-field reflects the value of the ?a? bit, within the most recently received e3 frame. note: this register bit pertains to the ?a? bit that has been received by the primary frame synchronizer block. 0 rxn r/o received n bit value: this read-only bit-field refl ects the value of the ?n? bi t, within the most recently received e3 frames. note: this register bit pertains to the ?n? bit that has been received by the primary frame synchronizer block.
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 470 1.10.4 r eceive e3, itu-t g.832 r elated r egisters table 316: rxe3 configuration and status register # 1 ? g.832 (address location= 0xn310, where n ranges from 0x02 to 0x04) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 rxpldtype[2:0] rxferf algo. rxtmark algo rxpldtypeexp[2:0] r/o r/o r/o r/w r/w r/w r/w r/w 0 1 0 0 0 0 1 0 b it n umber n ame t ype d escription 7 - 5 rxpldtype[2:0] r/o received pld (payload) type[2:0]: these three read-only bit-fields reflect the value of the payload type bits, within the ma byte of the most recently received e3 frame. 4 rxferf algo r/w receive ferf/rdi defect decl aration/clearance algorithm: this read/write bit-field permits the user to select a ?ferf/rdi defect declaration and clearance? algorithm, as indicated below. 0 ? configures the primary frame synchronizer block to declare the ferf/rdi defect condition anytime that it receives the ferf/rdi indicator in 3 consecutive e3 frames. additionally, this same setting will also configure the primary frame synchronizer block to clear the ferf/rdi defect condition if it no longer receives the ferf/rdi indicator (within the e3 data-stream) for 3 consecutive e3 frames. 1 ? configures the primary frame synchronizer block to declare the ferf/rdi defect conditio n anytime it receives the ferf/rdi indicator (within the incoming e3 data-stream) in 5 consecutive e3 frames. additionally, this same seting will also configure the primary frame synchronizer block to clear the fe rf/rdi defect condition anytime it ceases to receive the ferf/rdi indi cator for 5 consecutive e3 frames. 3 rxtmark algo r/w receive timing marker validation algorithm: this read/write bit-field permits the user to select the ?receive timing marker validation? algorithm, as indicated below. 0 ? the timing marker will be validated if it is of the same state for three (3) consecutive e3 frames. 1 ? the timing marker will be validated if it is of the same state for five (5) consecutive e3 frames. 2 - 0 rxpldtypexp[2:0] r/w receive pld (payload) type ? expected: this read/write bit-field permits the user to specify the ?expected value? for the payload type, within the ma bytes of each incoming e3 frame. if the primary frame synchron izer block receives a payload type that differs then what has been written into these register bits, then it will generate the ?payload type mismatch? interrupt.
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 471 table 317: rxe3 configuration and status register # 2 ? g.832 (address location= 0xn311, where n ranges from 0x02 to 0x04) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 rxlof algo lof defect condition declared - primary frame synchronizer block oof defect condition declared ? primary frame synchronizer block los defect condition declared ? primary frame synchronizer block ais defect condition declared ? primary frame synchronizer block rxpld unstab rxtmark ferf/rdi defect condition declared ? primary frame synchronizer block r/w r/o r/o r/o r/o r/o r/o r/o 0 1 1 0 0 1 1 1 b it n umber n ame t ype d escription 7 rxlof algo r/w receive lof (loss of frame) defect declaration algorithm: this read/write bit-field permits the us er to select a ?receive lof defect declaration? algorithm, as indicated below. 0 ? configures the primary frame synchronizer block to declare the lof defect condition after it has resided with in the ?oof? (out of frame) condition for 24 e3 frame periods. 1 ? configures the primary frame synchronizer block to declare the lof defect condition after it has resided within the ?oof? condition for 8 e3 frame periods. 6 lof defect condition declared r/o lof (loss of frame) defect c ondition indicator ? primary frame synchronizer block: this read-only bit-field indicates whether or not the primary frame synchronizer block is currently declarin g the lof defect condition, as indicated below. 0 ? indicates that the primary frame synchronizer block is not currently declaring the lof defect condition. 1 ? indicates that the primary frame sync hronizer block is currently declaring the lof defect condition. 5 oof defect condition declared r/o oof (out of frame) defect condi tion indicator ? primary frame synchronizer block: this read-only bit-field indicates whether or not the primary frame synchronizer is currently declaring an out of frame (oof) defect condition, as indicated below. 0 ? indicates that the primary frame synchronizer block is not currently declaring the oof defect condition. 1 ? indicates that the primary frame sync hronizer block is currently declaring the oof defect condition. note: the primary frame synchronizer bl ock will declare the ?oof? defect condition anytime it detects fa1 or fa2 byte errors within four (4) consecutive ?incoming? e3 frames. 4 los detect condition declared r/o los (loss of signal) defect c ondition indicator ? primary frame synchronizer block: this read-only bit-field indicates whether or not the primary frame s y nchronizer block is currentl y declarin g the los ( loss of si g nal ) defect
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 472 condition, as indicated below. 0 ? indicates that the primary frame synchronizer block is not currently declaring the los defect condition. 1 ? indicates that the primary frame sy nchronizer block is currently declaring the los defect condition. 3 ais defect condition declared r/o ais defect condition indicator ? primary frame synchronizer block: this read-only bit-field indicates whether or not the primary frame synchronizer block is currently decla ring the ais defect condition within the incoming e3 data stream; as indicated below. 0 ? indicates that the primary frame synchronizer block is not currently declaring the ais defect condition within the incoming e3 data stream. 1 ? indicates that the primary frame sync hronizer block is currently declaring the ais defect condition within the incoming e3 data stream. note: the primary frame synchronizer block will declare an ?ais? condition if it detects 7 or less ?0s? within two consecutive ?incoming? e3 frames. 2 rxpld unstab r/o receive payload-type unstable indicator: this read-only bit-field indicates whether or not the payload type (within the ma bytes of each incoming e3 frame) has been consistent in the last 5 frames, as indicated below. 0 ? the payload type value has been cons istent for at least 5 consecutive e3 frames. 1 ? the payload type value has not been consistence for the last 5 e3 frames. 1 rxtmark r/o received (validated) timing marker: this read-only bit-field indicates the value of the most recently validated ?timing marker?. 0 ferf/rdi defect condition declared r/o ferf/rdi (far-end-receive failure) de fect condition indicator ? primary frame synchronizer block: this read-only bit-field indicates whether or not the primary frame synchronizer block is currently declar ing the ferf/rdi def ect condition, as indicated below. 0 ? indicates that the primary frame synchronizer block is not currently declaring the ferf/rdi defect condition. 1 ? indicates that the primary frame sy nchronizer block is currently declaring the ferf/rdi condition.
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 473 table 318: rxe3 interrupt enable register # 1 ? g.832 (address location= 0xn312, where n ranges from 0x02 to 0x04) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 unused change in ssm msg interrupt enable change in ssm oos interrupt enable cofa interrupt enable change in oof defect condition interrupt enable change in lof defect condition interrupt enable change in los defect condition interrupt enable change in ais defect condition interrupt enable r/o r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 unused r/o 6 change in ssm msg interrupt enable r/w change of synchronization status message (ssm) condition interrupt enable: this read/write bit-field permits the user to either enable or disable the ?change in ssm message? interrupt, as indicated below. 0 ? disables the ?change in ssm message? interrupt. 1 ? enables the ?change of ssm message? interrupt. in this configuration, the primary frame synchronizer block will generate an interrupt anytime it receives a new (or different) ssm message in the incoming e3 data-stream. 5 change in ssm oos state interrupt enable r/w change of ssm oos (out of sequence) condition interrupt enable: this read/write bit-field permits the user to either enable or disable the ?change of ssm oos condition? interrupt, as indicated below. 0 ? disables the ?change of ssm oos condition? interrupt. 1 ? enables the ?change of ssm oos condition? interrupt. in this configuration, the primary frame synchronizer block will generate an interrupt under the following conditions. ? whenever the primary frame synchronizer block declares the ssm oos condition. ? when the primary frame synchronizer block clears the ssm oos condition. 4 cofa interrupt enable r/w change of framing alignment interrupt enable: this read/write bit-field permits the user to either enable or disable the ?change of framing alignment? condition interrupt, as indicated below. 0 ? disables the ?change of framing alignment? interrupt. 1 ? enables the ?change of framing alignment? interrupt. 3 change in oof defect condition interrupt enable r/w change of oof (out of frame) defect condition interrupt enable: this read/write bit-field permits the user to either enable or disable the ?change of oof defect condition? interrupt, as indicated below.
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 474 0 ? disables the ?change of oof defect condition? interrupt. 1 ? enables the ?change of oof defect condition? interrupt. in this configuration setting, the primary frame synchronizer block will generate an interrupt under the following conditions. ? whenever the primary frame synchronizer block declares the oof defect condition. ? whenever the primary frame synchronizer block clears the oof defect condition. 2 change in lof defect condition interrupt enable r/w change of lof (loss of frame) defect condition interrupt enable: this read/write bit-field permits the user to either enable or disable the ?change of lof defect condition? interrupt, as indicated below. 0 ? disables the ?change of lof defect condition? interrupt. 1 ? enables the ?change of lof defect condition? interrupt. in this configuration, the primary frame synchronizer block will generate an interrupt under the following conditions. ? whenever the primary frame synchronizer block declares the lof defect condition. ? whenever the primary frame synchronizer block clears the lof defect condition. 1 change in los defect condition interrupt enable r/w change of los (loss of signal) defect condition interrupt enable: this read/write bit-field permits the user to either enable or disable the ?change of los defect condition? interrupt, as indicated below. 0 ? disables the ?change of los defect condition? interrupt. 1 ? enables the ?change of los defect condition? interrupt. in this configuration, the primary frame synchronizer block will generate an interrupt under the following conditions. ? whenever the primary frame synchronizer block declares the los defect condition. ? whenever the primary frame synchronizer block clears the los defect condition. 0 change of ais defect condition interrupt enable r/w change of ais (alarm indication signal) defect condition interrupt enable: this read/write bit-field permits the user to either enable or disable the ?change of ais defect condition? interrupt, as indicated below. 0 ? disables the ?change of ais defect condition? interrupt. 1 ? enables the ?change of ais defect condition? interrupt. in this configuration, the primary frame synchronizer block will generate an interrupt under the following conditions. ? whenever the primary frame synchronizer block declares the ais defect condition. ? whenever the primary frame synchronizer block clears the ais defect condition.
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 475 table 319: rxe3 interrupt enable register # 2 ? g.832 (address location= 0xn313, where n ranges from 0x02 to 0x04) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 unused change in receive trail- trace message interrupt enable reserved detection of febe event interrupt enable change in ferf/rdi defect condition interrupt enable detection of bip-8 error interrupt enable detection of framing byte error interrupt enable rxpld mismatch interrupt enable r/o r/w r/o r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 unused r/o 6 change in receive trail-trace message interrupt enable r/w change in receive trail-trace message interrupt enable: this read/write bit-field permits t he user to either enable or disable the ?change in receive trail-trace message? interrupt, as indicated below. 0 ? disables the ?change in receive trail-trace message? interrupt. 1 ? enables the ?change in receive trail-trace message? interrupt. in this mode, the primary frame synchronizer block will generate an interrupt anytime it receives a differ ent trail-trace message, then what it had been receiving. 5 unused r/w 4 detection of febe event interrupt enable r/w detection of febe interrupt enable: this read/write bit-field permits t he user to either enable or disable the ?detection of febe? interrupt, as indicated below. 0 ? disables the ?detection of febe? interrupt. 1 ? enables the ?det ection of febe? interrupt. in this mode, the primary frame synchronizer block will generate an interrupt anytime it detects a febe (far-end block error) indicator in the incoming e3 data-stream. 3 change in ferf/rdi defect condition interrupt enable r/w change in ferf defect condition interrupt enable: this read/write bit-field permits t he user to either enable or disable the change in ferf/rdi defect cond ition interrupt, as indicated below. 0 ? disables the ?change in ferf/rdi defect condition? interrupt. 1 ? enables the ?change in ferf/rdi defect condition? interrupt. in this mode, the primary frame synchronizer block will generate an interrupt, in response to either of the following conditions. ? whenever the primary frame synchronizer block declares the ferf/rdi defect condition. ? whenever the primary frame synchronizer block clears the ferf/rdi defect condition. 2 detection of bip-8 error interrupt enable r/w detection of bip-8 error interrupt enable: this read/write bit-field permits t he user to either enable or disable the ?detection of bip-8 error? interrupt, as indicated below.
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 476 0 ? disables the ?detection of bip-8 error? interrupt. 1 ? enables the ?detection of bip-8 error? interrupt. in this mode, the primary frame synchronizer block will generate an interrupt anytime it detects a bip-8 error in the incoming e3 data-stream. 1 detection of framing byte error interrupt enable r/w detection of framing byte interrupt enable: this read/write bit-field permits t he user to either enable or disable the ?detection of framing byte e rror? interrupt, as indicated below. 0 ? disables the ?detection of framing byte error? interrupt. 1 ? enables the ?detection of framing byte error? interrupt. in this mode, the primary frame synchronizer blo ck will generate an interrupt anytime it detects a fa1 or fa2 byte error in the incoming e3 data stream. 0 rxpld mis interrupt enable received payload type mismatch interrupt enable: this read/write bit-field permits t he user to either enable or disable the ?receive payload type mismatch? interrupt, as indicated below. 0 ? disables the ?received payload type mismatch? interrupt. 1 ? enables the ?received payload type mismatch? interrupt. in this mode, the primary frame synchronizer block will generate an interrupt anytime it receives a ?payload type? value (within the ma byte) that differs from that written into the ?rxpldexp[2:0]? bit-fields.
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 477 table 320: rxe3 interrupt status register # 1 ? g.832 (address location= 0xn314, where n ranges from 0x02 to 0x04) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 unused change in ssm msg interrupt status change in ssm oos interrupt status cofa interrupt status change in oof defect condition interrupt status change in lof defect condition interrupt status change in los defect condition interrupt status change in ais defect condition interrupt status r/o rur rur rur rur rur rur rur 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 unused r/o 6 change in ssm msg interrupt status rur change in ssm (synchronization status message) interrupt status: this reset-upon-read bit-field indicates whether or not the ?change in ssm message? interrupt has occurred since the last read of this register. if this interrupt is enabled, t hen the primary frame synchronizer block will generate an interrupt, anytime it detects a change in the ?ssm[3:0]? value that it has received via the incoming e3 data-stream. 0 ? indicates that the ?change in ssm message? interrupt has not occurred since the last read of this register. 1 ? indicates that the ?change in ssm message? interrupt has occurred since the last read of this register. note: the user can obtain the newly received value for ?ssm? by reading out the contents of bits 3 through 1 (rxssm[3:0]) within the ?r xe3 ssm register ? g.832? (address location= 0xn32c). 5 change in ssm oos state interrupt status rur change in ssm oos (out of sequence) state interrupt status: this reset-upon-read bit-field indicates whether or not the ?change in ssm oos state? interrupt has occurred since the last read of this register. if this interrupt is enabled, t hen the primary frame synchronizer block will generate the ?change in ssm oos state? interrupt will response to the following events. ? whenever the primary frame synchronizer block declares the ssm oos condition. ? whenever the primary frame synchronizer block clears the ssm oos condition. 0 ? indicates that the ?change in ssm oos condition? interrupt has not occurred since the la st read of this register. 1 ? indicates that the ?change in ssm oos condition? interrupt has occurred since the last read of this register. 4 cofa interrupt status rur cofa interrupt status: this reset-upon-read bit-field indicates whether or not the ?cofa? ( chan g e of framin g ali g nment ) interru p t has occurred
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 478 since the last read of this register. if this interrupt is enabled, t hen the primary frame synchronizer block will generate an interrupt anytime it detects a new ?framing alignment? with the incoming e3 data-stream. 0 ? indicates that the ?cofa interrupt? has not occurred since the last of this register. 1 ? indicates that the ?cofa interrupt? has occurred since the last read of this register. 3 change in oof defect condition interrupt status rur change in oof (out of frame) defect condition interrupt status: this reset-upon-read bit-field indicates whether or not the ?change in oof defect condition? interrupt has occurred since the last read of this register. if this interrupt is enabled, t hen the primary frame synchronizer block will generate the ?change in oof defect condition? interrupt in response to the following events. ? whenever the primary frame synchronizer block declares the ?oof condition?. ? whenever the primary frame synchronizer block clears the ?oof condition?. 0 ? indicates that the ?change in oof defect condition interrupt? has not occurred since the last of this register. 1 ? indicates that the ?change in oof defect condition interrupt? has occurred since the last read of this register. note: the user can determine the cu rrent state of the ?ais condition? by reading out the contents of bit 5 (oof defect declared) within the ?rxe3 configuration and status register # 2 ? g.832? (address location= 0xn311). 2 change in lof defect condition interrupt status rur change in lof (loss of frame) defect condition interrupt status: this reset-upon-read bit-field indicates whether or not the ?change in lof defect condition interrupt has occurred since the last read of this register. if this interrupt is enabled, t hen the primary frame synchronizer block will generate the ?change in lof defect condition? interrupt will occur in response to the following events. ? whenever the primary frame synchronizer block declares the ?lof defect condition?. ? when the primary frame synchronizer block clears the ?lof defect condition?. 0 ? indicates that the ?change in lof defect condition interrupt? has not occurred since the last of this register. 1 ? indicates that the ?change in lof defect condition interrupt? has occurred since the last read of this register. note: the user can determine the cu rrent state of the ?lof condition? by reading out the contents of bit 6 (lof defect declared) within the ?rxe3 configuration and status register # 2 ? g.832? (address location= 0xn311). 1 change in los defect rur change in los (loss of signal) defect condition interrupt
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 479 condition interrupt status status: this reset-upon-read bit-field indicates whether or not the ?change in los defect condition? interrupt has occurred since the last read of this register. if this interrupt is enabled, t hen the primary frame synchronizer block will generate the ?change in los defect condition? interrupt will occur in response to the following events. ? whenever the primary frame synchronizer block declares the ?los defect condition?. ? when the primary frame synchronizer block clears the ?los defect condition?. 0 ? indicates that the ?change in los defect condition interrupt? has not occurred since the last of this register. 1 ? indicates that the ?change in los defect condition interrupt? has occurred since the last read of this register. note: the user can determine the cu rrent state of the ?los condition? by reading out the contents of bit 4 (los defect declared) within the ?rxe3 configuration and status register # 2 ? g.832? (address location= 0xn311). 0 change in ais defect condiiton interrupt status rur change in ais defect condition interrupt status: this reset-upon-read bit-field indicates whether or not the ?change in ais defect condition? interrupt has occurred since the last read of this register. if this interrupt is enabled, t hen the primary frame synchronizer block will generate the ?change in ais defect condition? interrupt will occur in response to the following events. ? whenever the primary frame synchronizer block declares the ?ais condition?. ? whenever the primary frame synchronizer block clears the ?ais condition?. 0 ? indicates that the ?change in ais defect condition interrupt? has not occurred since the last of this register. 1 ? indicates that the ?change in ais defect condition interrupt? has occurred since the last read of this register. note: the user can determine the cu rrent state of the ?ais condition? by reading out the contents of bit 3 (ais defect declared) within the ?rxe3 configuration and status register # 2 ? g.832? (address location= 0xn311).
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 480 table 321: rxe3 interrupt status register # 2 ? g.832 (address location= 0xn315, where n ranges from 0x02 to 0x04) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 unused change in receive trail-trace message interrupt status reserved detection of febe/rei event interrupt status change in ferf/rdi defect condition interrupt status detection of bip-8 error interrupt status detection of framing byte error interrupt status rxpld mismatch interrupt status r/o rur r/o rur rur rur rur rur 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 unused r/o 6 change in receive trail-trace message interrupt status rur change in receive trail-trace message interrupt status: this reset-upon-read bit-field indicates whether or not the ?change in receive trail-trace message? interrupt has occurred since the last read of this register. if this interrupt is enabled, then the primary frame synchronizer block will generate an interrupt anytime it receives a trail-trace message, that is different from that of the previously received message. 0 ? indicates that the ?change in receive trail-trace message? interrupt has not occurred since the last read of this register. 1 ? indicates that the ?change in receive trail-trace message? interrupt has occurred since the last read of this register. note: the user can obtain the value of the most recently received trail-trace message by reading out the contents of the ?rxe3 trail-trace message byte-0? through ?rxe3 trail-trace message byte-15? registers (address location= 0xn31c through 0xn32b). 5 unused r/o 4 detection of febe/rei event interrupt status rur detection of febe/rei event interrupt status: this reset-upon-read bit-field indicates whether or not the ?detection of febe/rei event? inte rrupt has occurred since the last read of this register. if this interrupt is enabled, then the primary frame synchronizer block will generate an interrupt anytime is detects a febe/rei event in the incoming e3 data-stream. 0 ? indicates that the ?detection of febe/rei event? interrupt has not occurred since the last read of this register. 1 ? indicates that the ?detection of febe/rei event? interrupt has occurred since the last read of this register. 3 change in ferf/rdi defect condition interrupt status rur change in ferf/rdi (far-end r eceive failure) defect condition interrupt status: this reset-upon-read bit-field indicates whether or not the ?change in ferf/rdi defect condition? in terrupt has occurred since the last read of this register. if this interru p t is enabled, then the primar y frame s y nchronizer block
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 481 will generate an interrupt in response to the following events. ? whenever the primary frame synchronizer block declares the ferf/rdi defect condition. ? whenever the primary frame synchronizer block clears the ferf/rdi condition. 0 ? indicates that the ?change in fe rf/rdi defect condition? interrupt has not occurred since the la st read of this register. 1 ? indicates that the ?change in fe rf/rdi defect condition? interrupt has occurred since the last read of the register. note: the user can obtain the stat e of the ferf/rdi defect condition, by reading out th e contents of bit 0 (ferf/rdi defect declared) within the ?rxe3 configuration and status register # 2 ? g.832? (address location= 0xn311). 2 detection of bip-8 error interrupt status rur detection of bip-8 error interrupt status: this reset-upon-read bit-field indicates whether or not the ?detection of bip-8 error? interrupt has occurred since the last read of this register. if this interrupt is enabled, then the primary frame synchronizer block will generate an interrupt anytime is detects a bip-8 error in the incoming e3 data-stream. 0 ? indicates that the ?detection of bip-8 error? interrupt has not occurred since the last read of this register. 1 ? indicates that the ?detection of bip-8 error? interrupt has occurred since the last read of this register. 1 detection of framing byte error interrupt status rur detection of framing byte error interrupt status: this reset-upon-read bit-field indicates whether or not the ?detection of framing byte error? interrupt has occurred since the last read of this register. if this interrupt is enabled, then the primary frame synchronizer block will generate an interrupt anytime is detects an error in either the fa1 or fa2 byte, within the in coming e3 data-stream. 0 ? indicates that the ?detection of framing byte error? interrupt has not occurred since the last read of this register. 1 ? indicates that the ?detection of framing byte error? interrupt has occurred since the last read of this register. 0 detection of pld type mismatch interrupt status rur detection of payload type mismatch interrupt status: this reset-upon-read bit-field indicates whether or not the ?detection of payload type mismatch? interrupt has occurred since the last read of this register. if this interrupt is enabled, then the primary frame synchronizer block will generate an interrupt anytime it receives an e3 data-stream that contains a ?rxpldtype[2:0]? that is different from the ?rxpldtypeexp[2:0]? value. 0 ? indicates that the ?detection of payload type mismatch? interrupt has not occurred since the la st read of this register. 1 ? indicates that the ?detection of payload type mismatch? interrupt has occurred since the last read of this register. note: the user can obtain the contents of the most recently received payload type by reading out the contents of bits 7 through 5 ( rxpldt yp e [ 2:0 ]) within the ?rxe3 confi g uration and status
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 482 register # 1 ? g.832? (address location= 0xn310).
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 483 table 322: rxe3 lapd control register ? g.832 (address location= 0xn318, where n ranges from 0x02 to 0x04) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 rxlapd any message check disable unused receive lapd from nr byte receive lapd enable receive lapd interrupt enable receive lapd interrupt status r/w r/w r/o r/o r/w r/w r/w rur 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 rxlapd any r/w receive lapd ? any kind: this read/write bit-field permits the user to configure the receive lapd controller sub-block (within the primary frame synchronizer block) to receive any kind of lapd message (or hdlc message) with a size of 82 bytes or less. if the user implements this opt ion, then the receive lapd controller sub-block will be capable of receiving any kind of hdlc message (with any value of header bytes). the only restri ction is that the size of the hdlc message must not exceed 82 bytes. 0 ? does not invoke this ?any kind of hdlc message? feature. in this case, the receive lapd controller sub-block will only receive hdlc messages that contains the bellcore gr-499-core values for sapi and tei. 1-invokes this ?any kind of hdlc message? feature. in this case, the receive lapd controller sub-block will be able to receive hdlc messages that contain any header byte values. note: this bit-field is ignored if the prim ary frame synchronizer block is by- passed. the user can determine the size (or byte count) fo the most recently received lapd/pmdl message, by reading the contents of the ?rxlapd byte count? register (address location= 0xn384). 6 message check disable r/w message check disable: this read/write bit-field permits the user to either enable or disable the new message comparison logic. if the user disables the new message comparison logic, then every message received would generate an interrupt. 0 ? enables the new message comparison logic 1 ? disables the new message comparison logic 6 ? 4 unused r/o 3 receive lapd from nr byte r/w receive lapd message from nr byte select: this read/write bit-field permits the user to configure the receive lapd controller sub-block to extract out the pmdl data from the nr or gc byte, within the incoming e3 data stream. 0 ? configures the receive lapd controlller sub-block to extract pmdl information from the gc byte, with in the incoming e3 data stream. 1 ? configures the receive lapd controller sub-block to extract pmdl information from the nr byte, within the incoming e3 data stream. note: this bit-field is ignored if the prim ary frame synchronizer block is by- passed.
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 484 2 receive lapd enable r/w receive lapd controller block enable: this read/write bit-field permits the user to either enable or disable the receive lapd controller sub-block (w ithin the primary frame synchronizer block). if the user enables the receive lapd controller sub-block, then it will immediately begin extracting out and m onitoring the data that is being carried by either the nr or gc bytes (dependi ng upon user configuration) within the incoming e3 data stream. 0 ? disables the receive lapd controller sub-block. 1 ? enables the receive lapd controller sub-block. note: this bit-field is ignored if the prim ary frame synchronizer block is by- passed. 1 receive lapd interrupt enable r/w receive lapd message interrupt enable: this read/write bit-field permits the user to either enable or disable the ?receive lapd message? interrupt. if the user enables this interrupt, then the receive lapd controller sub-block (w ithin the primary frame synchronizer block) will generate an interrupt, anytime the receive lapd controller sub- block receives a new lapd/pmdl message. 0 ? disables the ?receive lapd message? interrupt. 1 ? enables the ?receive lapd message? interrupt. note: this bit-field is ignored if the receive lapd controller sub-block is disabled. 0 receive lapd interrupt status rur receive lapd message interrupt status: this reset-upon-read bit-field indicates whether or not the ?receive lapd message? interrupt has occurred since t he last read of this register. 0 ? indicates that the ?receive lapd message? interrupt has not occurred since the last read of this register. 1 ? indicates that the ?receive lapd message? interrupt has occurred since the last read of this register. note: this bit-field is ignored if the receive lapd controller sub-block is disabled.
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 485 table 323: rxe3 lapd status register ? g.832 (address location= 0xn319, where n ranges from 0x02 to 0x04) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 unused rxabort rxlapdtype[1:0] rxcr type rxfcs error end of message flag present r/o r/o r/o r/o r/o r/o r/o r/o 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 unused r/o 6 rxabort r/o receive abort sequence indicator: this read-only bit-field indicates whether or not the most recently received lapd/pmdl message was interrupted by an abort sequence (e.g., a string of seven consecutive ?1s?) as described below. 0 ? indicates that the receive l apd controller sub-block has not received an abort sequence within the most recently lapd/pmdl message. 1 - indicates that the receive lapd controller sub-block has received an abort sequence within the most recently received lapd/pmdl message. note: once the receive lapd contro ller sub-block receives an abort sequence, it will set this bit-field ?high?, until it receives another lapd message. 5 ? 4 rxlapdtype[1:0] r/o receive lapd message type indicator[1:0]: these two read-only bits indicate the type of lapd message that is residing within the receive lapd message buffer. the relationship between the content of these two bit-fields and the corresponding message type is presented below. rxlapdtype[1:0] message type 0 0 cl path identification 0 1 idle signal identification 1 0 test signal identification 1 1 itu-t path identification 3 rxcr type r/o received c/r value: this read-only bit-field indicates the value of the c/r bit (within one of the header bytes) of the most recently received lapd message. 2 rxfcs error r/o receive frame check sequence (fcs) error indicator: this read-only bit-field indicates whether or not the most recently received lapd message frame contained an fcs error as described below. 0 ? indicates that the most rec ently received lapd message frame does not contain an fcs error. 1 ? indicates that the most recentl y received lapd messa g e frame
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 486 does contain an fcs error. 1 end of message r/o end of message indicator this read-only bit-field indicates whether or not the receive lapd controller sub-block has received a complete lapd message as described below. 0 ? indicates that the receive lapd controller sub-block is currently receiving a lapd message, but has not received the complete message. 1 ? indicates that the receive lapd controller sub-block has received a completed lapd message. note: once the receive lapd controller sub-block sets this bit-field ?high?, this bit-field will remain high, until the receive lapd controller sub-block begins to receive a new lapd message. 0 flag present r/o receive flag sequence indicator: this read-only bit-field indicates whether or not the receive lapd controller sub-block is currently receiving the flag sequence (e.g., a continuous stream of 0x7e octets within the data link channel). 0 ? indicates that the receive la pd controller sub-block is not currently receiving the flag sequence octet. 1 ? indicates that the receive lapd controller sub-block is currently receiving the flag sequence octet.
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 487 table 324: rxe3 nr byte register ? g.832 (address location= 0xn31a, where n ranges from 0x02 to 0x04) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 rxnr_byte[7:0] r/o r/o r/o r/o r/o r/o r/o r/o 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 - 0 rxnr_byte[7:0] r/o receive nr byte value: these read-only bit-fields contain the va lue of the nr byte, within the most recently received e3 frame. table 325: rxe3 gc byte register ? g.832 (address location= 0xn31b, where n ranges from 0x02 to 0x04) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 rxgc_byte[7:0] r/o r/o r/o r/o r/o r/o r/o r/o 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 - 0 rxgc_byte[7:0] r/o receive gc byte value: these read-only bit-fields contain the value of the gc byte, within the most recently received e3 frame. table 326: rxe3 trail-trace-0 register ? g.832 (address location= 0xn31c, where n ranges from 0x02 to 0x04) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 rxttb_0[7:0] r/o r/o r/o r/o r/o r/o r/o r/o 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 - 0 rxttb_0[7:0] r/o receive trail-trace buffer message ? byte 0: these read-only bit-fields contain the contents of byte 0 (e.g., the ?marker? byte), within the most recently received trail-trace buffer? message.
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 488 table 327: rxe3 trail-trace-1 register ? g.832 (address location= 0xn31d, where n ranges from 0x02 to 0x04) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 rxttb_1[7:0] r/o r/o r/o r/o r/o r/o r/o r/o 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 - 0 rxttb_1[7:0] r/o receive trail-trace buffer message ? byte 1: these read-only bit-fields contain the contents of byte 1, within the most recently received trail-trace buffer? message. table 328: rxe3 trail-trace-2 register ? g.832 (address location= 0xn31e, where n ranges from 0x02 to 0x04) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 rxttb_2[7:0] r/o r/o r/o r/o r/o r/o r/o r/o 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 - 0 rxttb_2[7:0] r/o receive trail-trace buffer message ? byte 2: these read-only bit-fields contain the contents of byte 2, within the most recently received trail-trace buffer? message. table 329: rxe3 trail-trace-3 register ? g.832 (address location= 0xn31f, where n ranges from 0x02 to 0x04) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 rxttb_3[7:0] r/o r/o r/o r/o r/o r/o r/o r/o 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 - 0 rxttb_3[7:0] r/o receive trail-trace buffer message ? byte 3: these read-only bit-fields contain the contents of byte 3, within the most recently received trail-trace buffer? message.
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 489 table 330: rxe3 trail-trace-4 register ? g.832 (address location= 0xn320, where n ranges from 0x02 to 0x04) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 rxttb_4[7:0] r/o r/o r/o r/o r/o r/o r/o r/o 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 - 0 rxttb_4[7:0] r/o receive trail-trace buffer message ? byte 4: these read-only bit-fields contain the contents of byte 4, within the most recently received trail-trace buffer? message. table 331: rxe3 trail-trace-5 register ? g.832 (address location= 0xn321, where n ranges from 0x02 to 0x04) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 rxttb_5[7:0] r/o r/o r/o r/o r/o r/o r/o r/o 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 - 0 rxttb_5[7:0] r/o receive trail-trace buffer message ? byte 5: these read-only bit-fields contain the contents of byte 5, within the most recently received trail-trace buffer? message. table 332: rxe3 trail-trace-6 register ? g.832 (address location= 0xn322, where n ranges from 0x02 to 0x04) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 rxttb_6[7:0] r/o r/o r/o r/o r/o r/o r/o r/o 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 - 0 rxttb_6[7:0] r/o receive trail-trace buffer message ? byte 6: these read-only bit-fields contain the contents of byte 6, within the most recently received trail-trace buffer? message.
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 490 table 333: rxe3 trail-trace-7 register ? g.832 (address location= 0xn323, where n ranges from 0x02 to 0x04) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 rxttb_7[7:0] r/o r/o r/o r/o r/o r/o r/o r/o 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 - 0 rxttb_7[7:0] r/o receive trail-trace buffer message ? byte 7: these read-only bit-fields contain the contents of byte 7, within the most recently received trail-trace buffer? message. table 334: rxe3 trail-trace-8 register ? g.832 (address location= 0xn324, where n ranges from 0x02 to 0x04) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 rxttb_8[7:0] r/o r/o r/o r/o r/o r/o r/o r/o 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 - 0 rxttb_8[7:0] r/o receive trail-trace buffer message ? byte 8: these read-only bit-fields contain the contents of byte 8, within the most recently received trail-trace buffer? message. table 335: rxe3 trail-trace-9 register ? g.832 (address location= 0xn325, where n ranges from 0x02 to 0x04) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 rxttb_9[7:0] r/o r/o r/o r/o r/o r/o r/o r/o 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 - 0 rxttb_9[7:0] r/o receive trail-trace buffer message ? byte 9: these read-only bit-fields contain the contents of byte 9, within the most recently received trail-trace buffer? message.
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 491 table 336: rxe3 trail-trace-10 register ? g.832 (address location= 0xn326, where n ranges from 0x02 to 0x04) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 rxttb_10[7:0] r/o r/o r/o r/o r/o r/o r/o r/o 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 - 0 rxttb_10[7:0] r/o receive trail-trace buffer message ? byte 10: these read-only bit-fields contain the contents of byte 10, within the most recently received trail-trace buffer? message. table 337: rxe3 trail-trace-11 register ? g.832 (address location= 0xn327, where n ranges from 0x02 to 0x04) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 rxttb_11[7:0] r/o r/o r/o r/o r/o r/o r/o r/o 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 - 0 rxttb_11[7:0] r/o receive trail-trace buffer message ? byte 11: these read-only bit-fields contain the contents of byte 11, within the most recently received trail-trace buffer? message. table 338: rxe3 trail-trace-12 register ? g.832 (address location= 0xn328, where n ranges from 0x02 to 0x04) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 rxttb_12[7:0] r/o r/o r/o r/o r/o r/o r/o r/o 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 - 0 rxttb_12[7:0] r/o receive trail-trace buffer message ? byte 12: these read-only bit-fields contain the contents of byte 12, within the most recently received trail-trace buffer? message.
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 492 table 339: rxe3 trail-trace-13 register ? g.832 (address location= 0xn329, where n ranges from 0x02 to 0x04) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 rxttb_13[7:0] r/o r/o r/o r/o r/o r/o r/o r/o 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 - 0 rxttb_13[7:0] r/o receive trail-trace buffer message ? byte 13: these read-only bit-fields contain the contents of byte 13, within the most recently received trail-trace buffer? message. table 340: rxe3 trail-trace-14 register ? g.832 (address location= 0xn32a, where n ranges from 0x02 to 0x04) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 rxttb_14[7:0] r/o r/o r/o r/o r/o r/o r/o r/o 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 - 0 rxttb_14[7:0] r/o receive trail-trace buffer message ? byte 14: these read-only bit-fields contain the contents of byte 14, within the most recently received trail-trace buffer? message. table 341: rxe3 trail-trace-15 register ? g.832 (address location= 0xn32b, where n ranges from 0x02 to 0x04) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 rxttb_15[7:0] r/o r/o r/o r/o r/o r/o r/o r/o 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 - 0 rxttb_15[7:0] r/o receive trail-trace buffer message ? byte 15: these read-only bit-fields contain the contents of byte 15, within the most recently received trail-trace buffer? message.
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 493 table 342: rxe3 ssm register ? g.832 (address location= 0xn32c, where n ranges from 0x02 to 0x04) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 rxssm enable mf[1:0] reserved rxssm[3:0] r/w r/o r/o r/o r/o r/o r/o r/o 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 rxssm enable r/w receive ssm enable: this read/write bit-field permits the user to configure the primary frame synchronizer block to operate in either the ?old itu-t g.832 framing? format or in the ?new itu-t g.832 framing? format, as described below. 0 ? configures the primary frame sync hronizer block to support the ?pre october 1998? version of the e3, itu-t g.832 framing format. 1 ? configures the primary frame synchronizer block to support the ?october 1998? version of the e3, itu-t g.832 framing format. 6 - 5 mf[1:0] r/o multi-frame identification: these read-only bit-fields reflect the current frame number, within the received multi-frame. note: these bit-fields are only active if the primary frame synchronizer block is active, and if bit 7 (rxssm enable) of this register is set to ?1?. 4 unused r/o 3 - 0 rxssm[3:0] r/o receive synchronization status message[3:0]: these read-only bit-fields reflect the content of the ?ssm? bits, within the most recently rece ived ssm multiframe. note: these bit-fields are only active if the primary frame synchronizer block is active, and if bit 7 (rxssm enable) of this register is set to ?1?.
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 494 1.10.5 ds3/e3 f rame g enerator b lock r elated r egisters ? ds3 a pplications table 343: txds3 configuration register (address location= 0xn330, where n ranges from 0x02 to 0x04) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 force txferf/ rdi tx x-bits txidle txais txlos txferf/rdi upon los txferf/rdi upon oof txferf/rdi upon ais r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 force txferf/rdi r/w force transmit yellow alarm (ferf/rdi) indicator: this read/write bit-field permits the user to force the frame generator block to transmit the ferf/rdi in dicator to the remote te rminal equipment by setting both of the x-bits (within each outbound ds3 frame) to ?0?. 0 ? does not force the ds3/e3 frame g enerator block to transmit the ferf/rdi indicator. in this case, the ds3/e3 fr ame generator block will set the ?x? bits (within each outbound ds3 frame) to the appropriate value, depending upon receive conditions (as detected by t he primary frame synchronizer block). 1 ? forces the ds3/e3 frame generator block to transmit the ferf/rdi indicator. in this case, the ds3/e3 fram e generator block will force the ?x? bits (within each outbound ds3 frame) to ?0?. thereby transmitting the ferf/rdi indicator to the remo te terminal equipment. note: for normal operation, (e.g., where the ds3/e3 frame generator block will automatically transmit the ferf/rdi indicator whenever the primary frame synchronizer block declares either the los, ais or lof/oof defect condition), the user must set this bit-field to ?0? 6 tx x-bits r/w force x bits to ?1?: this read/write bit-field permits t he user to force the ds3/e3 frame generator block to set the x-bits (wit hin each outbound ds3 frame) to ?1?. 0 ? configures the ds3/e3 frame generator block to automatically set the ?x? bits to the appropriate value, depe nding upon the receive conditions (as detected by the corresponding primary frame synchronizer block). 1 ? configures the ds3/e3 frame generator block to force all of the ?x? bits (within the outbound ds3 data-stream) to ?1?. in this configuration setting, the ds3/e3 frame generator block will set all ?x? bits to ?1? independent of whether the corresponding primary frame synchroniz er block is currently declaring any defect conditions. note: for normal operation (e.g., where the ds3/e3 frame generator block will automatically transmit the ferf/rdi indicator whenever the primary frame synchronizer block declare s the los, ais or lof/oof defect condition) the user must set this bit-field to ?0?. 5 txidle r/w transmit ds3 idle signal: this read/write bit-field permits t he user to force the ds3/e3 frame generator block to transmit the ds3 idle signal pattern to the remote terminal equipment, as described below. 0 ? configures the ds3/e3 frame generator block to transmit normal traffic to the remote terminal equipment.
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 495 1 ? configures the ds3 fram e generator block transmits the ds3 idle pattern to the remote terminal equipment. note: this bit-field is ignored if ?txais? or ?txlos? bit-fields are set to ?1?. the exact pattern that the frame generator transmits (whenever this bit-field is set to ?1?) depends upon the contents within bits 3 through 0 (tx_idle_pattern[3:0 ]) within the ?transmit ds3 pattern? register (address location= 0xn34c). 4 txais r/w transmit ais pattern: this read/write bit-field permits t he user to force the ds3/e3 frame generator block to transmit the ais indicator to the remote terminal equipment as described below. 0 ? configures the ds3/e3 frame generator block to transmit normal traffic to the remote terminal equipment. 1 ? configures the ds3/e3 frame generator block to transmit the ds3 ais indicator to the remo te terminal equipment. note: this bit-field is ignored if the ?txlos? bit-field is set to ?1?. when this bit-field is set to ?1?, it will tr ansmit either a ?framed, repeating 1, 0, 1, 0, ?? pattern, or an ?unframed, all-o nes? pattern, depending upon the state of bit 7 (txais unframed all ones), within the ?transmit ds3 pattern register (address location= 0xn34c). 3 txlos r/w transmit los pattern: this read/write bit-field permits t he user to force the ds3/e3 frame generator block to transmit the los signal pattern to the remote terminal equipment as described below. 0 ? configures the ds3/e3 frame generator block to transmit normal traffic to the remote terminal equipment. 1 ? configures the ds3/e3 frame generat or block to transmit the los pattern (e.g., all zeros or an all ones, depe nding upon user configuration). note: this bit-field is ignored if ?txa is? or ?txlos? are set to ?1?. when this bit-field is set to ?1?, it will transmit either an ?all zeros? pattern, or an ?all ones? pattern; depending upon the state of bit 4 (txlos pattern) within the ?transmit ds3 pattern register (address location=0xn34c). 2 txferf/rdi upon los r/w transmit ferf/rdi upon declaration of the los defect condition: this read/write bit-field permits the user to configure the ds3/e3 frame generator block to automatically transmit the ferf/rdi indicator, anytime (and for the duration that) the correspondi ng primary frame synchronizer block declares the los defect condition. 0 ? the ds3/e3 frame generator block will not automatically transmit the ferf/rdi indicator, whenever (and fo r the duration that) the primary frame synchronizer block declares the los defect condition. 1 ? the ds3/e3 frame generator blo ck will automatically transmit the ferf/rdi indicator whenever (and fo r the duration that) the primary frame synchronizer block declares los defect condition. 1 txferf/rdi upon oof r/w transmit ferf/rdi upon declaration of the oof defect condition: this read/write bit-field permits t he user to configure the ds3 frame generator block to automatically transmit the ferf/rdi indicator, anytime (and for the duration that) the ds3/e3 frame synchronizer block declares the oof defect condition, as described below. 0 ? the ds3/e3 frame generator block will not automatically transmit the ferf/rdi indicator, whenever ( and for the duration that ) the primar y frame
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 496 synchronizer block declares the oof defect condition. 1 ? the ds3/e3 frame generator blo ck will automatically transmit the ferf/rdi indicator whenever (and fo r the duration that) the primary frame synchronizer block declares the oof defect condition. 0 txferf/rdi upon ais r/w transmit ferf/rdi upon declaration of the ais defect condition: this read/write bit-field permits the user to configure the ds3/e3 frame generator block to automatically transmit the ferf/rdi indicator, anytime (and for the duration that) the primary fram e synchronizer block declares the ais defect condition, as described below. 0 ? the ds3/e3 frame generator block will not automatically transmit the ferf/rdi indicator, whenever (and fo r the duration that) the primary frame synchronizer block declares the ais defect condition. 1 ? the ds3/e3 frame generator blo ck will automatically transmit the ferf/rdi indicator, whenever (and fo r the duration that) the primary frame synchronizer block declares the ais defect condition.
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 497 table 344: txds3 feac configuration and status register (address location= 0xn331, where n ranges from 0x02 to 0x04) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 unused txfeac interrupt enable txfeac interrupt status txfeac enable txfeac go txfeac busy r/o r/o r/o r/w rur r/w r/w r/o 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 - 5 unused r/o please set to ?0? for normal operation. 4 txfeac interrupt enable r/w transmit feac interrupt enable: this read/write bit-field permits the user to either enable or disable the ?transmit feac? interrupt. if the user enables this interrupt, then the ds3/e3 frame generator block will generate an interrupt, once the transmit feac controller sub-block has completed its 10 th transmission of a given feac message to the remote terminal equipment. 0 ? disables the transmit feac interrupt. in this configuration setting, the ds 3/e3 frame generator block will not generate an interrupt after the transmit feac controller sub-block has completed its 10 th transmission of a given feac message. 1 ? enables the transmit feac interrupt in this configuration setting, the ds3/e3 frame generator block will generate an interrupt after the transmit feac controller sub-block has completed its 10 th transmission of a given feac message. note: this bit-field is only active if bit 2 (txfeac enable) within this register is set to ?1?. 3 txfeac interrupt status rur transmit feac interrupt status: this reset-upon-read bit-field indicates whether or not the ?transmit feac interrupt? has occurred since the last read of this register, as described below. 0 ? indicates that the transmit feac interrupt has not occurred since the last read of this register. 1 ? indicates that the transmit feac inte rrupt has occurred since the last read of this register. note: this bit-field is only active if bit 2 (txfeac enable) within this register is set to ?1?. 2 txfeac enable r/w transmit feac controller sub-block enable: this read/write bit-field permits the user to either enable or disable the transmit feac controller sub-block, with in the ds3/e3 frame generator block, as described below. 0 ? disables the transmit feac controller sub-block. 1 ? enables the transmit feac controller sub-block. 1 txfeac go r/w transmit feac message command: a ?0? to ?1? transition, within this bit-field configures the transmit feac controller sub-block to begin its transmission of the feac message (which consists of the feac code, as specified within the ?txds3 feac? register).
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 498 note: the user is advised to perform a write operation that resets this bit-field back to ?0?, following execution of the command to transmit a feac message. 0 txfeac busy r/o transmit feac controller busy indicator: this read-only bit-field indicates whether or not the transmit feac controller sub-block is currently busy transmitting a feac message to the remote terminal. 0 ? transmit feac controller sub-block is not busy. 1 ? transmit feac controller sub-block is currently transmitting the feac message to the remote terminal. table 345: txds3 feac register (address location= 0xn332, where n ranges from 0x02 to 0x04) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 unused txfeaccode[5:0] unused r/o r/w r/w r/w r/w r/w r/w r/o 0 1 1 1 1 1 1 0 b it n umber n ame t ype d escription 7 unused r/o 6 - 1 txfeaccode[5:0] r/w transmit feac code word[5:0] these six (6) read/write bit-fields permit the user to specify the feac code word that the transmit feac controller sub-block (within the ds3/e3 frame generator block) should transmit to the remote terminal equipment. once the user enables the ?transmit feac controller sub-block? and commands it to begin its transmission, the transmit feac controller sub- block will then (1) encapsulate this six-bit code word into a 16-bit structure, (2) proceed to transmit this 16-bit st ructure 10 times, repeatedly, and then halt. note: these bit-fields are ignored if the user does not enable and use the transmit feac controller sub-block (within the ds3/e3 frame generator block). 0 unused r/o
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 499 table 346: txds3 lapd configuration register (address location= 0xn333, where n ranges from 0x02 to 0x04) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 txlapd any unused auto retransmit reserved txlapd message length txlapd enable r/w r/o r/o r/o r/w r/o r/w r/w 0 0 0 0 1 0 0 0 b it n umber n ame t ype d escription 7 txlapd any r/w transmit lapd ? any kind: this read/write bit-field permits the user to configure the transmit lapd controller sub-block (within the ds3/e3 frame generator block) to transmit any kind of lapd message (or hdlc message) with a size of 82 byte or less. if the user implements this option, then the transmit lapd controller sub-block will be capable of transmitting any kind of hdlc frame (with any value of header bytes). the only restriction is that the size of the hdlc frame must not exceed 82 bytes. 0 ? does not invoke this ?any kind of hdlc message? feature. in this case, the lapd transmitter will only transm it hdlc messages that contains the bellcore gr-499-core values for sapi and tei. 1- invokes this ?any kind of hdlc message? feature. in this case, the lapd transmitter will be able to transmit hdlc messages that contain any header byte values. note: if the user invokes the ?any kind of hdlc message? feature, then he/she must indicate the size of the information payload (in terms of bytes) within the ?transmit lapd byte count? register (address location=0xn383). 6 - 4 unused r/o 3 auto retransmit r/w auto-retransmit of lapd message: this read/write bit-field permits the user to configure the transmit lapd controller sub-block to transmit pm dl messages, repeatedly at one-second intervals. once the user enables this feature, and then commands the transmit lapd controller sub-block to transmit a given pmdl message; the transmit lapd controller sub-block will then proceed to transmit this pmdl message (based upon the contents within the transmit lapd message buffer) repeatedly at one-second intervals. 0 ? disables the auto-retransmit feature. in this case, the pmdl message will only be transmitted once. afterwards the transmit lapd controller sub-block wi ll proceed to transmit a continuous stream of flag sequence octets (0x7e) vi a the dl bits, within each output ds3 frame. no more pmdl messages will be transmitted until the user commands another transmission. 1 ? enables the auto-retransmit feature. in this case, the transmit lapd controller sub-block will transmit pmdl messages (based upon the contents within the transmit lapd message buffer) repeatedly at one-second intervals. note: this bit-field is ignored if the tr ansmit lapd controller sub-block is disabled.
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 500 2 reserved r/o 1 txlapd message length r/w transmit lapd message length select: this read/write bit-field permits the us er to specify the length of the payload data within the outbound lapd/pmd l message, as indicated below. 0 ? configures the transmit lapd controller sub-block to transmit a lapd/pmdl message that has a payload data size of 76 bytes. 1 ? configures the transmit lapd controller sub-block to transmit a lapd/pmdl message that has a payload data size of 82 bytes. note: this bit-field is ignored if the tr ansmit lapd controller sub-block is disabled. 0 transmit lapd enable r/w transmit lapd controller sub-block enable: this read/write bit-field permits the user to enable the transmit lapd controller sub-block, within the ds3/e3 frame generator block. once the user enables the transmit lapd controller su b-block, it will immediately begin transmitting the flag seq uence octet (0x7e) to th e remote terminal via the outbound ?dl? bits, within each ds3 data stream. the transmit lapd controller sub-block will continue to repeatedly transmit the flag sequence octet until the user commands the transmit lapd controller sub-block to transmit a pmdl message. 0 ? disables the transmit lapd controller sub-block. 1 ? enables the transmit lapd controller sub-block.
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 501 table 347: txds3 lapd status/interrupt register (address location= 0xn334, where n ranges from 0x02 to 0x04) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 unused initiate transmission of lapd/pmdl message transmit lapd controller busy transmit lapd interrupt enable transmit lapd interrupt status r/o r/o r/o r/o r/w r/o r/w rur 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 - 4 unused r/o 3 initiate transmission of lapd/ pmdl message r/w transmit lapd message command: a ?0? to ?1? transition, within this bit-field commands the transmit lapd controller sub-block to begin the following activities: ? reading out the contents of the transmit lapd message buffer. ? zero-stuffing of this data ? fcs calculation and insertion ? fragmentation of this composite pmdl message, and insertion into the ?dl? bit-fields, within each outbound ds3 frame. note: this bit-field is only active if the transmit lapd controller block has been enabled. 2 transmit lapd controller busy r/o transmit lapd controller busy indicator: this ?read-only? bit-field indicates whether or not the transmit lapd controller sub-block is currently busy transmitting a pmdl message to the remote terminal equipment. the user can continuously poll this bit-field in order to check for completion of transmi ssion of the lapd/pmdl message. 0 ? indicates that the transmit lapd controller sub-block is not busy transmitting a pmdl message. 1 ? indicates that the transmit lapd co ntroller sub-block is currently busy transmitting a pmdl message. note: this bit-field is only active if the transmit lapd controller sub-block has been enabled. 1 transmit lapd interrupt enable r/w transmit lapd interrupt enable: this read/write bit-field permits the user to either enable or disable the ?transmit lapd interrupt?. if the user enables this interrupt, then the ds3/e3 frame generator block will generate an interrupt anytime the transmit lapd controller sub-block has completed its transmission of a given lapd/pmdl message to the remote terminal. 0 ? disables the transmit lapd interrupt. 1 ? enables the transmit lapd interrupt. 0 transmit lapd interrupt status rur transmit lapd interrupt status: this reset-upon-read bit-field indicates whether or not the ?transmit lapd interrupt? has occurred since the last read of this register as described below. 0 ? indicates that the transmit lapd interru p t has not occurred since the last
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 502 read of this register. 1 ? indicates that the transmit lapd interrupt has occurred since the last read of this register.
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 503 table 348: txds3 m-bit mask register (address location= 0xn335, where n ranges from 0x02 to 0x04) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 txfebedat[2:0] febe register enable tx p-bit error txm_bit_mask[2:0] r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 b it n umber n ame t ype d ecription 7 - 5 txfebedat [2:0] r/w transmit febe value: these read/write bit-fields, along wi th ?febe register enable? permit the user to configure the ds3/e3 frame gener ator block to transmit ?user-specified? febe values (to the remote terminal) based upon the contents of these bit-fields. if the user sets the ?febe register enab le? bit-field to ?1?, then the ds3/e3 frame generator block will wr ite the contents of these bit-fields into the febe bits, within each outbound ds3 frame. if the user sets the ?febe register enable? bit-field to ?0? then these register bits will be ignored. 4 febe register enable r/w transmit febe (by software) enable: this read/write bit-field permits the user to configure the ds3/e3 frame generator block to transmit ?user-specifed? febe values (to the remote terminal) per register setting via the ?txfebedat[2:0]? bit-field. this option provides the user with software control over the ? outbound? febe values, within the ds3 data stream. 0 ? configures the ds3/e3 frame genera tor block to set the febe bit-fields (within each outbound ds3 frame) to the appropriate values based upon receive conditions, as determined by the companio n primary frame synchronizer block. 1 ? configures the ds3/e3 frame genera tor block to write the contents of the ?txfebedat[2:0]? bit-fields into the f ebe bits, within ea ch ?outbound? ds3 frame. 3 tx p-bit error r/w transmit p-bit error: this read/write bit-field permits the user to configure the ds3/e3 frame generator block to transmit ds3 frames with erred p-bits, as indicated below. 0 ? configures the ds3/e3 frame generat or block to generate and transmit ds3 frames, to the remote terminal equipment. 1 ? configures the ds3/e3 frame generat or block to generate and transmit ds3 frames, to the remote terminal equipment. 2 ? 0 txm_bit_ mask[2:0] r/w transmit m-bit error: these read/write bit-fields permit the user to configure the ds3/e3 frame generator block to transmit ds3 frames with erred m-bits. these three (3) bit-fields correspond to the three m-bits, within each outbound ds3 frame. the ds3/e3 frame generat or block will perform an xor operation with the contents of these bit-fields and the value of the three m-bits. the results of this calculation will be written back into the m-bit positions within each outbound ds3 frame. the user should set these bit-fields to ?0, 0, 0? for normal (e.g., un-erred) operation.
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 504 table 349: txds3 f-bit mask # 1 register (; addr ess location= 0xn336, where n ranges from 0x02 to 0x04) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 unused f, m, p bit pass thru enable f_bit mask[27]/ udl bit # 9 (c73) f_bit mask [26]/ udl bit # 8 (c72) f_bit mask [25]/ udl bit # 7 (c71) f_bit mask [24]/ r/o r/o r/o r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 - 5 unused r/o 4 f, m, p bit pass thru enable r/w f-bit, m-bit, p-bit pass-thru enable: this read/write bit-field permits the user to configure frame generator block to allow any f, m and p bits (within the ds3 signal) that it accepts to pass through in an un-altered manner. this feature is useful whenever the XRT94L33 device is handling unframed data that is operating at the ds3-rate (44.736mhz). 0 ? disables this feature 1 ? enables this feature 3 f bit mask[27]/ udl bit # 9 (c73) r/w transmit f-bit error ? bit 28/udl bit # 9 (c73): the exact function of this register bit depends upon whether bit 7 (txohsrc), within the ?test register? (address location= 0xn30c) is set to ?1? or ?0?. if ?txohsrc? = 0 ? transmit f-bit error ? bit 28: this read/write bit-field permits the user to configure the ds3/e3 frame generator block to transmit ds3 frames with a single/particular erred f bit. this particular f-bit corresponds with the 28 th f-bit, within a given outbound ds3 frame. the ds3/e3 frame g enerator block will perform an xor operation with the contents of this bit-field and value of the 28 th f-bit. the results of this calculation will be written back into the 28 th f-bit position, within each outbound ds3 frame. the user should set this bit-field to ?0? for normal (e.g., un-erred) operation. if ?txohsrc? = 1 ? insert enable for udl bit # 9 or c73 bit: this read/write bit-field permits the user to configure the ds3/e3 frame generator block to externally accept an overhead bit (from ?up-stream? circuitry) and insert it into the ?udl bit #9 (or c 73)? bit-fields, within the outbound ds3 data-stream. 0 ? configures the ds3/e3 frame generator block to externally accept and insert data into this particular overhead bit-field (e.g., the udl bit # 9 or the c73 bit-field). 1 ? configures the ds3/e3 frame genera tor block to not externally accept and insert data into this overhead bit-field. 2 f bit mask [26]/ udl bit #8 (c72) r/w transmit f-bit error ? bit 27/udl bit # 8 (c72): the exact function of this register bit depends upon whether bit 7 (txohsrc), within the ?test register? (address location= 0xn30c) is set to ?1? or ?0?. if ?txohsrc? = 0 ? transmit f-bit error ? bit 27 this read/write bit-field p ermits the user to confi g ure the ds3/e3 frame
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 505 generator block to transmit ds3 frames with a single/particular erred f bit. this particular f-bit corresponds with the 27 th f-bit, within a given outbound ds3 frame. the ds3/e3 frame g enerator block will perform an xor operation with the contents of this bit-field and value of the 27 th f-bit. the results of this calculation will be written back into the 27 th f-bit position, within each outbound ds3 frame. the user should set this bit-field to ?0? for normal (e.g., un-erred) operation. if ?txohsrc? = 1 ? insert enable for udl bit # 8 or c72 bit: this read/write bit-field permits the user to configure the ds3/e3 frame generator block to externally accept an overhead bit (from ?up-stream? circuitry) and insert it into the ?udl bit #8 (or c 72)? bit-fields, within the outbound ds3 data-stream. 0 ? configures the ds3/e3 frame generator block to externally accept and insert data into this particular overhead bit-field (e.g., the udl bit # 8 or the c72 bit-field). 1 ? configures the ds3/e3 frame genera tor block to not externally accept and insert data into this overhead bit-field. 1 f bit mask [25]/ udl bit # 7 (c71) r/w transmit f-bit error ? bit 26/udl bit # 7 (c71): the exact function of this register bit depends upon whether bit 7 (txohsrc), within the ?test register? (address location= 0xn30c) is set to ?1? or ?0?. if ?txohsrc? = 0 ? transmit f-bit error ? bit 26: this read/write bit-field permits the user to configure the ds3/e3 frame generator block to transmit ds3 frames with a single/particular erred f bit. this particular f-bit corresponds with the 26 th f-bit, within a given outbound ds3 frame. the ds3/e3 frame g enerator block will perform an xor operation with the contents of this bit-field and value of the 26 th f-bit. the results of this calculation will be written back into the 26 th f-bit position, within each outbound ds3 frame. the user should set this bit-field to ?0? for normal (e.g., un-erred) operation. if ?txohsrc? = 1 ? insert enable for udl bit # 7 or c71 bit: this read/write bit-field permits the user to configure the ds3/e3 frame generator block to externally accept an overhead bit (from ?up-stream? circuitry) and insert it into the ?udl bit #7 (or c 71)? bit-fields, within the outbound ds3 data-stream. 0 ? configures the ds3/e3 frame generator block to externally accept and insert data into this particular overhead bit-field (e.g., the udl bit # 7 or the c71 bit-field). 1 ? configures the ds3/e3 frame genera tor block to not externally accept and insert data into this overhead bit-field. 0 f bit mask [24] r/w transmit f-bit error ? bit 25: this read/write bit-field permits the user to configure the ds3/e3 frame generator block to transmit ds3 frames with a single/particular erred f bit. this particular f-bit corresponds with the 25 th f-bit, within a given outbound ds3 frame. the ds3/e3 frame g enerator block will perform an xor operation with the contents of this bit-field and value of the 25 th f-bit. the results of this calculation will be written back into the 25 th f-bit position, within each outbound ds3 frame. the user should set this bit-field to ?0? for normal (e.g., un-erred) operation. note: this bit-field is ignored if bit 7 (t xohsrc), within the ?test register (address location= 0xn30c) is set to the ?1?.
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 506 table 350: txds3 f-bit mask # 2 register (address location= 0xn337, where n ranges from 0x02 to 0x04) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 f_bit mask [23]/ udl bit # 6 (c63) f_bit mask [22]/ udl bit # 5 (c62) f_bit mask [21]/ udl bit # 4 (c61) f_bit mask [20] f_bit mask [19]/ dl bit # 3 (c53) f_bit mask [18]/ dl bit # 2 (c52) f_bit mask [17]/ dl bit # 1 (c51) f_bit mask [16] r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 f bit mask[23]/ udl bit # 6 (c63) r/w transmit f-bit error ? bit 24/udl bit # 6 (c63): the exact function of this register bit depends upon whether bit 7 (txohsrc), within the ?test register? (indirect address = 0xne, 0x0c; direct address address location= 0xnfn30c) is set to ?1? or ?0?. if ?txohsrc? = 0 ? transmit f-bit error ? bit 24: this read/write bit-field permits the user to configure the ds3/e3 frame generator block to transmit ds3 frames with a single/particular erred f bit. this particular f-bit corresponds with the 24th f-bit, within a given outbound ds3 frame. the ds3/e3 frame g enerator block will perform an xor operation with the contents of this bit-fi eld and value of the 24th f-bit. the results of this calculation will be wri tten back into the 24th f-bit position, within each outbound ds3 frame. the user should set this bit-field to ?0? for normal (e.g., un-erred) operation. if ?txohsrc? = 1 - insert enable for udl bit # 6 or c63 bit: this read/write bit-field permits the user to configure the ds3/e3 frame generator block to externally accept an overhead bit (from ?up-stream? circuitry) and insert it into the ?udl bit # 6 (or c63)? bit-fields, within the outbound ds3 data-stream. 0 - configures the ds3/e3 frame generator block to externally accept and insert data into this particular overhead bit-field (e.g, the udl bit # 6 or the c63 bit-field). 1- configures the ds3/e3 frame generat or block to not externally accept and insert data into this overhead bit-field. 6 f bit mask [22]/ udl bit # 5 (c62) r/w transmit f-bit error ? bit 23/udl bit # 5 (c62): the exact function of this register bit depends upon whether bit 7 (txohsrc), within the ?test register? (address location= 0xn30c) is set to ?1? or ?0?. if ?txohsrc? = 0 ? transmit f-bit error ? bit 23: this read/write bit-field permits the user to configure the ds3/e3 frame generator block to transmit ds3 frames with a single/particular erred f bit. this particular f-bit corresponds with the 23 rd f-bit, within a given outbound ds3 frame. the ds3/e3 frame g enerator block will perform an xor operation with the contents of th is bit-field and value of the 23 rd f-bit. the results of this calculation will be written back into the 23rd f-bit position, within each outbound ds3 frame. the user should set this bit-field to ?0? for normal (e.g., un-erred) operation. if ?txohsrc? = 1 - insert enable for udl bit # 5 or c62 bit: this read/write bit-field p ermits the user to confi g ure the ds3/e3 frame
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 507 generator block to externally accept an overhead bit (from ?up-stream? circuitry) and insert it into the ?udl bit # 5 (or c62)? bit-fields, within the outbound ds3 data-stream. 0 - configures the ds3/e3 frame generator block to externally accept and insert data into this particular overhead bit-field (e.g., the udl bit # 5 or the c62 bit-field). 1- configures the ds3/e3 frame generat or block to not externally accept and insert data into this overhead bit-field. 5 f bit mask [21]/ udl bit # 4 (c61) r/w transmit f-bit error ? bit 22/udl bit # 4 (c61): the exact function of this register bit depends upon whether bit 7 (txohsrc), within the ?test register? (address location= 0xn30c) is set to ?1? or ?0?. if ?txohsrc? = 0 ? transmit f-bit error ? bit 22: this read/write bit-field permits the user to configure the ds3/e3 frame generator block to transmit ds3 frames with a single/particular erred f bit. this particular f-bit corresponds with the 22 nd f-bit, within a given outbound ds3 frame. the ds3/e3 frame g enerator block will perform an xor operation with the contents of this bit-field and value of the 22 nd f-bit. the results of this calculation will be written back into the 22 nd f-bit position, within each outbound ds3 frame. the user should set this bit-field to ?0? for normal (e.g., un-erred) operation. if ?txohsrc? = 1 - insert enable for udl bit # 4 or c61 bit: this read/write bit-field permits the user to configure the ds3/e3 frame generator block to externally accept an overhead bit (from ?up-stream? circuitry) and insert it into the ?udl bit # 4 (or c61)? bit-fields, within the outbound ds3 data-stream. 0 - configures the ds3/e3 frame generator block to externally accept and insert data into this particular overhead bit-field (e.g., the udl bit # 4 or the c61 bit-field). 1- configures the ds3/e3 frame generat or block to not externally accept and insert data into this overhead bit-field. 4 f bit mask [20] r/w transmit f-bit error ? bit 21: this read/write bit-field permits the user to configure the ds3/e3 frame generator block to transmit ds3 frames with a single/particular erred f bit. this particular f-bit corresponds with the 21 st f-bit, within a given outbound ds3 frame. the ds3/e3 frame g enerator block will perform an xor operation with the contents of th is bit-field and value of the 21 st f-bit. the results of this calculation will be written back into the 21 st f-bit position, within each outbound ds3 frame. the user should set this bit-field to ?0? for normal (e.g., un-erred) operation. 3 f bit mask [19]/ dl bit # 3 (c53) r/w transmit f-bit error ? bit 20/dl bit # 3 (c53): the exact function of this register bit depends upon whether bit 7 (txohsrc), within the ?test register? (address location= 0xn30c) is set to ?1? or ?0?. if ?txohsrc? = 0 ? transmit f-bit error ? bit 20: this read/write bit-field permits the user to configure the ds3/e3 frame generator block to transmit ds3 frames with a single/particular erred f bit. this particular f-bit corresponds with the 20 th f-bit, within a given outbound ds3 frame. the ds3/e3 frame g enerator block will perform an xor operation with the contents of this bit-field and value of the 20 th f-bit. the results of this calculation will be written back into the 20 th f-bit position, within each outbound ds3 frame.
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 508 the user should set this bit-field to ?0? for normal (e.g., un-erred) operation. if ?txohsrc? = 1 - insert enable for dl bit # 3 or c53 bit: this read/write bit-field permits the user to configure the ds3/e3 frame generator block to externally accept an overhead bit (from ?up-stream? circuitry) and insert it into the ?dl bit # 3 (or c53)? bit-fields, within the outbound ds3 data-stream. 0 - configures the ds3/e3 frame generator block to externally accept and insert data into this particular overhead bit-field (e.g., the dl # bit 3 or the c53 bit-field). 1- configures the ds3/e3 frame generat or block to not externally accept and insert data into this overhead bit-field. 2 f bit mask [18]/ dl bit # 2 (c52) r/w transmit f-bit error ? bit 19/dl bit # 2 (c52): the exact function of this register bit depends upon whether bit 7 (txohsrc), within the ?test register? (address location= 0xn30c) is set to ?1? or ?0?. if ?txohsrc? = 0 ? transmit f-bit error ? bit 19: this read/write bit-field permits the user to configure the ds3/e3 frame generator block to transmit ds3 frames with a single/particular erred f bit. this particular f-bit corresponds with the 19 th f-bit, within a given outbound ds3 frame. the ds3/e3 frame g enerator block will perform an xor operation with the contents of this bit-field and value of the 19 th f-bit. the results of this calculation will be written back into the 19 th f-bit position, within each outbound ds3 frame. the user should set this bit-field to ?0? for normal (e.g., un-erred) operation. if ?txohsrc? = 1 - insert enable for dl bit # 2 or c52 bit: this read/write bit-field permits the user to configure the ds3/e3 frame generator block to externally accept an overhead bit (from ?up-stream? circuitry) and insert it into the ?dl bit # 2 (or c52)? bit-fields, within the outbound ds3 data-stream. 0 - configures the ds3/e3 frame generator block to externally accept and insert data into this particular overhead bit-field (e.g., the dl bit # 2 or the c52 bit-field). 1- configures the ds3/e3 frame generat or block to not externally accept and insert data into this overhead bit-field. 1 f bit mask [17]/ dl bit # 1 (c51) r/w transmit f-bit error ? bit 18/dl bit # 1 (c51): the exact function of this register bit depends upon whether bit 7 (txohsrc), within the ?test register? (address location= 0xn30c) is set to ?1? or ?0?. if ?txohsrc? = 0 ? transmit f-bit error ? bit 18: this read/write bit-field permits the user to configure the ds3/e3 frame generator block to transmit ds3 frames with a single/particular erred f bit. this particular f-bit corresponds with the 18 th f-bit, within a given outbound ds3 frame. the ds3/e3 frame g enerator block will perform an xor operation with the contents of this bit-field and value of the 18 th f-bit. the results of this calculation will be written back into the 18 th f-bit position, within each outbound ds3 frame. the user should set this bit-field to ?0? for normal (e.g., un-erred) operation. if ?txohsrc? = 1 - insert enable for dl bit # 1 or c51 bit: this read/write bit-field permits the user to configure the ds3/e3 frame generator block to externally accept an overhead bit (from ?up-stream? circuitry) and insert it into the ?dl bit # 1 (or c51)? bit-fields, within the outbound ds3 data-stream.
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 509 0 - configures the ds3/e3 frame generator block to externally accept and insert data into this particular overhead bit-field (e.g., the dl bit # 1 or the c51 bit-field). 1- configures the ds3/e3 frame generat or block to not externally accept and insert data into this overhead bit-field. 0 f bit mask [16] r/w transmit f-bit error ? bit 17: this read/write bit-field permits the user to configure the ds3/e3 frame generator block to transmit ds3 frames with a single/particular erred f bit. this particular f-bit corresponds with the 17 th f-bit, within a given outbound ds3 frame. the ds3/e3 frame g enerator block will perform an xor operation with the contents of this bit-field and value of the 17 th f-bit. the results of this calculation will be written back into the 17 th f-bit position, within each outbound ds3 frame. the user should set this bit-field to ?0? for normal (e.g., un-erred) operation.
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 510 table 351: txds3 f-bit mask # 3 register (address location= 0xn338, where n ranges from 0x02 to 0x04) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 f_bit mask [15]/ febe bit 3 (c43) f_bit mask [14]/ febe bit 2 (c42) f_bit mask [13]/ febe bit 1 (c41) f_bit mask [12] f_bit mask [11]/ cp bit # 3 (c33) f_bit mask [10]/ cp bit # 2 (c32) f_bit mask [9]/ cp bit # 1 (c31) f_bit mask [8] r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 f bit mask[15]/ febe bit # 3 (c43) r/w transmit f-bit error ? bit 16/febe bit # 3 (c43): the exact function of this register bi t depends upon whether bit 7 (txohsrc), within the ?test register? (address location= 0xn30c) is set to ?1? or ?0?. if ?txohsrc? = 0 ? transmit f-bit error ? bit 16: this read/write bit-field permits the user to configure the ds3/e3 frame generator block to transmit ds3 frames with a single/particular erred f bit. this particular f-bit corresponds with the 16 th f-bit, within a given outbound ds3 frame. the ds3/e3 frame g enerator block will perform an xor operation with the contents of this bit-field and value of the 16 th f-bit. the results of this calculation will be written back into the 16 th f-bit position, within each outbound ds3 frame. the user should set this bit-field to ?0? for normal (e.g., un-erred) operation. if ?txohsrc? = 1 - insert enable for febe bit # 3 or c43 bit: this read/write bit-field permits the user to configure the ds3/e3 frame generator block to externally acc ept an overhead bit (from ?up-stream? circuitry) and insert it into the ?febe bi t # 3 (or c43)? bit-fields, within the outbound ds3 data-stream. 0 - configures the ds3/e3 frame generator block to externally accept and insert data into this particular overh ead bit-field (e.g., the febe bit # 3 or the c43 bit-field). 1- configures the ds3/e3 frame genera tor block to not externally accept and insert data into this overhead bit-field. 6 f bit mask [14]/ febe bit # 2 (c42) r/w transmit f-bit error ? bit 15/febe bit # 2 (c42): the exact function of this register bi t depends upon whether bit 7 (txohsrc), within the ?test register? (address location= 0xn30c) is set to ?1? or ?0?. if ?txohsrc? = 0 ? transmit f-bit error ? bit 15: this read/write bit-field permits the user to configure the ds3/e3 frame generator block to transmit ds3 frames with a single/particular erred f bit. this particular f-bit corresponds with the 15 th f-bit, within a given outbound ds3 frame. the ds3/e3 frame g enerator block will perform an xor operation with the contents of this bit-field and value of the 15 th f-bit. the results of this calculation will be written back into the 15 th f-bit position, within each outbound ds3 frame. the user should set this bit-field to ?0? for normal (e.g., un-erred) operation. if ?txohsrc? = 1 - insert enable for febe bit # 2 or c42 bit: this read/write bit-field permits the user to configure the ds3/e3 frame generator block to externall y acce p t an overhead bit ( from ?u p -stream?
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 511 circuitry) and insert it into the ?febe bi t # 2 (or c42)? bit-fields, within the outbound ds3 data-stream. 0 - configures the ds3/e3 frame generator block to externally accept and insert data into this particular overh ead bit-field (e.g., the febe bit # 2 or the c42 bit-field). 1- configures the ds3/e3 frame genera tor block to not externally accept and insert data into this overhead bit-field. 5 f bit mask [13]/ febe bit 1 (c41) r/w transmit f-bit error ? bit 14/febe bit # 1 c41): the exact function of this register bi t depends upon whether bit 7 (txohsrc), within the ?test register? (address location= 0xn30c) is set to ?1? or ?0?. if ?txohsrc? = 0 ? transmit f-bit error ? bit 14: this read/write bit-field permits the user to configure the ds3/e3 frame generator block to transmit ds3 frames with a single/particular erred f bit. this particular f-bit corresponds with the 14 th f-bit, within a given outbound ds3 frame. the ds3/e# frame g enerator block will perform an xor operation with the contents of this bit-field and value of the 14 th f-bit. the results of this calculation will be written back into the 14 th f-bit position, within each outbound ds3 frame. the user should set this bit-field to ?0? for normal (e.g., un-erred) operation. if ?txohsrc? = 1 - insert enable for febe bit # 1 or c41 bit: this read/write bit-field permits the user to configure the ds3/e3 frame generator block to externally acc ept an overhead bit (from ?up-stream? circuitry) and insert it into the ?febe bi t # 1 (or c41)? bit-fields, within the outbound ds3 data-stream. 0 - configures the ds3/e3 frame generator block to externally accept and insert data into this particular overhe ad bit-field (e.g, th e febe bit # 1 or the c41 bit-field). 1- configures the ds3/e3 frame genera tor block to not externally accept and insert data into this overhead bit-field. 4 f bit mask [12] r/w transmit f-bit error ? bit 13: this read/write bit-field permits the user to configure the ds3/e3 frame generator block to transmit ds3 frames with a single/particular erred f bit. this particular f-bit corresponds with the 13 th f-bit, within a given outbound ds3 frame. the ds3/e3 frame g enerator block will perform an xor operation with the contents of this bit-field and value of the 13 th f-bit. the results of this calculation will be written back into the 13 th f-bit position, within each outbound ds3 frame. the user should set this bit-field to ?0? for normal (e.g., un-erred) operation. 3 f bit mask [11]/ cp bit # 3 (c33) r/w transmit f-bit error ? bit 12/cp bit # 3 (c33): the exact function of this register bi t depends upon whether bit 7 (txohsrc), within the ?test register? (address location= 0xn30c) is set to ?1? or ?0?. if ?txohsrc? = 0 ? transmit f-bit error ? bit 12: this read/write bit-field permits the user to configure the ds3/e3 frame generator block to transmit ds3 frames with a single/particular erred f bit. this particular f-bit corresponds with the 12th f-bit, within a given outbound ds3 frame. the ds3/e3 frame g enerator block will perform an xor operation with the contents of this bit- field and value of the 12th f-bit. the results of this calculation will be writt en back into the 12th f-bit position, within each outbound ds3 frame.
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 512 the user should set this bit-field to ?0? for normal (e.g., un-erred) operation. if ?txohsrc? = 1 - insert enable for cp bit # 3 or c33 bit: this read/write bit-field permits the user to configure the ds3/e3 frame generator block to externally acc ept an overhead bit (from ?up-stream? circuitry) and insert it into the ?cp bi t # 3 (or c33)? bit-fields, within the outbound ds3 data-stream. 0 - configures the ds3/e3 frame generator block to externally accept and insert data into this particular overhead bit-field (e.g., the cp bit # 3 or the c33 bit-field). 1- configures the ds3/e3 frame genera tor block to not externally accept and insert data into this overhead bit-field. 2 f bit mask [10]/ cp bit # 2 (c32) r/w transmit f-bit error ? bit 11/cp bit # 2 (c32): the exact function of this register bi t depends upon whether bit 7 (txohsrc), within the ?test register? (address location= 0xn30c) is set to ?1? or ?0?. if ?txohsrc? = 0 ? transmit f-bit error ? bit 11: this read/write bit-field permits the user to configure the ds3/e3 frame generator block to transmit ds3 frames with a single/particular erred f bit. this particular f-bit corresponds with the 11th f-bit, within a given outbound ds3 frame. the ds3/e3 frame g enerator block will perform an xor operation with the contents of this bit- field and value of the 11th f-bit. the results of this calculation will be writt en back into the 11th f-bit position, within each outbound ds3 frame. the user should set this bit-field to ?0? for normal (e.g., un-erred) operation. if ?txohsrc? = 1 - insert enable for cp bit # 2 or c32 bit: this read/write bit-field permits the user to configure the ds3/e3 frame generator block to externally acc ept an overhead bit (from ?up-stream? circuitry) and insert it into the ?cp bi t # 2 (or c32)? bit-fields, within the outbound ds3 data-stream. 0 - configures the ds3/e3 frame generator block to externally accept and insert data into this particular overhead bit-field (e.g., the cp bit # 2 or the c32 bit-field). 1- configures the ds3/e3 frame genera tor block to not externally accept and insert data into this overhead bit-field. 1 f bit mask [9]/ cp bit # 1 (c31) r/w transmit f-bit error ? bit 10/cp bit # 1 (c31): the exact function of this register bi t depends upon whether bit 7 (txohsrc), within the ?test register? (address location= 0xn30c) is set to ?1? or ?0?. if ?txohsrc? = 0 ? transmit f-bit error ? bit 10: this read/write bit-field permits the user to configure the ds3/e3 frame generator block to transmit ds3 frames with a single/particular erred f bit. this particular f-bit corresponds with the 10th f-bit, within a given outbound ds3 frame. the ds3/e3 frame g enerator block will perform an xor operation with the contents of this bit- field and value of the 10th f-bit. the results of this calculation will be writt en back into the 10th f-bit position, within each outbound ds3 frame. the user should set this bit-field to ?0? for normal (e.g., un-erred) operation. if ?txohsrc? = 1 - insert enable for cp bit # 1 or c31 bit: this read/write bit-field permits the user to configure the ds3/e3 frame generator block to externally acc ept an overhead bit (from ?up-stream? circuitry) and insert it into the ?cp bi t # 1 (or c31)? bit-fields, within the outbound ds3 data-stream.
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 513 0 - configures the ds3/e3 frame generator block to externally accept and insert data into this particular overhead bit-field (e.g., the cp bit # 1 or the c31 bit-field). 1- configures the ds3/e3 frame genera tor block to not externally accept and insert data into this overhead bit-field. 0 f bit mask [8] r/w transmit f-bit error ? bit 9: this read/write bit-field permits the user to configure the ds3/e3 frame generator block to transmit ds3 frames with a single/particular erred f bit. this particular f-bit corresponds with the 9th f-bit, within a given outbound ds3 frame. the ds3/e3 frame g enerator block will perform an xor operation with the contents of this bit- field and value of the 9th f-bit. the results of this calculation will be writte n back into the 9th f-bit position, within each outbound ds3 frame. the user should set this bit-field to ?0? for normal (e.g., un-erred) operation.
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 514 table 352: txds3 f-bit mask # 4 register (address location= 0xn339, where n ranges from 0x02 to 0x04) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 f_bit mask [7]/ udl bit # 3 (c23) f_bit mask [6]/ udl bit # 2 (c22) f_bit mask [5]/ udl bit # 1 (c21) f_bit mask [4]/ x bit # 2 f_bit mask [3]/ feac bit (c13) f_bit mask [2]/ na bit (c12) f_bit mask [1]/ aic bit (c11) f_bit mask [0]/ x bit # 1 r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 f bit mask[7]/ udl bit # 3 (c23) r/w transmit f-bit error ? bit 8/udl bit # 3 (c23): the exact function of this register bi t depends upon whether bit 7 (txohsrc), within the ?test register? (address location= 0xn30c) is set to ?1? or ?0?. if ?txohsrc? = 0 ? transmit f-bit error ? bit 8: this read/write bit-field permits the user to configure the ds3/e3 frame generator block to transmit ds3 frames with a single/particular erred f bit. this particular f-bit corresponds with the 8th f-bit, within a given outbound ds3 frame. the ds3/e3 frame generator bl ock will perform an xor operation with the contents of this bit-field and value of the 8th f-bit. the results of this calculation will be written back into the 8th f-bit position, within each outbound ds3 frame. the user should set this bit-field to ?0? for normal (e.g., un-erred) operation. if ?txohsrc? = 1 - insert enable for udl bit # 3 or c23 bit: this read/write bit-field permits the user to configure the ds3/e3 frame generator block to externally accept an overhead bit (from ?up-stream? circuitry) and insert it into the ?udl bit # 3 (or c23)? bit-fields, within the outbound ds3 data-stream. 0 - configures the ds3/e3 frame generator block to externally accept and insert data into this particular overhead bit-field (e.g., the udl bit # 3 or the c23 bit-field). 1- configures the ds3/e3 frame generator block to not externally accept and insert data into this overhead bit-field. 6 f bit mask [6]/ udl bit # 2 (c22) r/w transmit f-bit error ? bit 7/udl bit # 2 (c22): the exact function of this register bi t depends upon whether bit 7 (txohsrc), within the ?test register? (address location= 0xn30c) is set to ?1? or ?0?. if ?txohsrc? = 0 ? transmit f-bit error ? bit 7: this read/write bit-field permits the user to configure the ds3/e3 frame generator block to transmit ds3 frames with a single/particular erred f bit. this particular f-bit corresponds with the 7th f-bit, within a given outbound ds3 frame. the ds3/e3 frame generator bl ock will perform an xor operation with the contents of this bit-field and value of the 7th f-bit. the results of this calculation will be written back into the 7th f-bit position, within each outbound ds3 frame. the user should set this bit-field to ?0? for normal (e.g., un-erred) operation. if ?txohsrc? = 1 - insert enable for udl bit # 2 or c22 bit: this read/write bit-field permits the user to configure the ds3/e3 frame generator block to externall y acce p t an overhead bit ( from
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 515 ?up-stream? circuitry) and insert it into t he ?udl bit # 2 (or c22)? bit-fields, within the outbound ds3 data-stream. 0 - configures the ds3/e3 frame generator block to externally accept and insert data into this particular overhead bit-field (e.g., the udl bit # 2 or the c22 bit-field). 1- configures the ds3/e3 frame generator block to not externally accept and insert data into this overhead bit-field. 5 f bit mask [5]/ udl bit # 1 (c21) r/w transmit f-bit error ? bit 6/udl bit # 1 (c21): the exact function of this register bi t depends upon whether bit 7 (txohsrc), within the ?test register? (address location= 0xn30c) is set to ?1? or ?0?. if ?txohsrc? = 0 ? transmit f-bit error ? bit 6: this read/write bit-field permits the user to configure the ds3/e3 frame generator block to transmit ds3 frames with a single/particular erred f bit. this particular f-bit corresponds with the 6th f-bit, within a given outbound ds3 frame. the ds3/e3 frame generator bl ock will perform an xor operation with the contents of this bit-field and value of the 6th f-bit. the results of this calculation will be written back into the 6th f-bit position, within each outbound ds3 frame. the user should set this bit-field to ?0? for normal (e.g., un-erred) operation. if ?txohsrc? = 1 - insert enable for udl bit # 1 or c21 bit: this read/write bit-field permits the user to configure the ds3/e3 frame generator block to externally accept an overhead bit (from ?up-stream? circuitry) and insert it into the ?udl bit # 1 (or c21)? bit-field, within the outbound ds3 data-stream. 0 - configures the ds3/e3 frame generator block to externally accept and insert data into this overhead bit-field (e.g ., the udl bit # 1 or the c21 bit-field). 1- configures the ds3/e3 frame generator block to not externally accept and insert data into this overhead bit-field. 4 f bit mask [4]/ x bit # 2 r/w transmit f-bit error ? bit 5/x bit # 2: the exact function of this register bi t depends upon whether bit 7 (txohsrc), within the ?test register? (address location= 0xn30c) is set to ?1? or ?0?. if ?txohsrc? = 0 ? transmit f-bit error ? bit 5: this read/write bit-field permits the user to configure the ds3/e3 frame generator block to transmit ds3 frames with a single/particular erred f bit. this particular f-bit corresponds with the 5th f-bit, within a given outbound ds3 frame. the ds3/e3 frame generator bl ock will perform an xor operation with the contents of this bit-field and value of the 5th f-bit. the results of this calculation will be written back into the 5th f-bit position, within each outbound ds3 frame. the user should set this bit-field to ?0? for normal (e.g., un-erred) operation. if ?txohsrc? = 1 - insert enable for x bit # 2: this read/write bit-field permits the user to configure the ds3/e3 frame generator block to externally accept an overhead bit (from ?up-stream? circuitry) and insert it into the ?x-bit # 2? bit-fi eld, within the outbound ds3 data-stream. 0 - configures the ds3/e3 frame generator block to externally accept and insert data into this overhead bit-field (e.g., the x bit # 2). 1- configures the ds3/e3 frame generator block to not externally accept and insert data into this overhead bit-field. 3 f bit mask [3]/ r/w transmit f-bit error ? bit 4/feac bit (c13):
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 516 feac bit (c13) the exact function of this register bi t depends upon whether bit 7 (txohsrc), within the ?test register? (address location= 0xn30c) is set to ?1? or ?0?. if ?txohsrc? = 0 ? transmit f-bit error ? bit 4: this read/write bit-field permits the user to configure the ds3/e3 frame generator block to transmit ds3 frames with a single/particular erred f bit. this particular f-bit corresponds with the 4th f-bit, within a given outbound ds3 frame. the ds3/e3 frame generator bl ock will perform an xor operation with the contents of this bit-field and value of the 4th f-bit. the results of this calculation will be written back into the 4th f-bit position, within each outbound ds3 frame. the user should set this bit-field to ?0? for normal (e.g., un-erred) operation. if ?txohsrc? = 1 - insert enable for feac or c13 bit: this read/write bit-field permits the user to configure the ds3/e3 frame generator block to externally accept an overhead bit (from ?up-stream? circuitry) and insert it into the ?feac (or c13)? bit-field, within the outbound ds3 data- stream. 0 - configures the ds3/e3 frame generator block to externally accept and insert data into this overhead bit-field (e.g., the feac or the c13 bit-field). 1- configures the ds3/e3 frame generator block to not externally accept and insert data into this overhead bit-field. 2 f bit mask [2]/ na bit (c12) r/w transmit f-bit error ? bit 3/na bit (c12): the exact function of this register bi t depends upon whether bit 7 (txohsrc), within the ?test register? (address location= 0xn30c) is set to ?1? or ?0?. if ?txohsrc? = 0 ? transmit f-bit error ? bit 3: this read/write bit-field permits the user to configure the ds3/e3 frame generator block to transmit ds3 frames with a single/particular erred f bit. this particular f-bit corresponds with the 3rd f-bit, within a given outbound ds3 frame. the ds3/e3 frame generator bl ock will perform an xor operation with the contents of this bit-field and value of the 3rd f-bit. the results of this calculation will be written back into the 3 rd f-bit position, within each outbound ds3 frame. the user should set this bit-field to ?0? for normal (e.g., un-erred) operation. if ?txohsrc? = 1 - insert enable for na or c12 bit: this read/write bit-field permits the user to configure the ds3/e3 frame generator block to externally accept an overhead bit (from ?up-stream? circuitry) and insert it into the ?na (or c12)? bit-field, within the outbound ds3 data- stream. 0 - configures the ds3/e3 frame generator block to externally accept and insert data into this overhead bit-field (e.g., the na or the c12 bit-field). 1- configures the ds3/e3 frame generator block to not externally accept and insert data into this overhead bit-field. 1 f bit mask [1]/ aic bit (c11) r/w transmit f-bit error ? bit 2/aic bit (c11): the exact function of this register bi t depends upon whether bit 7 (txohsrc), within the ?test register? (address location= 0xn30c) is set to ?1? or ?0?. if ?txohsrc? = 0 ? transmit f-bit error ? bit 2: this read/write bit-field permits the user to configure the ds3/e3 frame generator block to transmit ds3 frames with a single/particular erred f bit. this particular f-bit corresponds with the 2 nd f-bit, within a given outbound ds3 frame. the ds3/e3 frame generator bl ock will perform an xor operation with the contents of this bit-field and value of the 2 nd f-bit. the results of this
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 517 calculation will be written back into the 2 nd f-bit position, within each outbound ds3 frame. the user should set this bit-field to ?0? for normal (e.g., un-erred) operation. if ?txohsrc? = 1 - insert enable for aic or c11 bit: this read/write bit-field permits the user to configure the ds3/e3 frame generator block to externally accept an overhead bit (from ?up-stream? circuitry) and insert it into the ?aic (or c11)? bit-field, within the outbound ds3 data-stream. 0 - configures the ds3/e3 frame generator block to externally accept and insert data into this overhead bit-fiel d (e.g., the aic or the c11 bit-field). 1- configures the ds3/e3 frame generator block to not externally accept and insert data into this overhead bit-field. 0 f bit mask [0]/ x bit # 1 r/w transmit f-bit error ? bit 1/x bit # 1: the exact function of this register bi t depends upon whether bit 7 (txohsrc), within the ?test register? (address location= 0xn30c) is set to ?1? or ?0?. if ?txohsrc? = 0 ? transmit f-bit error ? bit 1: this read/write bit-field permits the user to configure the ds3/e3 frame generator block to transmit ds3 frames with a single/particular erred f bit. this particular f-bit corresponds with the 1 st f-bit, within a given outbound ds3 frame. the ds3/e3 frame generator bl ock will perform an xor operation with the contents of this bit-field and value of the 1 st f-bit. the results of this calculation will be written back into the 1 st f-bit position, within each outbound ds3 frame. the user should set this bit-field to ?0? for normal (e.g., un-erred) operation. if ?txohsrc? = 1 - insert enable for x bit # 1: this read/write bit-field permits the user to configure the ds3/e3 frame generator block to externally accept an overhead bit (from ?up-stream? circuitry) and insert it into the ?x-bit # 1? bit-fi eld, within the outbound ds3 data-stream. 0 - configures the ds3/e3 frame generator block to externally accept and insert data into this overhead bit-field (e.g., the x-bit # 1 bit-field). 1- configures the ds3/e3 frame generator block to not externally accept and insert data into this overhead bit-field.
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 518 table 353: transmit ds3 pattern register (address location= 0xn34c, where n ranges from 0x02 to 0x04) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 txais - unframed all ones ds3 ais non-stuck stuff txlos pattern select transmit_idle_p attern[3:0] r/w r/w r/o r/w r/w r/w r/w r/w 0 0 0 0 1 1 0 0 b it n umber n ame t ype d escription 7 txais - unframed all ones r/w transmit ais ? unframed all ones: this read/write bit-field permits the user to configure the ?ds3/e3 frame generator? block to transmit either of the following patterns, anytime it is configured to transmit the ais indicator. ? a ?framed, repeating 1, 0, 1, 0? pattern (per bellcore gr-499- core) or ? an ?unframed all ones? pattern. 0 ? configures both the ds3/e3 frame generator block and the ais/ds3 idle signal pattern generator (within the primary frame synchronizer block) to transmit the ?framed, repeating 1, 0, 1, 0, ? pattern; whenever it is configured to transmit the ais indicator. 1- configures both the ds3/e3 fram e generator and the ais/ds3 idle signal pattern generator (within t he primary frame synchronizer block) to transmit an ?unframed, all-ones? pattern, whenever it is configured to transmit the ais indicator. note: this configuration setting app lies to both the ds3/e3 frame generator block and the ais/ds3 idle signal pattern generator sub- block (within the primary frame synchronizer block) 6 ds3 ais non-stuck stuff r/w ds3 ais ? non-stuck stuff option ? ais pattern: this read/write bit-field (along with the ?txais ? unframed all ones? bit-field) permits the user to define the type of ais data-stream that both the ds3/e3 frame gener ator and the ais/ds3 idle signal pattern generator sub-block (withi n the primary frame synchronizer block) will transmit, as described below. 0 ? configures the ds3/e3 frame generator block and the ais/ds3 idle signal pattern generator sub-block to force all of the ?c? bits to ?0?, whenever it is configured to transmit a framed ais signal. 1 ? configures the ds3/e3 frame generator block and the ais/ds3 idle signal pattern generator sub-blo ck to not force all of the ?c? bits to ?0?, when it is configured to transmit a framed ais signal. in this case, the ?c? bits can be used to transport feac and pmdl messages. note: this bit-field is ignored if the ds3/e3 frame generator block and the ais/ds3 idle signal pattern generator sub-block has been configured to transmit an ?unframed ? all ones? type of ais signal. 5 unused r/w 4 txlos pattern select r/w transmit los pattern select: this read/write bit-field permits the user to configure the ?ds3/e3 frame generator? block to transmit either an ?all zeros? or an ?all ones? p attern, an y time it is confi g ured to transmit the ?los pattern? to
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 519 the remote terminal equipment, as described below. 0 ? configures the ds3/e3 frame generator to transmit an ?all zeros? pattern, whenever it is config ured to transmit the los pattern. 1 ? configures the ds3/e3 frame generator to transmit an ?all ones? pattern, whenever it is configur ed to transmit the los pattern. 3 - 0 tx_idle pattern[3:0] r/w transmit ds3 idle signal pattern: these read/write bit-fields permit the user to specify the type of framed, repetitive four-bit pattern that the ds3/e3 frame generator block should send, whenever it is transmitting the ?ds3 idle? pattern. note: setting these bit-fields to ?[1, 1, 0, 0] configures the ds3/e3 frame generator block to transmit the standard ?framed, repeating ?1, 1, 0, 0, ?? pa ttern (per bellcore gr-499-core) requirements.
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 520 1.10.6 t ransmit e3, itu-t g.751 r elated r egisters table 354: txe3 configuration register ? g.751 (address location= 0xn330, where n ranges from 0x02 to 0x04) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 txbip-4 enable txasrcsel[1:0] txnsrcsel[1:0] txais enable txlos enable txfas source sel r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 txbip-4 enable r/w transmit bip-4 enable: this read/write bit-field permits the user to configure the ds3/e3 frame generator block to do the following: ? to compute the bip-4 value over a given outbound e3 frame. ? to insert this bip-4 value into the last nibble-field within the very next e3 frame. 0 ? does not configure this option. in this case, the last nibble (of each ?outbound? e3 frame) will contain payload data. 1 ? configures the ds3/e3 frame generator block to compute and insert the bip-4 value. 6 - 5 txasrcsel[1:0] r/w transmit a bit source select[1:0]: these two read/write bit-fields permit the user to specif y the source or type of data that is being carried via the ?a? bits, within each ?outbound? e3 data stream, as indicated below. txasrcsel[1:0] resulting source of a bit 0 0 the ?txa? bit-field, within the ?txe3 service bit? register (address location= 0xn335). 0 1 not valid - do not use. 1 0 the ?a? bit is sourced via up-stream circuitry and inserted into the ?outbound e3 data-stream. this is discussed in greater detail in section _. 1 1 the companion primary frame synchronizer block. in this case, the a bit will transmit the febe indicator to the remote terminal equipment. the a bit will be set to ?1? when the companion primary frame synchronizer block detects a bip-4 error, and will be set to ?0? when the primary frame synchronizer block detects un-erred e3 frames.
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 521 4 ? 3 txnsrcsel[1:0] r/w transmit n bit source select[1:0]: these two read/write bit-fields permit the user to specif y the source or type of data that is being carried via the ?n? bits, within each ?outbound? e3 data stream, as indicated below. txnsrcsel[1:0] resulting source of n bit 0 0 the ?txn? bit-field, within the ?txe3 service bit? register (address location= 0xn335). 0 1 not valid ? do not use. 1 0 the transmit lapd controller sub- block (within the ds3/e3 frame generator block) in this case, the n bit will function as the lapd/pmdl channel. 1 1 the ?n? bit is accepted (via ?up-stream? circuitry) and inserted into the outbound e3 data-stream. this is discussed in greater detail in section _. 2 txais enable r/w transmit ais indicator: this read/write bit-field permits the user to (by software control) force the ds3/e3 frame generator block to generate and transmit the ais indicator to the remote terminal equipment, as described below. 0 ? does not configure the ds3/e3 frame generator block to generate and transmit the ais indicator. in th is case, the ds3/e3 frame generator block will transmit normal e3 traffic. 1 ? configures the ds3/e3 fram e generator block to generate and transmit the ais indicator. in this case, the ds3/e3 frame generator will force all bits (within the ?outbound? e3 data stream) to an ?unframed, all ones? pattern. note: this bit-field is ignored if the ds3/e3 frame generator block has been configured to transmit the los pattern. 1 txlos enable r/w transmit los (pattern) enable: this read/write bit-field permits the user to (by software control) force the ds3/e3 frame generator block to transmit the los (loss of signal) pattern to the remote terminal equipment, as described below. 0 ? does not configure the ds3/e3 frame generator block to generate and transmit the los pattern. in this case, the ds3/e3 frame generator block will be transmiting normal e3 traffic. 1 ? configures the ds3/e3 fram e generator block to generate and transmit the los pattern. in this case, the ds3/e3 frame generator block will force all bits (within the ?outbound? e3 data stream) to an ?all zeros? pattern. 0 txfas source sel r/w transmit fas source select: this read/write bit-field permits the user to specify the source of the fas (framing alignment signal), to be used in the ?outbound? e3 data- stream, as indicated below. 0 ? confi g ures the ds3/e3 frame generator block to internall y g enerate
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 522 and insert the fas bits within the outbound e3 data-stream. 1 ? configures the ds3/e3 frame gener ator block to accept the fas bits from ?up-stream? circuitry (via the transmit payload data input interface block) and to insert this data into the outbound e3 data-stream. this is discussed in greater detail in section _.
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 523 table 355: txe3 lapd configuration register ? g.751 (address location= 0xn333, where n ranges from 0x02 to 0x04) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 unused auto retransmit reserved transmit lapd message length transmit lapd enable r/o r/o r/o r/o r/w r/o r/w r/w 0 0 0 0 1 0 0 0 b it n umber n ame t ype d escription 7 - 4 unused r/o 3 auto retransmit r/w auto-retransmit of lapd message: this read/write bit-field permits the user to configure the transmit lapd controller sub-block (within the ds3/e3 frame generator block) to transmit pmdl messages, repeatedly at one-second intervals. once the user enables this feature, and then commands the transmit lapd controller sub-block to transmit a given pmdl message; the transmit lapd controller sub-block will then proceed to transmit this pmdl message (based upon the contents within the transmit lapd message buffer) repeatedly at one-second intervals. 0 ? disables the auto-retransmit feature. in this case, the transmit lapd controller sub-block will transmit this pmdl message only once, afterwards the transmit lapd controller sub-block will proceed to transmit a continuous stream of flag sequence octets (0x7e) via the dl bits, within each output ds3 frame. no more pmdl messages will be transmitted until the user commands another transmission. 1 ? enables the auto-retransmit feature. in this case, the transmit lapd controller sub-block will transmit pmdl messages (based upon the contents within the transmit lapd message buffer) repeatedly at one-second intervals. note: this bit-field is ignored if the tr ansmit lapd controller sub-block is disabled. 2 reserved r/o 1 transmit lapd message length r/w transmit lapd message length select: this read/write bit-field permits the user to specify the length of the payload data within the outbound lapd/pmd l message, as indicated below. 0 ? configures the transmit lapd controller sub-block to transmit a lapd/pmdl message that has a payload data size of 76 bytes. 1 ? configures the transmit lapd controller sub-block to transmit a lapd/pmdl message that has a payload data size of 82 bytes. 0 transmit lapd enable r/w transmit lapd controller sub-block enable: this read/write bit-field permits the user to enable the transmit lapd controller sub--block, within the ds3/e3 frame generator block. once the user enables the transmit lapd controller sub-block, it will immediately begin transmitting the flag sequence octet (0 x7e) to the remote terminal via the outbound ?dl? bits, within each ds3 data stream. the transmit lapd controller sub-block will continue to do this until the user commands the transmit lapd controller sub-block to transmit a pmdl message.
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 524 0 ? disables the transmit lapd controller sub-block. 1 ? enables the transmit lapd controller sub-block.
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 525 table 356: txe3 lapd status/interrupt register ? g.751 (address location= 0xn334, where n ranges from 0x02 to 0x04) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 unused initiate transmission of lapd/ pmdl message transmit lapd controller busy transmit lapd interrupt enable transmit lapd interrupt status r/o r/o r/o r/o r/w r/o r/w rur 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 - 4 unused r/o 3 initiate transmission of lapd/ pmdl message r/w transmit lapd message command: a ?0? to ?1? transition, within this bit-field commands the transmit lapd controller sub-block to begin the following activities: ? reading out the contents of the transmit lapd message buffer. ? zero-stuffing of this data ? fcs calculation and insertion ? fragmentation of this composite pmdl message, and insertion into the ?n? bit-fields, within each outbound e3 frame. note: this bit-field is only active if the transmit lapd controller sub-block has been enabled. 2 transmit lapd controller busy r/o transmit lapd controller busy indicator: this ?read-only? bit-field indicates whether or not the transmit lapd controller sub-block is currently busy transmitting a pmdl message to the remote terminal equipment. the user can continuously poll this bit-field in order to check for completion of transmi ssion of the lapd/pmdl message. 0 ? indicates that the transmit lapd controller sub-block is not busy transmitting a pmdl message. 1 ? indicates that the transmit lapd co ntroller sub-block is currently busy transmitting a pmdl message. note: this bit-field is only active if t he transmit lapd controller sub-block has been enabled. 1 transmit lapd interrupt enable r/w transmit lapd interrupt enable: this read/write bit-field permits the user to either enable or disable the ?transmit lapd interrupt?. if the user enables this interrupt, then the ds3/e3 frame generator block will generate an interrupt anytime the transmit lapd controller sub-block has completed its transmission of a given lapd/pmdl message to the remote terminal. 0 ? disables transmit lapd interrupt. 1 ? enables transmit lapd interrupt. 0 transmit lapd interrupt status rur transmit lapd interrupt status: this reset-upon-read bit-field indicates whether or not the ?transmit lapd interrupt? has occurred since the last read of this register. 0 ? transmit lapd interru p t has not occurred since the last read of this
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 526 register. 1 ? transmit lapd interrupt has occurred since the last read of this register.
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 527 table 357: txe3 service bits register ? g.751 (address location= 0xn335, where n ranges from 0x02 to 0x04) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 unused txa txn r/o r/o r/o r/o r/o r/o r/w r/w 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 ? 2 unused r/o 1 txa r/w transmit a bit: this read/write bit-field permits the user to control the state of the ?a? bit, within each ?outbound? e3 frame, as indicated below. 0 ? forces each a bit (within the ?outbound? e3 frame) to ?0?. 1 ? forces each a bit (within the ?outbound? e3 frame) to ?1?. note: this bit-field is only valid if the ds 3/e3 frame generator block has been configured to use this bit-field as the source of the ?a? bit (e.g., if ?txasrcsel[1:0] = ?0, 0?). 0 txn r/w transmit n bit: this read/write bit-field permits the user to control the state of the ?n? bit, within each ?outbound? e3 frame, as indicated below. 0 ? forces each n bit (within the ?outbound? e3 frame) to ?0?. 1 ? forces each n bit (within the ?outbound? e3 frame) to ?1?. note: this bit-field is only valid if the ds 3/e3 frame generator block has been configured to use this bit-field as the source of the ?n? bit (e.g., if ?txnsrcsel[1:0] = ?0, 0?).
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 528 table 358: txe3 fas error mask upper register ? g.751 (address location= 0xn348, where n ranges from 0x02 to 0x04) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 unused txfas_error_mask_upper[4:0] r/o r/o r/o r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 ? 5 unused r/o 4 ? 0 txfas_error_mask_ upper[4:0] r/w txfas error mask upper[4:0]: these read/write bit-fields permit the user to insert bit errors into the upper five bits, within the fas (framing alignment signal), within the outbound e3 data stream. the ds3/e3 frame generator block will perform an xor operation with the contents of these fas bits, and this register. the results of this calculation will be inserted into the upper 5 fas bit positions within the ?outbound? e3 data stream. for each bi t-field (within this register) that is set to ?1?, the corresponding bi t, within the fas will be in error. note: for normal operation, the user should set this register to 0x00. table 359: txe3 fas error mask lower register ? g.751 (address location= 0xn349, where n ranges from 0x02 to 0x04) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 unused txfas_error_mask_lower[4:0] r/o r/o r/o r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 ? 5 unused r/o 4 ? 0 txfas_error_mask_lower[4:0] r/w txfas error mask lower[4:0]: these read/write bit-fields permit the user to insert bit errors into the lower five bi ts, within the fas (framing alignment signal), within the outbound e3 data stream. the ds3/e3 frame generator block will perform an xor operation with the contents of these fas bits, and this register. the results of this calculation will be inserted into the lower 5 fas bit positions within the ?outbound? e3 data stream. for each bit-field (within this register) that is set to ?1?, the corresponding bit, within the fas will be in error. note: for normal operation, the user should set this register to 0x00.
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 529 table 360: txe3 bip-4 mask register ? g.751 (address location= 0xn34a, where n ranges from 0x02 to 0x04) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 unused txbip-4_mask[3:0] r/o r/o r/o r/o r/w r/w r/w r/w 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 ? 4 unused r/o 3 - 0 txbip-4_mask_[3:0] r/w txbip-4 error mask[3:0]: these read/write bit-fields permit the user to insert bit errors into the bip-4 bits, within the outbound e3 data stream. the ds3/e3 frame generator block will perform an xor operation with the contents of the bip-4 bits, and this register. the results of this calculation will be inserted into the bip-4 bit positions within the ?outbound? e3 data stream. for each bit- field (within this register) that is set to ?1?, the corresponding bit, within the bip-4 will be in error. note: for normal operation, the user should set this register to 0x00.
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 530 1.10.7 t ransmit e3, itu-t g.832 r elated r egisters table 361: txe3 configuration register ? g.832 (address location= 0xn330, where n ranges from 0x02 to 0x04) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 unused txdl in nr reserved txais enable txlos enable txma rx r/o r/o r/o r/w r/o r/w r/w r/w 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 - 5 unused r/o 4 txdl in nr r/w transmit dl (data link channel) in nr byte: this read/write bit-field permits the user to configure the transmit lapd controller sub-block (within the ds3/e3 frame generator block) to use either the nr or the gc byte as the lapd/pmdl channel, as described below. 0 ? configures the transmit lapd controller sub-block to transmit all ?outbound? lapd/pmdl messages via the gc byte. 1 ? configures the transmit lapd controller sub-block to transmit all ?outbound? lapd/pmdl messages via the nr byte. 3 unused r/o 2 txais enable r/w transmit ais indicator: this read/write bit-field permits the us er to (by software control) force the ds3/e3 frame generator block to gener ate and transmit the ais indicator to the remote terminal equipment as described below. 0 ? does not configure the ds3/e3 fr ame generator block to generate and transmit the ais indicator. in this case, the ds3/e3 frame generator block will transmit normal e3 traffic. 1 ? configures the ds3/e3 frame gener ator block to generate and transmit the ais indicator. in this case, the ds 3/e3 frame generator will force all bits (within the ?outbound? e3 data stream) to an ?unframed, all ones? pattern. note: this bit-field is ignored if the ds3/e3 frame generator block has been configured to transmit the los pattern. 1 txlos enable r/w transmit los (pattern) enable: this read/write bit-field permits the us er to (by software control) force the ds3/e3 frame generator block to transmi t the los (loss of signal) pattern to the remote terminal equipment. 0 ? does not configure the ds3/e3 fr ame generator block to generate and transmit the los pattern. in this case, the ds3/e3 frame generator block will transmit normal e3 traffic. 1 ? configures the ds3/e3 frame gener ator block to generate and transmit the los pattern. in this case, the ds3/ e3 frame generator block will force all bits (within the ?outbound? e3 data stream) to an ?all zeros? pattern. 0 txma primary frame synchronizer block r/w transmit ma byte from primary frame synchronizer block select: this read/write bit-field permits the user to configure the ds3/e3 frame generator block to use either the primary frame synchronizer block or the ?tx ma byte ? register as the source of t he ferf/rdi and febe/rei bit fields
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 531 ma byte? register as th e source of the ferf/rdi and febe/rei bit-fields (within the ma byte-field of the ?out bound? e3 data stream); as indicated below. 0 ? configures the ds3/e3 frame genera tor block to read in the contents of the ?tx ma byte? register (address loc ation= 0xn336), and write this value into the ?ma? byte-field within each ?outbound? e3 frame. note: this option permits th e user to send the ferf/rdi and febe/rei indicators, under software control. 1 ? configures the ds3/e3 frame generator block to set the ferf/rdi and febe/rei bit-fields to values, bas ed upon conditions detected by the companion priimary frame synchronizer block.
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 532 table 362: txe3 lapd configuration register ? g.832 (address location= 0xn333, where n ranges from 0x02 to 0x04) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 unused auto retransmit reserved txlapd message length txlapd enable r/o r/o r/o r/o r/w r/o r/w r/w 0 0 0 0 1 0 0 0 b it n umber n ame t ype d escription 7 - 4 unused r/o 3 auto retransmit r/w auto-retransmit of lapd message: this read/write bit-field permits the user to configure the transmit lapd controller sub-block to transmit pm dl messages, repeatedly at one-second intervals. once the user enables this feature, and then commands the transmit lapd controller sub-block to transmit a given pmdl message; the transmit lapd controller sub-block will then proceed to transmit this pmdl message (based upon the contents within the transmit lapd message buffer) repeatedly at one-second intervals. 0 ? disables the auto-retransmit feature. in this case, the transmit lapd controller sub-block will only transmit the pmdl message once. afterwards the transmit lapd controller sub-block will proceed to transmit a continuous stream of flag sequence octets (0x7e) via either the nr or gc byte, within each output e3 frame. the transmit lapd controller sub-block will not transmit any more pmdl messages until the user commands another transmission. 1 ? enables the auto-retransmit feature. in this case, the transmit lapd controller sub-block will transmit pmdl messages (based upon the contents within the transmit lapd message buffer) repeatedly at one-second intervals. note: this bit-field is ignored if the tr ansmit lapd controller sub-block is disabled. 2 reserved r/o 1 transmit lapd message length r/w transmit lapd message length select: this read/write bit-field permits the us er to specify the length of the payload data within the outbound lapd/pmd l message, as indicated below. 0 ? configures the transmit lapd controller sub-block to transmit a lapd/pmdl message that has a payload data size of 76 bytes. 1 ? configures the transmit lapd controller sub-block to transmit a lapd/pmdl message that has a payload data size of 82 bytes. note: this bit-field is ignored if the tr ansmit lapd controller sub-block is disabled. 0 transmit lapd enable r/w transmit lapd controller sub-block enable: this read/write bit-field permits the user to enable the transmit lapd controller sub-block, within the ds3/e3 frame generator block. once the user enables the transmit lapd controller su b-block, it will immediately begin transmitting the flag sequence octet (0x7e) to the remote terminal via either the ?nr? or ?gc? bytes, within the ou tbound e3 data stream. the transmit lapd controller sub-block will continue to do this until the user commands the
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 533 transmit lapd controller sub-bl ock to transmit a pmdl message. 0 ? disables the transmit lapd controller sub-block. 1 ? enables the transmit lapd controller sub-block.
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 534 table 363: txe3 lapd status/interrupt register ? g.832 (address location= 0xn334, where n ranges from 0x02 to 0x04) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 unused initiate transmission of lapd/ pmdl message transmit lapd controller busy transmit lapd interrupt enable transmit lapd interrupt status r/o r/o r/o r/o r/w r/o r/w rur 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 - 4 unused r/o 3 initiate transmission of lapd/ pmdl message r/w transmit lapd message command: a ?0? to ?1? transition, within this bit-field commands the transmit lapd controller sub-block to begin the following activities: ? reading out the contents of the transmit lapd message buffer. ? zero-stuffing of this data ? fcs calculation and insertion ? fragmentation of this composite pmdl message, and insertion into either the ?nr? or ?gc? byte-fields, within each outbound e3 frame. note: this bit-field is only active if t he transmit lapd controller sub-block has been enabled. 2 transmit lapd controller busy r/o transmit lapd controller busy indicator: this ?read-only? bit-field indicates whether or not the transmit lapd controller sub-block is currently busy transmitting a pmdl message to the remote terminal equipment. the user can continuously poll this bit-field in order to check for completion of transmi ssion of the lapd/pmdl message. 0 ? indicates that the transmit lapd controller sub-block is not busy transmitting a pmdl message. 1 ? indicates that the transmit lapd co ntroller sub-block is currently busy transmitting a pmdl message. note: this bit-field is only active if t he transmit lapd controller sub-block has been enabled. 1 transmit lapd interrupt enable r/w transmit lapd interrupt enable: this read/write bit-field permits the user to either enable or disable the ?transmit lapd interrupt?. if the user enables this interrupt, then the ds3/e3 frame generator block will generate an interrupt anytime the transmit lapd controller sub-block has completed its transmission of a given lapd/pmdl message to the remote terminal. 0 ? disables transmit lapd interrupt. 1 ? enables transmit lapd interrupt. 0 transmit lapd interrupt status rur transmit lapd interrupt status: this reset-upon-read bit-field indicates whether or not the ?transmit lapd interrupt? has occurred since the last read of this register, as described below. 0 ? indicates that the transmit lapd interru p t has not occurred since the last
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 535 read of this register. 1 ? indicates that the transmit lapd interrupt has occurred since the last read of this register.
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 536 table 364: txe3 gc byte register ? g.832 (address location= 0xn335, where n ranges from 0x02 to 0x04) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 txgc_byte[7:0] r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 ? 0 txgc_byte[7:0] r/w transmit gc byte: this read/write bit-field permits the user to specify the contents of the gc byte, within the ?outbound? e3 data stream. the ds3/e3 frame generator block will load the contents of this register in the gc byte-field, within each outbound e3 frame. note: this register is ignored if the gc byte is configured to be the ?lapd/pmdl? channel. table 365: txe3 ma byte register ? g.832 (addr ess location= 0xn336, where n ranges from 0x02 to 0x04) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 txma byte[7:0] r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 1 0 0 0 0 b it n umber n ame t ype d escription 7 ? 0 txma_byte[7:0] r/w transmit ma byte: this read/write bit-field permits the user to specify the contents of the ma byte, within the ?outbound? e3 data stream. the ds3/e3 frame generator block will load the contents of this register in the ma byte-field, within each outbound e3 frame. note: this register is ignored if the ?transmit ma byte ? from primary frame synchronizer block? option is selected (e.g., by setting ?txma primary frame synchronizer block = 1?). this feature permits the user to transmit the ferf/rdi and febe/rei indicators upon software command.
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 537 table 366: txe3 nr byte register ? g.832 (addr ess location= 0xn337, where n ranges from 0x02 to 0x04) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 txnr_byte[7:0] r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 ? 0 txnr_byte[7:0] r/w transmit nr byte: this read/write bit-field permits the user to specify the contents of the nr byte, within the ?outbound? e3 data stream. the ds3/e3 frame generator block will load the contents of this register in the nr byte-field, within each outbound e3 frame. note: this register is ignored if the nr byte is configured to be the ?lapd/pmdl? channel. table 367: txe3 trail-trace - 0 register ? g.832 (address location= 0xn338, where n ranges from 0x02 to 0x04) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 txttb_byte_0 r/w r/w r/w r/w r/w r/w r/w r/w 1 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 ? 0 txttb_byte_0[7:0] r/w transmit trail-trace message - byte 0: these read/write bits permit the user to specify the contents of byte 0, within the ?outbound? trail-trace message, which is to be transmitted via the outbound e3 data stream. by default, the msb (most significant bit) of this register bit will be set to ?1? in order to permit the remote te rminal to be able to identify this particular byte, as being the first byte of the ?trail-trace buffer? message.
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 538 table 368: txe3 trail-trace-1 register ? g.832 (address location = 0xn339, where n ranges from 0x02 to 0x04) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 txttb_byte_1 r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 ? 0 txttb_byte_1[7:0] r/w transmit trail-trace message - byte 1: these read/write bits permit the user to specify the contents of the second byte (byte 1) within the ?trail-trace message? that is be be transported via the outbound e3 data stream. note: in order to permit the proper reception of this particular trail- trace message, it is imperative t hat the user set the msb (most significant bit) within this register to ?0?. table 369: txe3 trail-trace-2 register ? g.832 (address location= 0xn33a, where n ranges from 0x02 to 0x04) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 txttb_byte_2 r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 ? 0 txttb_byte_2[7:0] r/w transmit trail-trace message - byte 2: these read/write bits permit the us er to specify the contents of the third byte (byte 2) within the ?trail-trace message? that is to be transported via the outbound e3 data stream. note: in order to permit the proper reception of this particular trail- trace message, it is imperative t hat the user set the msb (most significant bit) within this register to ?0?.
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 539 table 370: txe3 trail-trace-3 register ? g.832 (address location= 0xn33b, where n ranges from 0x02 to 0x04) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 txttb_byte_3 r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 ? 0 txttb_byte_3[7:0] r/w transmit trail-trace message - byte 3: these read/write bits permit the user to specify the contents of the fourth byte (byte 3) within the ?t rail-trace message? that is to be transported via the outbound e3 data stream. note: in order to permit the proper reception of this particular trail- trace message, it is imperative t hat the user set the msb (most significant bit) within this register to ?0?. table 371: txe3 trail-trace-4 register ? g.832 (address location= 0xn33c, where n ranges from 0x02 to 0x04) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 txttb_byte_4 r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 ? 0 txttb_byte_4[7:0] r/w transmit trail-trace message - byte 4: these read/write bits permit the user to specify the contents of the fifth byte (byte 4) within the ?trail-trace message? that is to be transported via the outbound e3 data stream. note: in order to permit the proper reception of this particular trail- trace message, it is imperative t hat the user set the msb (most significant bit) within this register to ?0?.
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 540 table 372: txe3 ttb-5 register ? g.832 (address location= 0xn33d, where n ranges from 0x02 to 0x04) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 txttb_byte_5 r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 ? 0 txttb_byte_5[7:0] r/w transmit trail-trace message - byte 5: these read/write bits permit the user to specify the contents of the sixth byte (byte 5) within the ?trail-trace message? that is to be transported via the outbound e3 data stream. note: in order to permit the proper reception of this particular trail- trace message, it is imperative t hat the user set the msb (most significant bit) within this register to ?0?. table 373: txe3 trail-trace-6 register ? g.832 (address location= 0xn33e, where n ranges from 0x02 to 0x04) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 txttb_byte_6 r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 ? 0 txttb_byte_6[7:0] r/w transmit trail-trace message - byte 6: these read/write bits permit the us er to specify the contents of the seventh byte (byte 6) within the ?trail-trace message? that is to be transported vai the outbound e3 data stream. note: in order to permit the proper reception of this particular trail- trace message, it is imperative t hat the user set the msb (most significant bit) within this register to ?0?.
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 541 table 374: txe3 trail-trace-7 register ? g.832 (address location= 0xn33f, where n ranges from 0x02 to 0x04) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 txttb_byte_7 r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 ? 0 txttb_byte_7[7:0] r/w transmit trail-trace message - byte 7: these read/write bits permit the user to specify the contents of the eighth byte (byte 7) within the ?trail-trace message? that is to be transported via the outbound e3 data stream. note: in order to permit the proper reception of this particular trail- trace message, it is imperative t hat the user set the msb (most significant bit) within this register to ?0?.
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 542 table 375: txe3 trail-trace- 8 register ? g.832 (address location = 0xn340, where n ranges from 0x02 to 0x04) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 txttb_byte_8 r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 ? 0 txttb_byte_8[7:0] r/w transmit trail-trace message - byte 8: these read/write bits permit the us er to specify the contents of the ninth byte (byte 8) within the ?t rail-trace message? that is to be transported via the outbound e3 data stream. note: in order to permit the proper reception of this particular trail- trace message, it is imperative t hat the user set the msb (most signficant bit) within this register to ?0?. table 376: txe3 trail-trace-9 register ? g.832 (address location= 0xn341, where n ranges from 0x02 to 0x04) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 txttb_byte_9 r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 ? 0 txttb_byte_9[7:0] r/w transmit trail-trace message - byte 9: these read/write bits permit the us er to specify the contents of the tenth byte (byte 9) within the ?t rail-trace message? that is to be transported via the outbound e3 data stream. note: in order to permit the proper reception of this particular trace trail message, it is imperative t hat the user set the msb (most signficant bit) within this register to ?0?.
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 543 table 377: txe3 trail-trace-10 register ? g.832 (address location= 0xn342, where n ranges from 0x02 to 0x04) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 txttb_byte_10 r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 ? 0 txttb_byte_10[7:0] r/w transmit trail-trace message - byte 10: these read/write bits permit the us er to specify the contents of the eleventh byte (byte 10) within the ?trail-trace message? that is to be transported via the outbound e3 data stream. note: in order to permit the proper reception of this particular trail- trace message, it is imperative t hat the user set the msb (most significant bit) within this register to ?0?.
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 544 table 378: txe3 trail-trace-11 register ? g.832 (address location= 0xn343, where n ranges from 0x02 to 0x04) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 txttb_byte_11 r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 ? 0 txttb_byte_11[7:0] r/w transmit trail-trace message - byte 11: these read/write bits permit the us er to specify the contents of the twelfth byte within the ?trail-trace message? that is to be transported via the outbound e3 data stream. note: in order to permit the proper reception of this particular trail- trace message, it is imperative t hat the user set the msb (most signfiicant bit) within this register to ?0?. table 379: txe3 trail-trace-12 register ? g.832 (address location= 0xn344, where n ranges from 0x02 to 0x04) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 txttb_byte_12 r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 ? 0 txttb_byte_12[7:0] r/w transmit trail-trace message - byte 12: these read/write bits permit the us er to specify the contents of the 13 th byte (byte 12) within the ?trail-trace message? that is to be transported via the outbound e3 data stream. note: in order to permit the proper reception of this particular trail- trace message, it is imperative t hat the user set the msb (most signficant bit) within this register to ?0?.
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 545 table 380: txe3 ttb-13 register ? g.832 (address location= 0xn345, where n ranges from 0x02 to 0x04) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 txttb_byte_13 r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 ? 0 txttb_byte_13[7:0] r/w transmit trail-trace message - byte 13: these read/write bits permit the us er to specify the contents of the 14 th byte (byte 13) within the ?trail-trace message? that is to be transported via the outbound e3 data stream. note: in order to permit the proper reception of this particular trail- trace message, it is imperative t hat the user set the msb (most signficant bit) within this register to ?0?.
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 546 table 381: txe3 trail-trace-14 register ? g.832 (address location= 0xn346, where n ranges from 0x02 to 0x04) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 txttb_byte_14 r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 ? 0 txttb_byte_14[7:0] r/w transmit trail-trace message - byte 14: these read/write bits permit the us er to specify the contents of the 15 th byte (byte 14) within the ?trail-trace message? that is to be transported via the outbound e3 data stream. note: in order to permit the proper reception of this particular trail- trace message, it is imperative t hat the user set the msb (most signficant bit) within this register to ?0?. table 382: txe3 trail-trace-15 register ? g.832 (address location= 0xn347, where n ranges from 0x02 to 0x04) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 txttb_byte_15 r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 ? 0 txttb_byte_15[7:0] r/w transmit trail-trace message - byte 15: these read/write bits permit the us er to specify the contents of the 16 th (and last) byte within the ?trail-trace message? that is to be transported via the outbound e3 data stream. note: in order to permit the proper reception of this particular trail- trace message, it is imperative t hat the user set the msb (most signficant bit) within this register to ?0?.
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 547 table 383: txe3 fa1 error mask register ? g.832 (address location= 0xn348, where n ranges from 0x02 to 0x04) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 txfa1_mask_byte[7:0] r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 - 0 txfa1_mask_byte[7:0] r/w txfa1 error mask byte[7:0]: these read/write bit-fields permit the user to insert bit errors into the fa1 bytes, within the outbound e3 data stream. the ds3/e3 frame generator blo ck will perform an xor operation with the contents of the fa1 byte, and this register. the results of this calculation will be inserted into the fa1 byte position within the ?outbound? e3 data stream. for eac h bit-field (within this register) that is set to ?1?, the corresponding bit, within the fa1 byte will be in error. note: for normal operation, the user should set this register to 0x00. table 384: txe3 fa2 error mask register ? g.832 (address location= 0xn349, where n ranges from 0x02 to 0x04) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 txfa2_mask_byte[7:0] r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 - 0 txfa2_mask_byte[7:0] r/w txfa2 error mask byte[7:0]: these read/write bit-fields permit the user to insert bit errors into the fa2 bytes, within the outbound e3 data stream. the ds3/e3 frame generator block will perform an xor operation with the contents of the fa2 byte, and this register. the results of this calculation will be inserted into the fa2 byte position within the ?outbound? e3 data stream. for each bit-field (within this register) that is se t to ?1?, the corresponding bit, within the fa2 byte will be in error. note: for normal operation, the user should set this register to 0x00.
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 548 table 385: txe3 bip-8 error mask register ? g.832 (address location= 0xn34a, where n ranges from 0x02 to 0x04) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 txbip-8_mask_byte[7:0] r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 - 0 txbip-8_mask_byte[7:0] r/w txbip-8 (b1) error mask[7:0]: these read/write bit-fields pe rmit the user to insert bit errors into the b1 bytes, within the outbound e3 data stream. the ds3/e3 frame generator block will perform an xor operation with the contents of the b1 byte, and this register. the results of this calculation will be inserted into the b1 byte position within the ?outbound? e3 data stream. for each bit- field (within this register) that is set to ?1?, the corresponding bit, within the b1 byte will be in error. note: for normal operation, the user should set this register to 0x00.
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 549 table 386: txe3 ssm register ? g.832 (address location= 0xn34b, where n ranges from 0x02 to 0x04) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 txssm enable unused txssm[3:0] r/w r/o r/o r/o r/w r/w r/w r/w 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 txssm enable r/w transmit ssm enable: this read/write bit-field permits the user to configure the ds3/e3 frame generator block to operate in either the ?old itu-t g.832 framing? format or in the ?new itu-t g.832 framing? format, as described below. 0 ? configures the ds3/e3 frame g enerator block to support the ?pre october 1998? version of the e3, itu-t g.832 framing format. 1 ? configures the ds3/e3 frame generator block to support the ?october 1998? version of the e3, itu-t g.832 framing format. 6 - 4 unused r/o 3 - 0 txssm[3:0] r/w transmit synchronization status message[3:0]: these read/write bit-fields permit th e user to specify the contents of the ?outbound? synchronization stat us message (ssm) that is to be transported vai the ?outbound? e3 data-stream. the transmit ssm controller sub-block (within the ds3/e3 frame generator block) will then proceed to transport this ssm via the outbound e3 data-stream. note: these bit-fields are only active if the ds3/e3 frame generator block is active, and if bit 7 (txssm enable) of this register is set to ?1?.
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 550 1.10.8 ais/pdi-p a larm e nable r egister table 387: receive ds3/e3 ais/pdi-p alarm enab le register ? primary frame synchronizer block (address location= 0xn34d, where n ranges from 0x02 to 0x04) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 unused transmit pdi- p (down- stream) upon los transmit ais (down- stream) upon los transmit pdi- p (down- stream) upon lof transmit ais (down- stream) upon lof transmit pdi- p (down- stream) upon ais transmit ais (down- stream) upon ais r/o r/o r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 - 6 unused r/o 5 transmit pdi-p (down-stream) upon los r/w transmit the pdi-p indicator (down-stream) upon declaration of the ds3/e3 los defect condition: this read/write bit-field permits the user to configure the ds3/e3 framer block (via the primary fr ame synchronizer block) and the transmit sonet poh processor block to automatically tr ansmit the pdi- p (path ? payload defect indicator) anytime the los defect is declared within the ds3/e3 ingress path. more specifically, if this configurat ion is implemented then the following events will occur. if the primary frame synchronizer block is operating in the ?ds3/e3 ingress? path (e.g., if the ds3/e3 fr amer block has been configured to operate in frame generator/frame sy nchronizer configuration # 0xe6), and if it were to declare the los defect condition (within the ingress path), then the corresponding transmit sonet poh processor block will automatically transmit the pdi-p indicator (via its sts-1 signal, within the outbound composite sts-3 signal), by setting the c2 byte (within each ?down-stream? sts-1 spe) to the va lue ?0xfc?. the transmit sonet poh processor block will continue to transmit the pdi-p indicator for the duration that the primary frame synchronizer block declares the los defect condition. once the primary frame synchroniz er block clears the los defect, then the transmit sonet poh processor block will automatically terminate its transmission of the pdi-p indicator by setting the c2 byte (within each ?down-stream? sts-1 spe) to the ?0x04?. 0 ? disables this ?transmit pdi-p (down-stream) upon los feature. 1 ? enables this ?transmit pdi-p (down-stream) upon los feature. note: the user should only invoke th is feature if t he primary frame synchronizer block has been configured to operate in the ds3/e3 ingress path.
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 551 4 transmit ais (down-stream) upon los r/w transmit the ds3/e3 ais indicator (down-stream) upon declaration of the los defect condition: this read/write bit-field permits the user to configure the ds3/e3 framer block to do all of the followi ng, if the los defect is declared. if the primary frame synchronizer block declares the los detect (within its receive path) then the ais/ds3 idle signal pattern generator (within the primary frame synchronizer blo ck) will automatically transmit the ds3/e3 ais indicator, via its output pa th. in this case, the ais/ds3 idle signal pattern generator will transmit the ais indicator (in the down- stream path) for the duration that t he primary frame synchronizer block declares the los defect condition. once the primary frame synchroniz er block clears the los defect condition, then the ais/ds3 idle signal pattern generator (within the primary frame synchronizer block) will automatically terminate its transmission of the ds3/e3 ais indicator, and will permit normal ds3/e3 traffic to pass through the primary frame synchronizer block (towards the down-stream signal path). 0 ? disables the ?transmit ais (down-stream) upon los feature. 1 ? enables the ?transmit ais (down-stream) upon los feature. 3 transmit pdi-p (down-stream) upon lof r/w transmit pdi-p indicator (down- stream) upon declaration of the ds3/e3 lof defect condition: this read/write bit-field permits the user to configure the ds3/e3 framer block (via the primary fr ame synchronizer block) and the transmit sonet poh processor block to automatically tr ansmit the pdi- p (path ? payload defect indicator) anytime the lof defect is declared within the ds3/e3 ingress path. more specifically, if this configurat ion is implemented then the following events will occur. if the primary frame synchronizer block is operating in the ?ds3/e3 ingress? path (e.g., if the ds3/e3 fr amer block has been configured to operate in the frame generator/fram e synchronizer configuration # 0xe6), and if it were to declare t he lof/oof defect condition (within the ingress path), then the correspondi ng transmit sonet poh processor block will automatically transmit the pdi-p indicator (via its sts-1 signal, within the outbound composite sts-3 signal), by setting the c2 byte (within each ?down-stream? sts-1 spe) to the value ?0xfc?. the transmit sonet poh processor block wi ll continue to transmit the pdi-p indicator for the duration that the primary frame synchronizer block declares the lof defect condition. once the primary frame synchronizer block clears the lof defect, then the transmit sonet poh processor block will automatically terminate its transmission of the pdi-p indicator by setting the c2 byte (within each ?down-stream? sts-1 spe) to the ?0x04?. 0 ? disables this ?transmit pdi-p (down-stream) upon lof feature. 1 ? enables this ?transmit pdi-p (down-stream) upon lof feature. notes: i. the user should only invoke this feature if the primary frame synchronizer block has been configured to operate in the ds3/e3 ingress path. ii. for ds3 applications, this automatic transmission of pdi-p will occur whenever the primary frame synchronizer block declares the oof defecf condition.
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 552 2 transmit ais (down-stream) upon lof r/w transmit the ds3/e3 ais indicator (down-stream) upon declaration of the lof defect condition: this read/write bit-field permits the user to configure the ds3/e3 framer block to do all of the followi ng, if the lof defect is declared. if the primary frame synchronizer block declares the lof detect (within its receive path) then the ais/ds3 idle signal pattern generator (within the primary frame synchronizer blo ck) will automatically transmit the ds3/e3 ais indicator, via its output pa th. in this case, the ais/ds3 idle signal pattern generator will transmit the ais indicator (in the down- stream path) for the duration that t he primary frame synchronizer block declares the ds3/e3 lof defect condition. once the primary frame synchroniz er block clears the lof/oof defect condition, then the ais/ds3 idle signal pattern generator (within the primary frame synchronizer block) will automatically terminate its transmission of the ds3/e3 ais indicator, and will permit normal ds3/e3 traffic to pass through the primary frame synchronizer block (towards the down-stream signal path). 0 ? disables the ?transmit ais (down-stream) upon lof feature. 1 ? enables the ?transmit ais (down-stream) upon lof feature. 1 transmit pdi-p (down-stream) upon ais r/w transmit pdi-p (down-stream) upon ais: this read/write bit-field permits the user to configure the ds3/e3 framer block (via the primary fr ame synchronizer block) and the transmit sonet poh processor block to automatically tr ansmit the pdi- p (path ? payload defect indicator) anytime the ais defect is declared within the ds3/e3 ingress path. more specifically, if this configurat ion is implemented then the following events will occur. if the primary frame synchronizer block is operating in the ?ds3/e3 ingress? path (e.g., if the ds3/e3 fr amer block has been configured to operate in frame generator/frame sy nchronizer configuration # 0xe6), and if it were to declare the ais defec t condition (within the ingress path), then the corresponding transmit sonet poh processor block will automatically transmit the pdi-p indicator, by setting the c2 byte (within each ?down-stream? sts-1 spe) to the value ?0xfc?. the transmit sonet poh processor block will continue to transmit the pdi-p indicator for the duration that the primary fram e synchronizer block declares the ais defect condition. once the primary frame synchronizer block clears the ais defect, then the transmit sonet poh processor block will automatically terminate its transmission of the pdi-p indicator by setting the c2 byte (within each ?down-stream? sts-1 spe) to the ?0x04?. 0 ? disables this ?transmit pdi-p (down-stream) upon ais feature. 1 ? enables this ?transmit pdi-p (down-stream) upon ais feature. note: the user should only invoke th is feature if t he primary frame synchronizer block has been configured to operate in the ds3/e3 ingress path. 0 transmit ais (down-stream) upon ais r/w transmit the ds3/e3 ais indicator (down-stream) upon declaration of the ais defect condition: this read/write bit-field permits the user to configure the ds3/e3 framer block to do all of the followi ng, if the ais defect is declared. if the primary frame synchronizer block declares the ais detect (within its receive path) then the ais/ds3 idle signal pattern generator (within the primary frame synchronizer blo ck) will automatically transmit the ds3/e3 ais indicator, via its out p ut path. in this case, the ais/ds3 idle
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 553 signal pattern generator will transmit the ais indicator (in the down- stream path) for the duration that t he primary frame synchronizer block declares the ds3/e3 ais defect condition. once the primary frame synchronizer block clears the ais defect condition, then the ais/ds3 idle signal pattern generator (within the primary frame synchronizer block) will automatically terminate its transmission of the ds3/e3 ais indicator, and will permit normal ds3/e3 traffic to pass through the primary frame synchronizer block (towards the down-stream signal path). 0 ? disables the ?transmit ais (down-stream) upon ais feature. 1 ? enables the ?transmit ais (down-stream) upon ais feature.
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 554 table 388: receive ds3/e3 ais/pdi-p alarm enable register ? secondary frame synchronizer block (address location= 0xn3f2, where n ranges from 0x02 to 0x04) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 unused transmit pdi-p (down- stream) upon los transmit ais (down- stream) upon los transmit pdi-p (down- stream) upon lof transmit ais (down- stream) upon lof transmit pdi-p (down- stream) upon ais transmit ais (down- stream) upon ais r/o r/o r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 - 6 unused r/o 5 transmit pdi- p (down- stream) upon los r/w transmit pdi-pindicator (down-stream ) upon declaration of the ds3/e3 los defect condition: this read/write bit-field permits the user to configure the ds3/e3 framer block (via the secondary frame synchronzer block) and the transmit sonet poh processor block to automatically transmit the pdi-p (path ? payload defect indicator) anytime the los defect is declared within the ds3/e3 ingress path. more specifically, if this configurati on is implemented then the following events will occur. if the secondary frame synchronizer block is operating in the ?ds3/e3 ingress? path (e.g., if the ds3/e3 framer block ha s been configured to operate in frame generator/frame synchronizer configuration # 0xc0), and if it were to declare the los defect condition (within the ingress path), then the corresponding transmit sonet poh processor block will automatically transmit the pdi-p indicator (via its sts-1 signal, within the outbound composite sts-3 signal) by setting the c2 byte (within each ?down-stream? sts-1 spe) to the value ?0xfc?. the transmit sonet poh processor block will continue to transmit the pdi-p indicator for the duration that the seco ndary frame synchronizer block declares the los defect condition. once the secondary frame synchronizer block clears the los defect, then the transmit sonet poh processor block will automatically terminate its transmission of the pdi-p indicator by setting the c2 byte (within each ?down- stream? sts-1 spe) to the value ?0x04?. 0 ? disables this ?transmit pdi-p (down-stream) upon los feature. 1 ? enables this ?transmit pdi-p (down-stream) upon los feature. note: the user should only invoke this feature if the secondary frame synchronizer block has been configured to operate in the ds3/e3 ingress path. 4 transmit ais (down-stream) upon los r/w transmit the ds3/e3 ais indicator (down-stream) upon declaration of the los defect condition: this read/write bit-field permits the user to configure the ds3/e3 framer block to do the following, if the los defect is declared. if the secondary frame synchronizer block declares the los defect (within its receive path) then it will automatically force the corresponding ?ds3/e3 frame generator? block to generate and transmit the ds3/e3 ais indicator. in this case, the ds3/e3 frame generator block will transmit the ais indicator (in the down-stream path) for the duration t hat the secondary frame synchronizer block declares the los defect condition. once the secondar y frame s y nchronizer block clears the los defect condition,
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 555 then the ds3/e3 frame generator block will automatically terminate its transmission of the ds3/e3 ais indicator, and will permit normal ds3/e3 traffic to pass through the ds3/e3 framer block (towards the down-stream signal path). 0 ? disables the ?transmit ais (down-stream) upon los feature. 1 ? enables the ?transmit ais (down-stream) upon los feature. 3 transmit pdi- p (down- stream) upon lof r/w transmit pdi-p indicator (down-str eam) upon declaration of the ds3/e3 lof defect condition: this read/write bit-field permits the user to configure the ds3/e3 framer block (via the secondary frame synchronizer block) and the corresponding transmit sonet poh processor block to automatically transmit the pdi-p (path ? payload defect indicator) anytim e the lof defect is declared within the ds3 ingress path. more specifically, if this configurati on is implemented then the following events will occur. if the secondary frame synchronizer block is operating in the ?ds3/e3 ingress? path (e.g., if the ds3/e3 framer block ha s been configured to operate in frame generator/frame synchronizer configuration # 0xc0), and if it were to declare the lof defect condition (within the ingr ess path), then the corresponding transmit sonet poh processor block will automatically transmit the pdi-p indicator (via its sts-1 signal, within the outbound composite sts-3 signal) by setting the c2 byte (within each ?down-stream? sts-1 spe) to the value ?0xfc?. the transmit sonet poh processor block will continue to transmit the pdi-p indicator for the duration that the seco ndary frame synchronizer block declares the lof defect condition. once the secondary frame synchronizer block clears the lof defect, then the transmit sonet poh processor block will automatically terminate its transmission of the pdi-p indicator by setting the c2 byte (within each ?down- stream? sts-1 spe) to the value ?0x04?. 0 ? disables this ?transmit pdi-p (down-stream) upon lof feature. 1 ? enables this ?transmit pdi-p (down-stream) upon lof feature. note: the user should only invoke th is feature if t he secondary frame synchronizer block has been configured to operate in the ds3/e3 ingress path. 2 transmit ais (down-stream) upon lof r/w transmit the ds3/e3 ais indicator (down-stream) upon declaration of the lof defect condition: this read/write bit-field permits the user to configure the ds3/e3 framer block to do the following, if the lof defect is declared. if the secondary frame synchronizer block declares the lof defect (within its receive path) then it will automatically force the corresponding ?ds3/e3 frame generator? block to generate and transmit the ds3/e3 ais indicator. in this case, the ds3/e3 frame generator block will transmit the ais indicator (in the down-stream path) for the duration t hat the secondary frame synchronizer block declares the lof defect condition. once the secondary frame synchronizer block clears the lof defect condition, then the ds3/e3 frame generator block will automatically terminate its transmission of the ds3/e3 ais indicator, and will permit normal ds3/e3 traffic to pass through the ds3/e3 framer block (towards the down-stream signal path). 0 ? disables the ?transmit ais (down-stream) upon lof feature. 1 ? enables the ?transmit ais (down-stream) upon lof feature. 1 transmit pdi- p (down- stream ) u p on r/w transmit pdi-p indicator (down-str eam) upon declaration of the ds3/e3 ais defect condition:
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 556 ais this read/write bit-field permits th e user to configure the ds3/e3 framer block (via the secondary frame synchronizer block) and the corresponding transmit sonet poh processor block to automatically transmit the pdi-p (path ? payload defect indicator) anytime the ais defect is declared within the ds3 ingress path. more specifically, if this configurati on is implemented then the following events will occur. if the secondary frame synchronizer block is operating in the ?ds3/e3 ingress? path (e.g., if the ds3/e3 framer block ha s been configured to operate in frame generator/frame synchronizer configuration # 0xc0), and if it were to declare the ais defect condition (within the ingr ess path), then the corresponding transmit sonet poh processor block will automatically transmit the pdi-p indicator (via its sts-1 signal, within the outbound composite sts-3 signal) by setting the c2 byte (within each ?down-stream? sts-1 spe) to the value ?0xfc?. the transmit sonet poh processor block will continue to transmit the pdi-p indicator for the duration that the seco ndary frame synchronizer block declares the ais defect condition. once the secondary frame synchronizer block clears the ais defect, then the transmit sonet poh processor block will automatically terminate its transmission of the pdi-p indicator by setting the c2 byte (within each ?down- stream? sts-1 spe) to the value ?0x04?. 0 ? disables this ?transmit pdi-p (down-stream) upon ais feature. 1 ? enables this ?transmit pdi-p (down-stream) upon ais feature. note: the user should only invoke th is feature if t he secondary frame synchronizer block has been configured to operate in the ds3/e3 ingress path. 0 transmit ais (down-stream) upon ais r/w transmit the ds3/e3 ais indicator (down-stream) upon declaration of the ais defect condition: this read/write bit-field permits the user to configure the ds3/e3 framer block to do the following, if the ais defect is declared. if the secondary frame synchronizer bl ock declares the ais defect (within its receive path) then it will automatically force the corresponding ?ds3/e3 frame generator? block to generate and transmit the ds3/e3 ais indicator. in this case, the ds3/e3 frame generator block will transmit the ais indicator (in the down-stream path) for the duration t hat the secondary frame synchronizer block declares the ais defect condition. once the secondary frame synchronizer bl ock clears the ais defect condition, then the ds3/e3 frame generator block will automatically terminate its transmission of the ds3/e3 ais indicator, and will permit normal ds3/e3 traffic to pass through the ds3/e3 framer block (towards the down-stream signal path). 0 ? disables the ?transmit ais (down-stream) upon ais feature. 1 ? enables the ?transmit ais (down-stream) upon ais feature.
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 557 1.10.9 p erformance m onitor r egisters table 389: pmon excessive zero count registers ? msb (address location= 0xn34e, where n ranges from 0x02 to 0x04) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 pmon_exz_count_up per_byte[7:0] rur rur rur rur rur rur rur rur 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 - 0 pmon_exz_count_u pper_byte[7:0] rur performance monitor ? excessive zero event count ? upper byte: these reset-upon-read bits, along with that within the ?pmon excessive zero count register ? lsb? combine to reflect the cumulative number of instances that a string of three or more consecutive zeros (for ds3 applications) or four or more consecutive zeros (for e3 applications) has been detected by the ?primary frame synchronizer? block since the last read of this register. this register contains the mo st significant byte of this 16-bit expression. note: this register only applies to the primary frame synchronizer block. the secondary frame synchronizer block does not have the ability to detect and flag exz events.
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 558 table 390: pmon excessive zero count registers ? lsb (address location= 0xn34f, where n ranges from 0x02 to 0x04) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 pmon_exz_count_low er_byte[7:0] rur rur rur rur rur rur rur rur 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 - 0 pmon_exz_count_u pper_byte[7:0] rur performance monitor ? excessive zero event count ? lower byte: these reset-upon-read bits, along with that within the ?pmon excessive zero count register ? msb? combine to reflect the cumulative number of instances that a string of three or more consecutive zeros (for ds3 applications) or four or more consecutive zeros (for e3 applications) has been detected by the ?primary frame synchronizer? block since the last read of this register. this register contains the least significant byte of this 16-bit expression. note: this register only applies to the primary frame synchronizer block. the secondary frame synchronizer block does not have the ability to detect and flag exz events.
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 559 table 391: pmon line code violation count regi sters ? msb (address location= 0xn350, where n ranges from 0x02 to 0x04) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 pmon_lcv_count_up per_byte[7:0] rur rur rur rur rur rur rur rur 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 ? 0 pmon lcv count upper byte[7:0] rur performance monitor- line code violation count register ? upper byte: these reset-upon-read bits alon g with that within the ?pmon line code violation count ? lsb? combine to reflect the cumulative number of line code violations that have been detected by the primary frame synchronizer block, since the last read of this register. this register contains the most significant byte of this 16-bit expression. note: this register only applies to the primary frame synchronizer block. the secondary frame synchronizer block does not have the ability to detect and flag lcv events. table 392: pmon line code violation count regi sters ? lsb (address location= 0xn351, where n ranges from 0x02 to 0x04) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 pmon_lcv_count_lower_byte[7:0] rur rur rur rur rur rur rur rur 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 ? 0 pmon lcv count lower byte[7:0] rur performance monitor- line code violation count register ? lower byte: these reset-upon-read bits alon g with that within the ?pmon line code violation count ? msb? combine to reflect the cumulative number of line code violations that have been detected by the primary frame synchronizer block, since the last read of this register. this register contains the least significant byte of this 16-bit expression. note: this register only applies to the primary frame synchronizer block. the secondary frame synchronizer block does not have the ability to detect and flag exz events.
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 560 table 393: pmon framing bit/byte error count re gister ? msb (address location= 0xn352, where n ranges from 0x02 to 0x04) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 pmon_framing_bit/byte_error_count_upper_byte[7:0] rur rur rur rur rur rur rur rur 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 - 0 pmon_framing bit/byte error_count_upper byte[7:0] rur performance monitor ? framing bit/byte error count ? upper byte: these reset-upon-read bits, along with that within the ?pmon framing bit/byte error count register ? lsb? combine to reflect the cumulative number of framing bit (or byte) errors that have been detected by the primary frame synchroniz er block, since the last read of this register. this register contains the most significant byte of this 16-bit expression. note: for ds3 applications, this register will increment for each f or m bit error detected. for e3, itu-t g.751 applications, this register will increment for each fas error detected. for e3, itu-t g.832 applications, this register will increment for each fa1 or fa2 byte error detected. these register bits are not active if the primary frame synchronizer block has been by-passed.
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 561 table 394: pmon framing bit/byte error count re gister ? lsb (address location= 0xn353, where n ranges from 0x02 to 0x04) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 pmon_framing_bit/byte_err or_count_lower _byte[7:0] rur rur rur rur rur rur rur rur 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 - 0 pmon_framing bit/byte error_count_lower byte[7:0] rur performance monitor ? framing bit/byte error count ? lower byte: these reset-upon-read bits, along with that within the ?pmon framing bit/byte error count regist er ? msb? combine to reflect the cumulative number of frami ng bit (or byte) errors that have been detected by the primary frame synchronizer block, since the last read of this register. this register contains the least significant byte of this 16-bit expression. note: for ds3 applications, this register will increment for each f or m bit error detected. for e3, itu-t g.751 applications, this register will increment for each fas error detected. for e3, itu-t g.832 applications, this register will increment for each fa1 or fa2 byte error detected. these register bits are not active if the primary frame synchronizer block has been by-passed.
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 562 table 395: pmon parity/p-bit error count regi ster ? msb (address location= 0xn354, where n ranges from 0x02 to 0x04) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 pmon_parity_error_count_upper_byte[7:0] rur rur rur rur rur rur rur rur 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 - 0 pmon_p-bit/parity bit error_count_upper byte[7:0] rur performance monitor ? p bit/parity bit error count ? upper byte: these reset-upon-read bits, along with that within the ?pmon p- bit/parity bit error count register ? lsb? combine to reflect the cumulative number of p bit errors (for ds3 applications) or bip-8/bip- 4 errors (for e3 applications) that have been detected by the primary frame synchronizer block, since the last read of this register. this register contains the most significant byte of this 16-bit expression. note: these register bits are not active if the primary frame synchronizer block has been by-passed. table 396: pmon parity/p-bit error count regist er ? lsb (address location= 0xn355, where n ranges from 0x02 to 0x04) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 pmon_parity_error_count_lower_byte[7:0] rur rur rur rur rur rur rur rur 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 - 0 pmon_p-bit/parity bit error_count_lower byte[7:0] rur performance monitor ? p bit/parity bit error count ? lower byte: these reset-upon-read bits, along with that within the ?pmon p- bit/parity bit error count register ? msb? combine to reflect the cumulative number of p bit errors (for ds3 applications) or bip-8/bip- 4 errors (for e3 applications) that have been detected by the primary frame synchronizer block, since the last read of this register. this register contains the least significant byte of this 16-bit expression. note: these register bits are not active if the primary frame synchronizer block has been by-passed.
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 563 table 397: pmon febe event count register ? msb (address location= 0xn356, where n ranges from 0x02 to 0x04) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 pmon_febe_event_count _upper_byte[7:0] rur rur rur rur rur rur rur rur 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 - 0 pmon_febe event_count_upper byte[7:0] rur performance monitor ? febe event count ? upper byte: these reset-upon-read bits, alon g with that within the ?pmon febe event count register ? lsb? combine to reflect the cumulative number of ?erred? febe events t hat have been detected by the primary frame synchronizer block, since the last read of this register. this register contains the most significant byte of this 16-bit expression. note: these register bits are not active if the primary frame synchronizer block has been by-passed. table 398: pmon febe event count register ? lsb (address location= 0xn357, where n ranges from 0x02 to 0x04) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 pmon_febe_event_count _lower_byte[7:0] rur rur rur rur rur rur rur rur 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 - 0 pmon_febe event_count_lower byte[7:0] rur performance monitor ? febe event count ? lower byte: these reset-upon-read bits, alon g with that within the ?pmon febe event count register ? m sb? combine to reflect the cumulative number of ?erred? f ebe events that have been detected by the primary frame synchronizer block, since the last read of this register. this register contains th e least significant byte of this 16- bit expression. note: these register bits are not active if the primary frame synchronizer block has been by-passed.
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 564 table 399: pmon cp-bit error co unt register ? msb (address location= 0xn358, where n ranges from 0x02 to 0x04) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 pmon_cp-bit_error_co unt_upper_ byte[7:0] rur rur rur rur rur rur rur rur 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 - 0 pmon_cp-bit error_count_upper byte[7:0] rur performance monitor ? cp bit error count ? upper byte: these reset-upon-read bits, along with that within the ?pmon cp-bit error count register ? lsb? combine to reflect the cumulative number of cp bit errors that have been detected by the primary frame synchronizer block, since the last read of this register. this register contains the mo st significant byte of this 16-bit expression. note: these register bits are not active if the primary frame synchronizer block has been by- passed, or if the ds3/e3 framer block has not been configured to operate in the ds3 c- bit parity framing format. table 400: pmon cp-bit error count register ? lsb (address location= 0xn359, where n ranges from 0x02 to 0x04) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 pmon_cp-bit_error_co unt_lower_byte[7:0] rur rur rur rur rur rur rur rur 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 - 0 pmon_cp-bit error_count_lower byte[7:0] rur performance monitor ? cp bit error count ? lower byte: these reset-upon-read bits, along with that within the ?pmon cp-bit error count register ? msb? combine to reflect the cumulative number of cp bit errors that have been detected by the primary frame synchronizer block, since the last read of this register. this register contains the le ast significant byte of this 16-bit expression. note: these register bits are not active if the primary frame synchronizer block has been by- passed, or if the ds3/e3 framer block has not been configured to operate in the ds3 c- bit parity framing format.
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 565 table 401: prbs error count regi ster ? msb (address location= 0xn368, where n ranges from 0x02 to 0x04) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 prbs_error_count_upper_byte[7:0] rur rur rur rur rur rur rur rur 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 - 0 prbs error_count_upper byte[7:0] rur prbs error count ? upper byte: these reset-upon-read bits, along with that within the ?prbs error count register ? lsb? combine to reflect the cumulative number of prbs bit errors that have been detected by the primary frame synchronizer block, since the last read of this register. this register contains the most significant byte of this 16-bit expression. note: these register bits are not active if the primary frame synchronizer block has been by- passed, and if the prbs receiver has not been enabled. table 402: prbs error count register ? lsb (add ress location= 0xn369, where n ranges from 0x02 to 0x04) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 prbs_error_count_lower_byte[7:0] rur rur rur rur rur rur rur rur 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 - 0 prbs error_count_lower byte[7:0] rur prbs error count ? lower byte: these reset-upon-read bits, along with that within the ?prbs error count register ? msb? combine to reflect the cumulative number of prbs bit errors that have been detected by the primary frame synchronizer block, since the last read of this register. this register contains the least significant byte of this 16-bit expression. note: these register bits are not active if the primary frame synchronizer block has been by- passed, and if the prbs receiver has not been enabled.
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 566 table 403: pmon holding register (address location= 0xn3, 0x6c; address location= 0xn36c, where n ranges from 0x02 to 0x04) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 pmon_hold_value[7:0] r/o r/o r/o r/o r/o r/o r/o r/o 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 ? 0 pmon holding value r/o pmon holding value : these read-only bit-fields were specifically allocated to support read operations to the pmon (performance monitor) registers, within the ds3/e3 framer blocks. since the pmon register (within the ds3/e3 framer block) are 16- bit registers. therefore, given that the bi-directional data bus of the XRT94L33 is only 8-bits wide, it will require two read operations in order to read out the entire 16 bi t content of these registers. the other thing to note is that the pmon registers (within the ds3/e3 framer blocks) are reset -upon-read type registers. as consequence, the entire 16-bit cont ents of a given pmon register will be cleared to ?0x0000? immediately after the user has executed the first (of two) read operations to this register. in order to avoid losing the contents of the other by te, the contents of the ?un-read? byte is automatically loaded into this register. hence, once the user reads a regist er, from a given pmon register, he/she is suppose to obtain the cont ents of the other byte, by reading the contents of this register.
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 567 table 404: one second error status register (address location= 0xn36d, where n ranges from 0x02 to 0x04) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 unused errored second severe errored second r/o r/o r/o r/o r/o r/o r/o r/o 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 ? 2 unused r/o 1 errored second r/o errored second indicator: this read-only bit-field indicates whether or not the ds3/e3 framer block has declared the last one-second accumulation period as a ?errored second?. the ds3/e3 framer block will declare an ?errored second? if the primary frame synchronizer block detects any of the following events. for ds3 applications ? p-bit errors ? cp bit errors ? framing bit (f or m bit) errors for e3 applications ? bip-4/bip-8 errors ? fas or framing byte (fa1, fa2) errors 0 ? indicates that the ds3/e3 framer block has not declared the last one- second accumulation period as being an errored second. 1 ? indicates that the ds3/e3 fram er block has declared the last one- second accumulation period as being an errored second. note: this bit-field is only active if the primary frame synchronizer block is enabled. 0 severely errored second r/o severely errored second indicator: this read-only bit-field indicates whether or not the ds3/e3 framer block has declared the last one second accumulation period as being a ?severely errored second?. the ds3/e3 framer block will declare a given second as being a ?severely errored? second if it determines that the ber (bit error rate) during this ?one-second accumulation? period is greater than 10 -3 errors/second. 0 ? indicates that the ds 3/e3 framer block has not declared the last one- second accumulation period as being a ?severely-errored? second. 1 ? indicates that the ds3/e3 fram er block has declared the last one- second accumulation period as being a ?severely-errored? second. note: this bit-field is only active if the primary frame synchronizer block is enabled.
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 568 table 405: one second ? lcv count accumulator re gister ? msb (address location= 0xn36e, where n ranges from 0x02 to 0x04) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 one_second_lcv_count_accum_msb[7:0] r/o r/o r/o r/o r/o r/o r/o r/o 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 - 0 one_second_lcv_count accum_lsb[7:0] r/o one second lcv count accumulator register ? msb: these read-only bits, along with that within the ?one second lcv count accumulator register ? msb? combine to reflect the cumulative number of ?line code violations? that have been detected by the primary frame synchronizer block, in the last ?one second? accumu lation period. this register contains the most significant by te of this 16-bit expression. note: this bit-field is only valid if the primary frame synchronizer block has been configured to operate in the ingress path. table 406: one second ? lcv count accumulator register ? lsb (address location= 0xn36f, where n ranges from 0x02 to 0x04) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 one_second_lcv_count_accum_lsb[7:0] r/o r/o r/o r/o r/o r/o r/o r/o 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 - 0 one_second_lcv_count accum_lsb[7:0] r/o one second lcv count accumulator register ? lsb: these read-only bits, along with that within the ?one second lcv count accumulator register ? lsb? combine to reflect the cumulative number of ?line code violations? that have been detected by the primary frame synchronizer block, in the last ?one second? accumu lation period. this register contains the least significant byte of this 16-bit expression. note: this bit-field is only vaiid if the primary frame synchronizer block has been configured to operate in the ingress path
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 569 table 407: one second ? parity error accumulator register ? msb (address location= 0xn370, where n ranges from 0x02 to 0x04) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 one_second_parity_error_accum_msb[7:0] r/o r/o r/o r/o r/o r/o r/o r/o 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 - 0 one_second_parity error accum_msb[7:0] r/o one second parity error accumulator register ? msb: these read-only bits, along with that within the ?one second parity error accumulator register ? lsb? combine to reflect the cumulative number of ?parity errors? that have been detected by the primary frame synchronizer bl ock, in the last ?one second? accumulation period. this register contains the most significant byte of this 16-bit expression. note: for ds3 applications, the register will reflect the number of p-bit errors, detected within the last ?one second? accumulation period. for e3, itu-t g.751 applications, this register will reflect the number of bip-4 errors, detected within the last ?one second? accumulation period. for e3, itu-t g.832 applications, this register will reflect the number of bip-8 (b1 byte) errors detected within the last ?one second? accumu lation period.
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 570 table 408: one second ? parity error accumulator register ? lsb (address location= 0xn371, where n ranges from 0x02 to 0x04) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 one_second_parity_error_accum_lsb[7:0] r/o r/o r/o r/o r/o r/o r/o r/o 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 - 0 one_second_parity error accum_lsb[7:0] r/o one second parity error accumulator register ? lsb: these read-only bits, along with that within the ?one second parity error accumulator register ? msb? combine to reflect the cumulative number of ?parity errors? that have been detected by the primary frame synchronizer bl ock, in the last ?one second? accumulation period. this register contains the least significant byte of this 16-bit expression. note: for ds3 applications, the register will reflect the number of p-bit errors, detected within the last ?one second? accumulation period. for e3, itu-t g.751 applications, this register will reflect the number of bip-4 errors, detected within the last ?one second? accumulation period. for e3, itu-t g.832 applications, this register will reflect the number of bip-8 (b1 byte) errors detected within the last ?one second? accumu lation period.
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 571 table 409: one second ? cp bit error accumulator register ? msb (address location= 0xn372, where n ranges from 0x02 to 0x04) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 one_second_cp_bit_error_accum_msb[7:0] r/o r/o r/o r/o r/o r/o r/o r/o 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 - 0 one_second_cp bit error accum_msb[7:0] r/o one second cp bit error accumulator register ? msb: these read-only bits, along with that within the ?one second cp-bit error accumulator register ? lsb? combine to reflect the cumulative number of ?cp bit errors? that have been detected by the frame synchronizer block, in the last ?one second? accumulation period. this register contains the most significant byte of this 16-bit expression. note: this register is inactive if the primary frame synchronizer block is ?by-passed? or if the ds3/e3 framer block has not been configured to operate in the ds3, c-bit parity framing format. table 410: one second ? cp bit error accumulator register ? lsb (address location= 0xn373, where n ranges from 0x02 to 0x04) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 one_second_cp_bit_err or_accum_lsb[7:0] r/o r/o r/o r/o r/o r/o r/o r/o 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 - 0 one_second_cp bit error accum_lsb[7:0] r/o one second cp bit error accumulator register ? lsb: these read-only bits, along with that within the ?one second cp-bit error accumulator register ? msb? combine to reflect the cumulative number of ?cp bit errors? that have been detected by the frame synchronizer block, in the last ?one second? accumulation period. this register contains the least significant byte of this 16-bit expression. note: this register is inactive if the primary frame synchronizer block is ?by-passed? or if the ds3/e3 framer block has not been configured to operate in the ds3, c-bit parity framing format.
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 572 1.10.10 g eneral p urpose i/o p in c ontrol r egisters table 411: line interface drive register (addr ess location= 0xn380, where n ranges from 0x02 to 0x04) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 internal remote loop-back transmit frame pulse disable unused r/w r/o r/o r/o r/o r/o r/o r/o 0 0 0 0 1 0 0 0 b it n umber n ame t ype d escription 7 internal remote loop- back r/w internal remote loop-back mode: this read/write bit-field permits the user to configure the ds3/e3 framer block to operate in the ?remote loop-back? mode. if the user enables this feature, then the receive input of the primary frame synchronizer block will automatically be routed to the transmit output of t he frame generator block. 0 ? disables the remote loop-back mode. 1 ? enables the remote loop-back mode. note: this feature is only availabl e if both the ds3/e3 frame generator and the primary frame synchronizer blocks are enabled. 6 transmit frame pulse disable r/w transmit frame pulse disable: this read/write bit-field permits the user to either enable or disable the ?frame pulse? that is output via the ?txds3neg_n? output pin (whenever the xrt94l31 device has been configured to exchange data, with the off-chip ds3/e3/sts-1 liu) in the single- rail manner. 0 ? configures the xrt94l31 device to output a ?frame pulse? via the corresponding ?txds3neg_n? output pin. 1 ? configures the xrt94l31 devic e to not output a ?frame pulse via the ?txds3neg_n? output pin. in this case, the chip will pull this output pin ?low?. note: this bit-field is ignored if the channel is configured to exchange data (with the off-chip ds3/e3/sts-1 liu ic) via the dual-rail manner. 5 - 0 unused r/o
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 573 table 412: payload hdlc control register (address location= 0xn382, where n ranges from 0x02 to 0x04) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 framer bypass hdlc on crc32 unused hdlc loopback unused r/w r/w r/w r/o r/w r/o r/o r/o 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 framer bypass r/w framer bypass: this read/write bit-field permits the user to bypass ds3/e3 framer. 0 ? ds3/e3 framer is not bypassed. 1 ? ds3/e3 framer is bypassed. 6 hdlc on r/w hdlc on: this read/write bit-field permits the user to either disable or enable the payload hdlc processor. when payload hdlc processo r is enabled, the payload portion of the ds3 data stream will come from this hdlc formatter which provides an external byte-wide data (txhdlcdata, from pin sts1txa_d) and a byte clock (txhdlcclk, from pin stuffcntl) 0 ? payload hdlc processor is disabled 1 ? payload hdlc processor is enabled 5 crc32 r/w crc32: this read/write bit-field permits the user to select the length of fcs to be 16-bit or 32-bit. if 16-bit fcs is selected, the fcs is calculated with polynomial: x 16 + x 12 + x 5 + 1. if 32-bit fcs is selected, it is then calculated with polynomial: x 32 + x 26 + x 23 + x 22 + x 16 + x 12 + x 11 + x 10 + x 8 + x 7 + x 5 + x 4 + x 2 + x + 1 0 ? crc16 is used 1 ? crc32 is used 4 unused r/o 3 hdlc loopback r/w hdlc loopback: this read/write bit-field permits the user to either enable or disable the hdlc loopback. 0 ? txhdlc loopback is disabled. 1 ? txhdlc loopback is enabled. transmit hdlc processor will loopback to the receive side. 2-0 unused r/o
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 574 1.10.11 lapd c ontroller b yte c ount r egisters table 413: txlapd byte count register (address location= 0xn383, where n ranges from 0x02 to 0x04) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 txlapd_message_size[7:0] r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 ? 0 txlapd_message_size[7:0] r/w transmit lapd message size: these read/write bit-fields permit the user to specify the size of the information payload (in terms of bytes) within the very next outbound lapd/pmdl message, whenever bit 7 (txlapd any) within the ?transmit tx lapd configuration? register has been set to ?1?. table 414: rxlapd byte count register (address location= 0xn384, where n ranges from 0x02 to 0x04) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 rxlapd_message_size[7:0] r/o r/o r/o r/o r/o r/o r/o r/o 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 ? 0 rxlapd_message_size[7:0] r/o receive lapd message size: these read-only bit-fields indicate the size of the most recently received lapd/pmdl message, whenever bit 7 (rxlapd any) within the ?rx lapd control? register; has been set to ?1?. the contents of these register bits, reflects the received lapd message size, in terms of bytes.
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 575 table 415: receive ds3/e3 configuration register ? secondary frame synchronizer (address location= 0xn3f0, where n ranges from 0x02 to 0x04) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 unused primary frame - clock output invert primary frame ? transmit ais enable secondary frame ? single-rail input primary frame - dual- rail output primary frame ? idle pattern insert r/o r/o r/o r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 - 5 unused r/o 4 primary frame ? clock output invert r/w primary frame synchronizer ? clock output invert: the exact function of this bit-fiel d depends upon whether the primary frame synchronizer block has been conf igured to operate in ingress or egress direction, as described below. if the primary frame synchronizer block has been configured to operate in the egress direction this read/write bit-field permits the user to configure the primary frame synchronizer block to update the ?t xds3pos_n/txds3neg_n? output pins upon either the rising or falling edge of ?txds3lineclk_n. 0 ? ?txds3pos_n/txds3neg_n is updated upon the rising edge of ?txds3lineclk_n?. the user should insure that the liu ic will sample the ?txds3pos_n/txds3neg_n? input pins upon the falling edge of ?txds3lincclk_n? 1 ? ?txds3pos_n/txds3neg_n? is updated upon the falling edge of ?txds3lineclk_n?. the user should insu re that the liu ic will sample the ?txds3pos_n/txds3neg_n? input pins upon the rising edge of ?txds3lineclk_n?. if the primary frame synchronizer block has been configured to operate in the ingress direction: this read/write bit-field permis the user to configure the primary frame synchronizer block to update the ?ingr ess direction? ds3/e3 data-stream (which is being routed to the ds3/e3 mapper block) upon either the rising or falling edge of the recovered li ne (ingress direction) ds3/e3 clock signal (from the liu ic). 0 ? ?ingress direction ds3/e3 data? is updated upon the rising edge of the ?recovered? clock signal. 1 ? ?ingress direction ds3/e3 data? is updated upon the falling edge of the ?recovered? clock signal. note: if the primary frame synchronizer block is configured to operate in the ingress direction, then we recommend that the user set this register bit to ?1?. this setting will insure that the ds3/e3 mapper block will be able to sample the ingress direction ds3/e3 data-stream with proper set-up and hold times. 3 primary frame ? transmit ais enable r/w primary frame synchronizer block ? transmit ais enable: this read/write bit-field permits the user to configure the ais/ds3 idle pattern generator, within the primary frame synchronizer block to transmit the ds3/e3 ais indicator to the remote terminal e q ui p ment (p er software
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 576 command). if the user commands the ?ais/ds3 id le signal pattern generator?, to generate and transmit the ds3/e3 ais pa ttern, then the data, that is output via the primary frame synchronizer bl ock, will be overwritten with this ds3/e3 ais pattern. 0 ?disables the ?ais/ds3 idle signal pattern generator? within the primary frame synchronizer block. in this setting, normal traffic will pass through the primary frame synchronizer block 1 ? configures the ?ais/ds3 idle signal pattern generator? (within the primary frame synchronizer block) to generate and transmit the ds3/e3 ais indicator. 2 secondary frame ? single-rail input r/w secondary frame synchronizer block ?single-rail/dual rail input select: this read/write bit-field permits t he user to configure the secondary frame synchronizer block to accept dat a via either the ?single-rail? or ?dual-rail? manner. 0 ? configures the secondary frame synchronizer block to accept data via the ?dual-rail? mode. 1 ? configures the secondary frame synchronizer block to accept data via the ?single-rail? mode. note: this register bit is only valid if the secondary frame synchronizer block has been configured to oper ate in the ?ingress? direction. 1 primary frame ? dual-rail output r/w primary frame synchronizer ? dual-rail output: this read/write bit-field permits t he user configure the primary frame synchronizer block to output data (to the liu ic) in either the single-rail or dual-rail manner. 0 ? configures the primary frame sync hronizer block to output data (to the liu ic) in a single-rail manner. 1 ? configures the primary frame sync hronizer block to output data (to the liu ic) in a dual-rail manner. note: this register bit is only valid if the primary frame synchronizer block has been configured to oper ate in the ?egress? direction. 0 primary frame ? idle pattern insert r/o primary frame synchronizer block ? ds3 idle pattern insert: this read/write bit-field permits the user to configure the ais/ds3 idle signal pattern generator, within the primary frame synchronizer block to transmit the ds3 idle signal to the remote terminal equipment (per software command). if the user commands the ?ais/ds3 idle signal pattern generator? to generate and transmit the ds3 idle signal pattern, then the data, that is output via the primary frame synchronizer block, will be overwritten with the ds3 idle signal pattern. 0 ?disables the ?ais/ds3 idle signal pattern generator? within the primary frame synchronizer block. in this setting, normal traffic will pass through the primary frame synchronizer block 1 ? configures the ?ais/ds3 idle signal pattern generator? (within the primary frame synchronizer block) to generate and transmit the ds3 idle signal.
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 577 table 416: receive ds3/e3 status register ? secondary frame synchronizer (address location= 0xn3f1, where n ranges from 0x02 to 0x04) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 secondary frame synchronizer - ds3/e3 ais defect declared secondary frame synchronizer ? ds3/e3 los defect declared secondary frame synchronizer ? ds3 idle pattern detected secondary frame synchronizer ? lof/oof defect declared unused r/o r/o r/o r/o r/o r/o r/o r/o 0 0 0 1 0 0 0 0 b it n umber n ame t ype d escription 7 secondary frame synchronizer ? ds3/e3 ais defect declared r/o ds3/e3 ais defect declared ? secondary frame synchronizer block: this read-ony bit-field indicates whether or not the secondary frame synchronizer block is currently decla ring the ais defect condition in its incoming path, as described below. 0 ? indicates that the secondary frame synchronizer block is not declaring the ds3/e3 ais defect condition. 1 ? indicates that the secondary fram e synchronizer block is currently declaring the ais defect condition. 6 secondary frame synchronizer ? los defect declared r/o ds3/e3 los defect declared ? secondary frame synchronizer block: this read/write bit-field indicates whether or not the secondary frame synchronizer block is currently decla ring the los defect condition as described below. 0 ? indicates that the secondary frame synchronizer block is not declaring the los defect condition in its incoming path. 1 ? indicates that the secondary fram e synchronizer block is currently declaring the los defect its incoming path. 5 secondary frame synchronizer ? ds3 idle pattern detected r/o ds3 idle signal pattern detected ? secondary frame synchronizer block: this read-ony bit-field indicates whether or not the secondary frame synchronizer block is currently detecting the ds3 idle pattern, within its incoming receive path. 0 ? indicates that the secondary frame synchronizer block is not detecting the ds3 idle pattern, in its incoming path. 1 ? indicates that the secondary fram e synchronizer block is currently detecting the ds3 idle pattern in its incoming path. note: this bit-field is only valid if the ds3/e3 framer block has been configured to operat e in the ds3 mode. 4 secondary frame synchronizer ? oof defect declared r/o oof/lof defect declared ? secondary frame synchronizer block: this read-only bit-field indicates whether or not the secondary frame synchronizer block is currently declaring the oof/lof defect condition, as described below. 0 ? indicates that the secondary frame synchronizer block is not declaring the oof/lof defect condition. 1 ? indicates that the secondary fram e synchronizer block is currently declaring the oof/lof defect condition.
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 578 3 ? 0 unused r/o
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 579 table 417: receive ds3/e3 interrupt enable register ? secondary frame synchronizer block (address location= 0xn3f8, where n ranges from 0x02 to 0x04) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 unused change of los defect condition interrupt enable change of ais defect condition interrupt enable change of ds3 idle condition interrupt enable unused change of oof defect condition interrupt enable unused r/o r/w r/w r/w r/o r/o r/w r/o 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 unused r/o 6 change of los defect condition interrupt enable r/w change of los defect condition interrupt enable ? secondary frame synchronizer block: this read/write bit-field permits the user to either enable or disable the ?change of los (loss of signal) defect condition? interrupt for the secondary frame synchronizer block. if the user enables this interrupt, then the secondary frame synchronizer block will generate an interrupt in response to either of the following conditions. ? whenever the secondary frame synchronizer block declares the los defect condition. ? whenever the secondary frame synchronizer block clears the los defect condition. 0 ? disables the ?change of los defect condition? interrupt. 1 ? enables the ?change of los defect condition? interrupt. note: this configuration setting only applies to the secondary frame synchronizer block. this configur ation setting does not apply to the primary frame synchronizer block. 5 change of ais defect condition interrupt enable r/w change of ais defect condition interrupt enable ? secondary frame synchronizer block: this read/write bit-field permits the user to either enable or disable the ?change of ais defect condit ion? interrupt for the secondary frame synchronizer block. if the user enables this interrupt, then the secondary frame synchronizer block will generate an interrupt in response to either of the following conditions. ? whenever the secondary frame synchronizer block declares the ais defect condition. ? whenever the secondary frame synchronizer block clears the ais defect condition. 0 ? disables the ?change of ais defect condition? interrupt. 1 ? enables the ?change of ais defect condition? interrupt. 4 change in ds3 idle condition interrupt enable r/w change of ds3 idle condition interrupt enable ? secondary frame synchronizer block: this read/write bit-field p ermits the user to either enable or disable
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 580 the ?change of ds3 idle condition? interrupt for the secondary frame synchronizer block. if the user enables this interrupt, then the secondary frame synchronizer block will generate an interrupt in response to either of the following conditions. ? whenever the secondary frame synchronizer block detects the ds3 idle pattern within its receive path. ? whenever the secondary frame synchronizer block ceases to detect the ds3 idle pattern wi thin its receive path. 0 ? disables the ?change of ds3 idle condition? interrupt. 1 ? enables the ?change of ds3 idle condition? interrupt. note: this bit-field is only active if the ds3/e3 framer block has been configured to operate in the ds3 mode. 3 - 2 unused r/o 1 change of oof defect condition interrupt enable r/w change of oof defect condition interrupt enable ? secondary frame synchronizer block: this read/write bit-field permits the user to either enable or disable the ?change of oof defect condition? interrupt for the secondary frame synchronizer block. if the user enables this interrupt, then the secondary frame synchronizer block will generate an interrupt in response to either of the following conditions. ? whenever the secondary frame synchronizer block declares the oof defect condition. ? whenever the secondary frame synchronizer block clears the oof defect condition. 0 ? disables the ?change of oof defect condition? interrupt. 1 ? enables the ?change of oof defect condition? interrupt. 0 unused r/o
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 581 table 418: receive ds3/e3 interrupt status regi ster ? secondary frame synchronizer block (address location= 0xn3f9, where n ranges from 0x02 to 0x04) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 unused change of los defect condition interrupt status change of ais defect condition interrupt status change of ds3 idle condition interrupt status unused change of oof defect condition interrupt status unused r/o rur rur rur r/o r/o rur r/o 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 unused r/o 6 change of los defect condition interrupt status rur change of los defect condition interrupt status ? secondary frame synchronizer block: this reset-upon-read bit-field indicates whether or not the ?change of los defect condition? interrupt (per the secondary frame synchronizer block) has occurred since the last read of this register. 0 ? indicates that the ?change of los defect condition? interrupt (per the secondary frame synchronizer block) has not occurred since the last read of this register. 1 ? indicates that the ?change of los defect condition? interrupt (per the secondary frame synchron izer block) has occurred since the last read of this register. note: the user can determine the curr ent state of ?los defect? (per the secondary frame synchronizer? block) by reading out the state of bit 6 (secondary frame synchronizer ? los defect declared) within the receive ds3/e3 status register ? secondary frame synchronizer block? register (address location= 0xn3f1). 5 change of ais defect condition interrupt status rur change of ais defect condition interrupt status ? secondary frame synchronizer block: this reset-upon-read bit-field indicates whether or not the ?change of ais defect condition? interrupt (per the secondary frame synchronizer block) has occurred since the last read of this register. 0 ? indicates that the ?change of ais defect condition? interrupt (per the secondary frame synchronizer block) has not occurred since the last read of this register. 1 ? indicates that the ?change of ais defect condition? interrupt (per the secondary frame synchron izer block) has occurred since the last read of this register. note: the user can determine the curr ent state of ?ais defect? (per the secondary frame synchronizer? block) by reading out the state of bit 7 (secondary frame synchronizer ? ais defect declared) within the receive ds3/e3 status register ? secondary frame synchronizer block? register (address location= 0xn3f1).
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 582 4 change of ds3 idle condition interrupt status rur change of ds3 idle condition interrupt status ? secondary frame synchronizer block: this reset-upon-read bit-field indicates whether or not the ?change of ds3 idle condition? interrupt (per the secondary frame synchronizer block) has occurred since the last read of this register. 0 ? indicates that the ?change of ds 3 idle condition? interrupt (per the secondary frame synchronizer block) has not occurred since the last read of this register. 1 ? indicates that the ?change of ds 3 idle condition? interrupt (per the secondary frame synchronizer block) has occurred since the last read of this register. note: the user can determine the curr ent ?ds3 idle? state (per the secondary frame synchronizer? block) by reading out the state of bit 5 (secondary frame synchronizer ? ds3 idle pattern detected) within the receive ds3/e3 status register ? secondary frame synchronizer block? register (address location= 0xn3f1). 3 - 2 unused r/o 1 change of oof defect condition interrupt status rur change of oof defect condition interrupt status ? secondary frame synchronizer block: this reset-upon-read bit-field indicates whether or not the ?change of oof defect condition? interrupt (per the secondary frame synchronizer block) has occurred since the last read of this register. 0 ? indicates that the ?change of oof defect condition? interrupt (per the secondary frame synchronizer block) has not occurred since the last read of this register. 1 ? indicates that the ?change of oof defect condition? interrupt (per the secondary frame synchron izer block) has occurred since the last read of this register. note: the user can determine the current state of ?oof defect? (per the secondary frame synchronizer? block) by reading out the state of bit 4 (secondary frame synchronizer ? oof defect declared) within the receive ds3/e3 status register ? secondary frame synchronizer block? register (address location= 0xn3f1). 0 unused r/o
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 583 1.11 transmit sone t poh processor block the register map for the transmit sonet poh proc essor block is presented in the table below. additionally, a detailed description of each of the ?transmit sonet poh proces sor? block registers is presented below. in order to provide some orientation for the reader, an illustration of the functional block diagram for the XRT94L33, with the ?transmit sonet poh processor bl ock ?highlighted? is pres ented below in figure 8. figure 8: illustration of the funct ional block diagram of the xrt9 4l33, with the transmit sonet poh processor block ?high-lighted?. ds3/e3 framer block ds3/e3 framer block rx sts-1 pointer justification block rx sts-1 pointer justification block rx sts-1 poh block rx sts-1 poh block tx sts-1 poh block tx sts-1 poh block tx sts-1 pointer justification block tx sts-1 pointer justification block tx sts-1 toh block tx sts-1 toh block rx sts-1 toh block rx sts-1 toh block ds3/e3 jitter attenuator block ds3/e3 jitter attenuator block ds3/e3 mapper block ds3/e3 mapper block tx sonet poh processor block tx sonet poh processor block tx sts-3 toh processor block tx sts-3 toh processor block sts-3 telecom bus block sts-3 telecom bus block tx/rx line i/f block (primary) tx/rx line i/f block (primary) tx/rx line i/f block (aps) tx/rx line i/f block (aps) clock synthesizer block clock synthesizer block channel 1 to channels 2 ? 3 microprocessor interface microprocessor interface jtag test port jtag test port rx sonet poh processor block rx sonet poh processor block rx sts-3 toh processor block rx sts-3 toh processor block from channels 2 ? 3 rx sts-3 toh processor block (primary) rx sts-3 toh processor block (primary)
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 584 transmit sonet poh pr ocessor block register table 419: transmit sonet poh processor block register - address map a ddress l ocation r egister n ame d efault v alues 0xn800 ? 0xn981 reserved 0x00 0xn982 transmit sonet path ? sonet control register ? byte 1 0x00 0xn983 transmit sonet path ? sonet control register ? byte 0 0x00 0xn984 ? 0xn8992 reserved 0x00 0xn993 transmit sonet path ? transmit j1 byte value register 0x00 0xn994 ? 0xn995 reserved 0x00 0xn996 transmit sonet path ? b3 byte control register 0x00 0xn997 transmit sonet path ? b3 byte mask register 0x00 0xn998 ? 0xn99a reserved 0x00 0xn99b transmit sonet path ? transmit c2 byte value register 0x00 0xn99c ? 0xn99e reserved 0x00 0xn99f transmit sonet path ? transmit g1 byte value register 0x00 0xn9a0 ? 0xn9a2 reserved 0x00 0xn9a3 transmit sonet path ? transmit f2 byte value register 0x00 0xn9a4 ? 0xn9a6 reserved 0x00 0xn9a7 transmit sonet path ? transmit h4 byte value register 0x00 0xn9a8 ? 0xn9aa reserved 0x00 0xn9ab transmit sonet path ? transmit z3 byte value register 0x00 0xn9ac ? 0xn9ae reserved 0x00 0xn9af transmit sonet path ? transmit z4 byte value register 0x00 0xn9b0 ? 0xn9b2 reserved 0x00 0xn9b3 transmit sonet path ? transmit z5 byte value register 0x00 0xn9b4 ? 0xn9b6 reserved 0x00 0xn9b7 transmit sonet path ? transmit path control register ? byte 0 0x00 0xn9b8 ? 0xn9ba reserved 0x00 0xn9bb transmit sonet path ? transmit j1 control register 0x00 0xn9bc ? 0xn9be reserved 0x00 0xn9bf transmit sonet path ? transmit arbitrary h1 byte pointer register 0x94 0xn9c0 ? 0xn9c2 reserved 0x00 0xn9c3 transmit sonet path ? transmit arbitrary h2 byte pointer register 0x00
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 585 a ddress l ocation r egister n ame d efault v alues 0xn9c4 ? 0xn9c5 reserved 0x00 0xn9c6 transmit sonet path ? transmit po inter byte register ? byte 1 0x02 0xn9c7 transmit sonet path ? transmit po inter byte register ? byte 0 0x0a 0xn9c8 reserved 0x00 0xn9c9 transmit sonet path ? rdi-p control register ? byte 2 0x40 0xn9ca transmit sonet path ? rdi-p control register ? byte 1 0xc0 0xn9cb transmit sonet path ? rdi-p control register ? byte 0 0xa0 0xn9cc ? 0xn9ce reserved 0x00 0xn9cf transmit sonet path ? transmit path serial port control register 0x00 0xn9d0 ? 0xn9ff reserved 0x00
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 586 1.11.1 transmit sonet poh processor block register description table 420: transmit sonet path ? sonet contro l register ? byte 1 (address location= 0xn982, where n ranges in value from 0x02 to 0x04) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 unused z5 byte insertion type z4 byte insertion type z3 byte insertion type h4 byte insertion type r/w r/o r/o r/o r/w r/w r/w r/w 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 ? 4 unused r/o 3 z5 byte insertion type r/w z5 byte insertion type: this read/write bit-field permits the user to configure the transmit sonet poh processor block to use either the contents within the ?transmit sonet path ? transmit z5 byte value? register or the tpoh input pin as the source for the z5 byte, in t he outbound sts-1 spe data-stream, as described below. 0 ? configures the transmit sonet poh processor block to insert the contents within the ?transmit sonet path ? transmit z5 byte value? register into the z5 byte position within ea ch outbound sts-1 spe. 1 ? configures the transmit sonet poh processor block to accept externally supplied data (via the ?tpoh? input port) and to insert this data into the z5 byte position with in each outbound sts-1 spe. note: the address location of the transmit sonet poh processor block ? transmit z5 byte value register is 0xn9b3. 2 z4 byte insertion type r/w z4 byte insertion type: this read/write bit-field permits the user to configure the transmit sonet poh processor block to use eit her the contents within the ?transmit sonet path ? transmit z4 byte value? register or the tpoh input pin as the source for the z4 byte, in t he outbound sts-1 spe data-stream, as described below. 0 ? configures the transmit sonet poh processor block to insert the contents within the ?transmit sonet path ? transmit z4 byte value? register into the z4 byte position within ea ch outbound sts-1 spe. 1 ? configures the transmit sonet poh processor block to accept externally supplied data (via the ?tpoh? input port) and to insert this data into the z4 byte position with in each outbound sts-1 spe. note: the address location of the transmit sonet poh processor block ? transmit z4 byte value register is 0xn9af. 1 z3 byte insertion type r/w z3 byte insertion type: this read/write bit-field permits the user to configure the transmit sonet poh processor block to use eit her the contents within the ?transmit sonet path ? transmit z3 byte value? register or the tpoh input pin as the source for the z3 byte, in t he outbound sts-1 spe data-stream, as described below. 0 ? configures the transmit sonet poh processor block to insert the contents within the ?transmit sonet path ? transmit z3 byte value? register into the z3 byte position within ea ch outbound sts-1 spe.
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 587 1 ? configures the transmit sonet poh processor block to accept externally supplied data (via the ?tpoh? input port) and to insert this data into the z3 byte position with in each outbound sts-1 spe. note: the address location of the transmit sonet poh processor block ? transmit z3 byte value register is 0xn9ab. 0 h4 byte insertion type r/w h4 byte insertion type: this read/write bit-field permits the user to configure the transmit sonet poh processor block to use eit her the contents within the ?transmit sonet path ? transmit h4 byte value? register or the tpoh input pin as the source for the h4 byte, in t he outbound sts-1 spe data-stream, as described below. 0 ? configures the transmit sonet poh processor block to insert the contents within the ?transmit sonet path ? transmit h4 byte value? register into the h4 byte posi tion within each outbound sts-1 spe. 1 ? configures the transmit sonet poh processor block to accept externally supplied data (via the ?tpoh? input port) and to insert this data into the h4 byte position within each outbound sts-1 spe. note: the address location of the transmit sonet poh processro block ? transmit h4 byte value register is 0xn9a7.
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 588 table 421: transmit sonet path ? sonet contro l register ? byte 0 (address location= 0xn983, where n ranges in value from 0x02 to 0x04) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 f2 byte insertion type rei-p insertion type[1:0] rdi-p insertion type[1:0] c2 byte insertion type c2 byte auto insert mode enable force transmission of ais-p r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 f2 byte insertion type r/w f2 byte insertion type: this read/write bit-field permits the user to configure the transmit sonet poh processor block to use eit her the contents within the ?transmit sonet path ? transmit f2 byte value? register or the tpoh input pin as the source for the f2 byte, in t he outbound sts-1 spe data-stream, as described below. 0 ? configures the transmit sonet poh processor block to insert the contents within the ?transmit sonet path ? transmit f2 byte value? register into the f2 byte posit ion within each outbound sts-1 spe. 1 ? configures the transmit sonet poh processor block to accept externally supplied data (via the ?tpoh? input port) and to insert this data into the f2 byte position with in each outbound sts-1 spe. note: the address location of the transmit sonet poh processor block ? transmit f2 byte value register is 0xn9a3. 6 - 5 rei-p insertion type[1:0] r/w rei-p insertion type[1:0]: these two read/write bit-fields permit the user to configure the transmit sonet poh processor block to use one of the three following sources for the rei-p bit-fields (e.g., bits 1 through 4, within the g1 byte of the outbound sts-1 spe). ? from the corresponding receive sonet poh processor block (e g., the transmit sonet poh processor block wi ll set the rei-p bit-fields to the appropriate value, based upon the number b3 byte errors that the corresponding receive sonet poh processor block detects and flags, within its incoming sts-1 spe data-stream). ? from the ?transmit g1 byte value? register. in this case, the transmit sonet poh processor block will insert the contents of bits 7 through 4 within the ?transmit sonet poh processor block ? transmit g1 byte value? register into the rei-p bit-fiel ds within each outbound sts-1 spe. ? from the ?tpoh? input pin. in this case, the transmit sonet poh processor block will accept externally supplied data (via the ?tpoh? input port) and it will insert this data into the rei-p bit-fields within each outbound sts-1 spe. 00/11 ? configures the transmit sonet poh processor block to set bits 1 through 4 (in the g1 byte of the outbound spe) based upon the number of b3 byte errors that the corresponding receive sonet poh processor block detects and flags within the incoming sts-1 data-stream. 01 ? configures the transmit sonet poh processor block to set bits 1 through 4 (in the g1 byte of the outbound spe) based upon the contents within the ?transmit sonet poh processor block - transmit g1 byte value? register. 10 ? confi g ures the transmit sonet poh processor block to acce p t
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 589 externally supplied data (via the tpoh i nput port) and to insert this data into the rei-p bit-positions with in each outbound sts-1 spe. note: the address location of the transmit sonet poh processor block ? transmit g1 byte value register is 0xn99f . 4 - 3 rdi-p insertion type[1:0] r/w rdi-p insertion type[1:0]: these two read/write bit-fields permit the user to configure the transmit sonet poh processor block to use one of the three following sources for the rdi-p bit-fields (e.g., bits 5 through 7, within the g1 byte of the outbound sts-1 spe). ? from the corresponding receive sonet poh processor block (e g., when it detects various defect conditi ons within its incoming spe data). ? from the ?transmit g1 byte value? register (address location= 0xn99f). ? from the ?tpoh? input pin. 00/11 ? configures the transmit sonet poh processor block to set bits 5 through 7 (in the g1 byte of the outbound spe) to the appropriate value coincident to whenever the receive sonet poh processor block declares any defect conditions? within t he incoming sts-1 data-stream.. 01 ? configures the transmit sonet poh processor block to set bits 5 through 7 (in the g1 byte of the outbound spe) based upon the contents within the ?transmit g1 byte value? register. 10 ? configures the transmit sonet po h processor block to use the tpoh input pin as the source of bits 5 th rough 7 (in the g1 byte of the outbound spe). 2 c2 byte insertion type r/w c2 insertion type: this read/write bit-field permits the user to configure the transmit sonet poh processor block to use ei ther the ?transmit sonet path ? transmit c2 value? register or the tpoh input pin as the source for the c2 byte, in the outbound sts-1 spe data-stream. 0 ? configures the transmit sonet poh processor block to use the ?transmit sonet path ? transmit c2 value? register (address location= 0xn99b). 1 ? configures the transmit sonet poh processor block to use the ?tpoh? input as the source for the c2 byte, in the outbound sts-1 spe. 1 auto-insert pdi-p indicator enable r/w auto-insert pdi-p indicator enable: this read/write bit-field permit the user to configure the transmit sonet poh processor block to automatically transmit the pdi-p (path - payload defect indicator) whenever the ds3/e3 framer block declares an los, oof or ais condition. if this feature is enabled, then the tr ansmit sonet poh processor block will automatically set the c2 byte (within the outbound spe) to 0xfc (to indicate a pdi-p condition) whenever the ds3/e3 framer block declares the los, oof or ais condition. 0 ? disables the ?auto-insert pdi-p? feature. 1 ? enables the ?auto-insert pdi-p? feature. note: this bit-field is only value if the ds3/e3 framer block (within the corresponding channel) has been enabled. 0 transmit ais-p enable r/w transmit ais-p enable: this read/write bit-field permits the user to configure the transmit sonet poh processor block to ( via software control ) transmit an ais-p
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 590 indicator to th e remote pte. if this feature is enabled, then the tr ansmit sonet poh processor block will unconditionally set the h1, h2, h3 and all the spe bytes to an ?all ones? pattern, prior to routing this data to the transmit sts-3 toh processor block. 0 ? configures the transmit sonet po h processor block to not transmit the ais-p indicator to the remote pte. 1 ? configures the transmit sonet po h processor block to transmit the ais-p indicator to the remote pte. note: for normal operation, the user should set this bit-field to ?0?.
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 591 table 422: transmit sonet path ? transmitter j1 byte value register (address location= 0xn993, where n ranges in value from 0x02 to 0x04) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 transmit_j1_byte[7:0] r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 - 0 transmit j1 byte value[7:0] r/w transmit j1 byte value: these read/write bit-fields permit the user to have software control over the value of the j1 byte, within each outbound sts-1 spe. if the user configures the transmit sonet poh processor block to this register as the source of the j1 byte , then it will automatically write the contents of this register into the j1 byte location, within each ?outbound? sts-1 spe. this feature is enabled whenever the user writes a ?[1, 0]? into bit 1 and 0 (transmit path trace message source[1:0]) within the ?transmit sonet path ? sonet path trace message control register? register (address location= 0xn983).
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 592 table 423: transmit sonet path ? b3 byte control register (address location = 0xn996, where n ranges in value from 0x02 to 0x04) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 unused b3 pass thru mode r/o r/o r/o r/o r/o r/o r/o r/w 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 - 1 unused r/o 0 b3 pass thru mode r/w b3 pass-thru mode: this read/write bit-field permits the user to configure the transmit sonet poh processor block to do either of the following. o. to operate in the ?normal? mode. p. to operate in the ?b3 pass-thru? mode. if in normal mode if the transmit sonet poh processor has been configured to operate in the ?normal? mode, then it will compute and insert a new b3 byte into each outbound sts-1 spe. if in the b3 pass-thru mode if the transmit sonet poh processor block has been configured to operate in the ?b3 pass-thru? mode, t hen it will not modify the b3 byte values within the sts-1 spes that it receives from its corresponding receive sts-1 poh processor block. 0 ? configures the transmit sonet po h processor block to operate in the ?normal? mode. 1 ? configures the transmit sonet po h processor block to operate in the ?b3 pass-thru? mode. note: this bit-field is not active if the corresponding channel has been configured to operate in the ds3/e3 mode.
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 593 table 424: transmit sonet path ? transmitter b3 byte error mask register (address location= 0xn997, where n ranges in value from 0x02 to 0x04) \ b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 transmit_b3_byte_error_mask[7:0] r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 - 0 transmit b3 byte error mask[7:0] r/w transmit b3 byte error mask[7:0]: this read/write bit-field permits the user to insert errors into the b3 byte, within each ?outbound? st s-1 spe, prior to transmi ssion to the transmit sts-3 toh processor block. the transmit sonet poh processor block will perform an xor operation with the contents of this register, and its ?locally-computed? b3 byte value. the results of this operation will be written back into the b3 byte position within each ?outbound? sts-1 spe. if the user sets a particular bit-field, within this register, to ?1?, then that corresponding bit, within the ?outbound? b3 byte will be in error. note: for normal operation, the user should set this register to 0x00. table 425: transmit sonet path ? transmit c2 byte value register (address location= 0xn99b, where n ranges in value from 0x02 to 0x04) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 transmit_c2_byte_value[7:0] r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 - 0 transmit c2 byte value[7:0] r/w transmit c2 byte value: these read/write bit-fields permit the user to have software control over the value of the c2 byte, with in each outbound sts-1 spe. if the user configures the transmit sonet poh processor block to this register as the source of the c2 by te, then it will automatically write the contents of this register into the c2 byte location, within each ?outbound? sts-1 spe. this feature is enabled whenever the user writes a ?0? into bit 2 (c2 byte insertion type) within the ?transmit so net path ? sonet control register ? byte 0? register (address location= 0xn983).
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 594 table 426: transmit sonet path ? transmit g1 byte value register (address location= 0xn99f, where n ranges in value from 0x02 to 0x04) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 transmit_g1_byte_value[7:0] r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 - 0 transmit g1 byte value[7:0] r/w transmit g1 byte value: these read/write bit-fields permit the user to have software control over the contents of the rdi-p and rei-p bit-fields, within each g1 byte in the ?outbound? sts-1 spe. if the users sets ?rei-p_insertion_type[ 1:0]? and ?rdi-p_insertion_type[1:0]? bits to the value [0, 1], then contents of the rei-p and the rdi-p bit-fields (within each g1 byte of the ?outboun d? sts-1 spe) will be dictated by the contents of this register. note: the ?rei-p_insertion_type[1:0]? and ?rdi-p_insertion_type[1:0]? bit- fields are located in the ?transmit sonet path ? sonet control register ? byte 0? register (address location= 0xn983) table 427: transmit sonet path ? transmit f2 byte value register (address location= 0xn9a3, where n ranges in value from 0x02 to 0x04) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 transmit_f2_byte_value[7:0] r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 - 0 transmit f2 byte value[7:0] r/w transmit f2 byte value: these read/write bit-fields permit the user to have software control over the value of the f2 byte, with in each outbound sts-1 spe. if the user configures the transmit sonet poh processor block to this register as the source of the f2 byte , then it will automatically write the contents of this register into the f2 byte location, within each ?outbound? sts-1 spe. this feature is enabled when ever the user writes a ?0? into bit 7 (f2 insertion type) within the ?transmit sonet path ? sonet control register ? byte 0? register (address location= 0xn983).
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 595 table 428: transmit sonet path ? transmit h4 byte value register (address location= 0xn9a7, where n ranges in value from 0x02 to 0x04) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 transmit_h4_byte_value[7:0] r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 - 0 transmit h4 byte value[7:0] r/w transmit h4 byte value: these read/write bit-fields permit the user to have software control over the value of the h4 byte, with in each outbound sts-1 spe. if the user configures the transmit sonet poh processor block to this register as the source of the h4 by te, then it will automatically write the contents of this register into the h4 byte location, within each ?outbound? sts-1 spe. this feature is enabled when ever the user writes a ?0? into bit 0 (h4 insertion type) within the ?transmit sonet path ? sonet control register ? byte 1? register (address location= 0xn9a7). note: this bit-field is configured if the XRT94L33 device has been configured to operate in ?sts-1 poh pass-thru? mode. table 429: transmit sonet path ? transmit z3 byte value register (address location= 0xn9ab, where n ranges in value from 0x02 to 0x04) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 transmit_z3_byte_value[7:0] r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 - 0 transmit z3 byte value[7:0] r/w transmit z3 byte value: these read/write bit-fields permit the user to have software control over the value of the z3 byte, with in each outbound sts-1 spe. if the user configures the transmit sonet poh processor block to this register as the source of the z3 byte , then it will automatically write the contents of this register into the z3 byte location, within each ?outbound? sts-1 spe. this feature is enabled when ever the user writes a ?0? into bit 1 (z3 insertion type) within the ?transmit sonet path ? sonet control register ? byte 0? register (address location= 0xn982).
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 596 table 430: transmit sonet path ? transmit z4 byte value register (address location= 0xn9af, where n ranges in value from 0x02 to 0x04) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 transmit_z4_byte_value[7:0] r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 - 0 transmit z4 byte value[7:0] r/w transmit z4 byte value: these read/write bit-fields permit the user to have software control over the value of the z4 byte, with in each outbound sts-1 spe. if the user configures the transmit sonet poh processor block to this register as the source of the z4 byte , then it will automatically write the contents of this register into the z4 byte location, within each ?outbound? sts-1 spe. this feature is enabled when ever the user writes a ?0? into bit 2 (z4 insertion type) within the ?transmit sonet path ? sonet control register ? byte 0? register (address location= 0xn982). table 431: transmit sonet path ? transmit z5 byte value register (address location= 0xn9b3, where n ranges in value from 0x02 to 0x04) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 transmit_z5_byte_value[7:0] r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 - 0 transmit z5 byte value[7:0] r/w transmit z5 byte value: these read/write bit-fields permit the user to have software control over the value of the z5 byte, wi thin each outbound sts-1 spe. if the user configures the transmit sonet poh processor block to this register as the source of the z5 byte , then it will automatically write the contents of this register into the z5 byte location, within each ?outbound? sts-1 spe. this feature is enabled whenever the user writes a ?0? into bit 3 (z5 insertion type) within the ?transmit sonet path ? sonet control register ? byte 0? register (address location= 0xn982).
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 597 table 432: transmit sonet path ? transmit path control register (address location= 0xn9b7, where n ranges in value from 0x02 to 0x04) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 unused pointer force check stuff insert negative stuff insert positive stuff insert continuous ndf events insert single ndf event r/o r/o r/w r/w w w r/w r/w 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 - 6 unused r/o 5 pointer force r/w pointer force: this read/write bit-field permits the user to load the values contained within the ?transmit sonet poh arbitrary h1 pointer? and ?transmit sonet poh arbitrary h2 pointer? registers (address location= 0xn9bf and 0xn9c3) into the h1 and h2 by tes (within the outbound sts-1 data stream). note: the actual location of the spe w ill not be adjusted, per the value of h1 and h2 bytes. hence, th is feature should cause the remote terminal to declare an ?invalid pointer? condition. 0 ? configures the transmit sonet poh and transmit sts-3 toh processor blocks to transmit sts-1/sts-3 data with normal and correct h1 and h2 bytes. 1 ? configures the transmit sonet poh and transmit sts-3 toh processor blocks to overwrite the val ues of the h1 and h2 bytes (in the outbound sts-1/sts-3 data-stream) wi th the values in the ?transmit sonet poh arbitrary h1 and h2 pointer? registers. 4 check stuff r/w check stuff monitoring: this read/write bit-field permits the user to configure the transmit sonet poh and transmit sts-3 toh processor blocks to only execute a ?positive?, ?negative? or ?ndf? event (v ia the ?insert positive stuff?, ?insert negative stuff?, ?insert continuous or single ndf? options, via software command) if no pointer adjustment (ndf or otherwise) has occurred during the last 3 sonet frame periods. 0 ? disables this feature. in this mode, the transmit sonet poh and transmit sts-3 toh processor blocks will execute a ?software-commanded? pointer adjustment event, independent of whether a pointe r adjustment event has occurred in the last 3 sonet frame periods. 1 ? enables this feature. in this mode, the transmit sonet poh and transmit sts-3 toh processor blocks will only execut e a ?software-commanded? pointer adjustment event, if no pointer adjustm ent event has occurred during the last 3 sonet frame periods. 3 insert negative stuff r/w insert negative stuff: this read/write bit-field permits the user to configure the transmit sonet poh and transmit sts-3 toh processor blocks to insert a negative-stuff into the outbound sts-1/ sts-3 data stream. this command, in-turn will cause a ?pointer decrementi ng? event at the remote terminal. writin g a ?0? to ?1? transition into this bit-field causes the followin g to
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 598 happen. ? a negative-stuff will occur (e.g., a single payload byte will be inserted into the h3 byte position within the outbound sts-1/sts-3 data stream). ? the ?d? bits, within the h1 and h2 bytes will be inverted (to denote a ?decrementing? pointer adjustment event). ? the contents of the h1 and h2 bytes will be decremented by ?1?, and will be used as the new pointer from this point on. note: once the user writes a ?1? into this bit-field, the XRT94L33 will automatically clear this bit-fiel d. hence, there is no need to subsequently reset this bit-field to ?0?. 2 insert positive stuff r/w insert positive stuff: this read/write bit-field permits the user to configure the transmit sonet poh and transmit sts-3 toh processor blocks to insert a positive-stuff into the outbound sts- 1/sts-3 data stream. this command, in-turn will cause a ?pointer incrementi ng? event at the remote terminal. writing a ?0? to ?1? transition into this bit-field causes the following to happen. ? a positive-stuff will occu r (e.g., a single stuff-byte will be inserted into the sts-1/sts-3 data-stream, i mmediately after the h3 byte position within the outbound sts-1/sts- 3 data stream). ? the ?i? bits, within the h1 and h2 bytes will be inverted (to denote a ?incrementing? pointer adjustment event). ? the contents of the h1 and h2 bytes will be incremented by ?1?, and will be used as the new pointer from this point on. note: once the user writes a ?1? into this bit-field, the XRT94L33 will automatically clear this bit-fiel d. hence, there is no need to subsequently reset this bit-field to ?0?. 1 insert continuous ndf events r/w insert continuous ndf events: this read/write bit-field permits t he user configure the transmit sonet poh and transmit sts-3 toh processor blocks to continuously insert a new data flag (ndf) pointer adjus tment into the outbound sts-1/sts-3 data stream. note: as the transmit sonet poh and transmit sts-3 toh processor blocks insert the ndf event into the sts-1/sts-3 data stream, it will proceed to load in the cont ents of the ?transmit sonet poh arbitrary h1 pointer? and ?transmit sonet poh arbitrary h2 pointer? registers into the h1 and h2 bytes (within the outbound sts-1/sts-3 data stream). 0 ? configures the ?transmit sonet toh and transmit sts-3 poh processor? blocks to not continuously insert ndf events in to the ?outbound? sts-1/sts-3 data stream. 1- configures the ?transmit sonet toh and transmit sts-3 poh processor? blocks to continuously inse rt ndf events into the ?outbound? sts-1/sts-3 data stream. 0 insert single ndf event r/w insert single ndf event: this read/write bit-field permits the user to configure the transmit sonet poh and transmit sts-3 toh processor blocks to insert a new data flag (ndf) pointer adjustment into the outbound sts-1/sts-3 data stream. writing a ?0? to ?1? transition into this bit-field causes the following to happen.
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 599 ? the ?n? bits, within the h1 byte will set to the value ?1001? ? the ten pointer-value bits (within the h1 and h2 bytes) will be set to new pointer value per the contents within the ?transmit sonet poh ? arbitrary h1 pointer? and ?transmit sonet poh arbitrary h2 pointer? registers (address location= 0xn9bf and 0xn9c3). ? afterwards, the ?n? bits will resume their normal value of ?0110?; and this new pointer value will be used as the new pointer from this point on. note: once the user writes a ?1? into this bit-field, the XRT94L33 will automatically clear this bit-fiel d. hence, there is no need to subsequently reset this bit-field to ?0?.
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 600 table 433: transmit sonet path ? transmit path trace message control register (address location= 0xn9bb, where n ranges in value from 0x02 to 0x04) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 unused transmit path trace message_length[1:0] transmit path tarce message source[1:0] r/o r/o r/o r/o r/w r/w r/w r/w 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 ? 4 unused r/o 3 - 2 transmit path trace message_length [1:0] r/w transmit path trace message length[1:0]: these read/write bit-fields permit the user to specify the length of the path trace message, that the transmit sonet poh processor block will repeatedly transmit to the remote pte. the relationship between the content of these bit-fields and the corresponding path trace message length is presented below. transmit path trace message length resulting path trace message length (in terms of bytes) 00 1 byte 01 16 bytes 10/11 64 bytes 1 - 0 transmit path trace message source[1:0] r/w transmit path trace message source[1:0]: these read/write bit-fields permit the user to specify the source of the ?outbound? path trace message that will be transported via the j1 byte channel within the outb ound sts-1 spe data-stream as depicted below. transmit path trace message source[1:0] resulting source of the path trace message 00 fixed value: the transmit sonet poh processor block will automatically set the j1 byte, within each outbound sts-1 spe to the value ?0x00? 01 the transmit path trace message buffer: the transmit sonet poh processor block will read out the contents within the transmit path trace message buffer, and will transmit this message to the remote pte. the transmit sonet poh processor block ? transmit path trace message buffer memory is located at address locations 0xnd00 through 0xnd3f (where n ranges in value from 0x02 to 0x04) 10 from the ?transmit j1 byte value[7:0]? register: in this settin g , the transmit sonet poh
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 601 processor block will read out the contents of the transmit sonet path ? transmit j1 byte value register, and will insert this value into the j1 byte-position within each outbound sts-1 spe. 11 from the ?txpoh? input pin: in this configuration setting, the transmit sonet poh processor block will externally accept the contents of the ?path trace message? via the ?txpoh input port? and it will transport this message (via the j1 byte-channel) to the remote pte.
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 602 table 434: transmit sonet path ? transmit arbitr ary h1 byte pointer register (address location= 0xn9bf, where n ranges in value from 0x02 to 0x04) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 ndf bits ss bits h1 pointer value r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 - 4 ndf bits r/w ndf (new data flag) bits: these read/write bit-fields permit the user provide the value that will be loaded into the ?ndf? bit-field (of the h1 byte), whenever a ?0 to 1? transition occurs in bit 5 (pointer fo rce) within the ?transmit sonet path ? transmit path control? register (address location= 0xn9b7). 3 - 2 ss bits r/w ss bits these read/write bit-fields permits the user to provide the value that will be loaded into the ?ss? bit-fields (of the h1 byte) whenever a ?0 to 1? transition occurs in bit 5 (pointer force) within the ?transmit sonet path ? transmit path control? register (address location= 0xn9b7). note: for sonetapplications, the ?ss? bits have no functional value, within the h1 byte. 1 - 0 h1 pointer value[1:0] r/w h1 pointer value[1:0]: these two read/write bit-fields, along with the constants of the ?transmit sonet path ? transmit arbitrary h2 byte pointer? register (address location= 0xn9c3) permit the user to provide the contents of the pointer word. these two read/write bit-fields permits the user to define the value of the two most significant bits within the pointer word. whenever a ?0 to 1? transition occurs in bit 5 (pointer force) within the transmit sonet path ? transmit path control? register (address location= 0xn9b7), the values of t hese two bits will be loaded into the two most significant bits within the pointer word.
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 603 table 435: transmit sonet path ? transmit arbitr ary h2 byte pointer register (address location= 0xn9c3, where n ranges in value from 0x02 to 0x04) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 h2 pointer value[7:0] r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 - 0 h2 pointer value[7:0] r/w h2 pointer value[1:0]: these eight read/write bit-fields, al ong with the constants of bits 1 and 0 within the ?transmit sonet path ? transmit arbitrary h1 pointer? register (address location= 0xn9c3) permit the user to provide the contents of the 10-bit pointer word. these two read/write bit-fields permit the user to define the value of the eight least significant bits within the pointer word. whenever a ?0 to 1? transition occurs in bit 5 (pointer force) within the transmit sonet path ? transmit path control? register (address location= 0xn9b7), the values of thes e eight bits will be loaded into the h2 byte, within the outbo und sts-1/sts-3 data stream. table 436: transmit sonet path ? transmit curr ent pointer byte register ? byte 1 (address location= 0xn9c6, where n ranges in value from 0x02 to 0x04) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 unused tx_pointer_high[1:0] r/o r/o r/o r/o r/o r/o r/o r/o 0 0 0 0 0 0 1 0 b it n umber n ame t ype d escription 7 ? 2 unused r/o 1 - 0 tx_pointer_high[1:0] r/o transmit pointer word ? high[1:0]: these two read-only bits, along with the contents of the ?transmit sonet path ? transmit current pointer byte register ? byte 0? (address location= 0xn9c7) reflect t he current value of the pointer (or offset of the sts-1 spe with in the outbound sts-1 frame). these two bits contain the two most significant bits within the ?10-bit pointer? word.
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 604 table 437: transmit sonet path ? transmit current pointer byte register ? byte 0 (address location= 0xn9c7, where n ranges in value from 0x02 to 0x04) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 tx_pointer_low[7:0] r/o r/o r/o r/o r/o r/o r/o r/o 0 0 0 0 1 0 1 0 b it n umber n ame t ype d escription 7 ? 0 tx_pointer_low[7:0] r/o transmit pointer word ? low[7:0]: these two read-only bits, along with the contents of the ?transmit sonet path ? transmit current pointer byte register ? byte 1? (address location= 0xn9c6) reflect t he current value of the pointer (or offset of the sts-1 spe with in the outbound sts-1 frame). these two bits contain the eight least significant bits within the ?10-bit pointer? word.
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 605 table 438: transmit sonet path ? rdi-p control register ? byte 2 (address location= 0xn9c9, where n ranges in value from 0x02 to 0x04) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 unused plm-p rdi-p code[2:0] transmit rdi-p upon plm-p r/o r/o r/o r/o r/w r/w r/w r/w 0 1 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 ? 5 unused r/o 3 - 1 plm-p rdi-p code[2:0] r/w plm-p (path ? payload mismatch) defect ? rdi-p code: these three read/write bit-fields permit the user to specify the value that the transmit sonet poh processor block will transmit, within the rdi-p bit-fields of the g1 byte (w ithin the each ?o utbound? sts-1 spe), whenever (and for the duration t hat) the corresponding receive sonet poh processor block detects and declares the plm-p defect condition. note: in order to enable this feature, the user must set bit 0 (transmit rdi-p upon plm-p) within this register to ?1?. 0 transmit rdi-p upon plm-p r/w transmit the rdi-p indicator upon declaration of the plm-p defect condition: this read/write bit-field permits the user to configure the transmit sonet poh processor block to automat ically transmit the rdi-p code (as configured in bits 3 through 1 ? within this register) towards the remote pte whenever (and for the duration that) the corresponding receive sonet poh processor block declares the plm-p defect condition. 0 ? configures the transmit sone t poh processor block to not automatically transmit the rdi-p indicator whenever (and for the duration that) the receive sonet poh processor block declares the plm-p defect condition. 1 ? configures the transmit sonet poh processor block to automatically transmit the rdi-p indicator whenever (and for the duration that) the receive sonet poh processor block declares the plm-p defect condition. note: the transmit sonet poh processor block will transmit the rdi-p indicator (in response to the receive sonet poh processor block declaring the plm-p defect condition) by setting the rdi-p bit- fields (within each outbound sts-1 spe) to the contents within the ?plm-p rdi-p code[2:0]? bit-fi elds within this register.
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 606 table 439: transmit sonet path ? rdi-p contro l register ? byte 1 (address location= 0xn9ca, where n ranges in value from 0x02 to 0x04) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 tim-p rdi-p code[2:0] transmit rdi-p upon tim-p uneq-p rdi-p code[2:0] transmit rdi-p upon uneq-p r/w r/w r/w r/w r/w r/w r/w r/w 1 1 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 - 5 tim-p rdi-p code[2:0] r/w tim-p (path ? trace identification mismatch) defect ? rdi-p code: these three read/write bit-fields permit the user to specify the value that the transmit sonet poh processor blo ck will transmit, within the rdi-p bit- fields of the g1 byte (within each ?outbound? sts-1 spe), whenever (and for the duration that) the corresponding receive sonet poh processor block detects and declares the tim-p defect condition. note: in order to enable this feature, t he user must set bit 4 (transmit rdi- p upon tim-p) within this register to ?1?. 4 transmit rdi-p upon tim-p r/w transmit the rdi-p indicator upon declaration of the tim-p defect condition: this read/write bit-field permits the user to configure the transmit sonet poh processor block to automat ically transmit the rdi-p code (as configured in bits 7 through 5 ? within this register) towards the remote pte whenever (and for the duration that) the corresponding receive sonet poh processor block declares the tim-p defect condition. 0 ? configures the transmit sone t poh processro block to not automatically transmit the rdi-p indicator whenever (and for the duration that) the corresponding receive sone t poh processor block declares the tim-p defect condition. 1 ? configures the transmit sonet po h processor block to automatically transmit the rdi-p indicator whenever (and for the duration that) the receive sonet poh processor block declare s the tim-p defect condition. note: the transmit sonet poh processor block will transmit the rdi-p indicator (in response to the corresponding receive sonet poh processor block declaring the tim-p defect condition) by setting the rdi-p bit-fields (within each outbound sts-1 spe) to t he contents within the ?tim-p rdi-p code[2:0]? bit-fields within this register. 3 - 1 uneq-p rdi-p code[2:0] r/w uneq-p (path ? unequipped) defect ? rdi-p code: these three read/write bit-fields permit the user to specify the value that the transmit sonet poh processor blo ck will transmit, within the rdi-p bit- fields of the g1 byte (within the ?o utbound? sts-1 spe), whenever (and for the duration that) the corresponding receive sonet poh processor block detects and declares the uneq-p defect condition. note: in order to enable this feature, t he user must set bit 0 (transmit rdi- p upon uneq-p) within this register to ?1?. 0 transmit rdi-p upon uneq-p r/w transmit the rdi-p indicator upon declaration of the uneq-p defect condition: this read/write bit-field permits the user to configure the transmit sonet poh processor block to automat ically transmit the rdi-p code (as configured in bits 7 through 5 ? within this register) towards the remote pte whenever ( and for the duration that ) the corres p ondin g receive sonet poh
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 607 processor block declares the uneq-p defect condition. 0 ? configures the transmit sone t poh processor block to not automatically transmit the rdi-p indicator whenever (and for the duration that) the receive sonet poh processor block declares the uneq-p defect condition. 1 ? configures the transmit sonet po h processor block to automatically transmit the rdi-p indicator whenev er (and for the duration that) the corresponding receive sonet poh processor block declares the uneq-p defect condition. note: the transmit sonet poh processor block will transmit the rdi-p indicator (in response to the corresponding receive sonet poh processor block declaring the uneq-p defect condition) by setting the rdi-p bit-fields (within each outbound sts-1 spe) to t he contents within the ?uneq-p rdi-p code[2:0]? bit-fields within this register.
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 608 table 440: transmit sonet path ? rdi-p contro l register ? byte 0 (address location= 0xn9cb, where n ranges in value from 0x02 to 0x04) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 lop-p rdi-p code[2:0] transmit rdi-p upon lop-p ais-p rdi-p code[2:0] transmit rdi-p upon ais-p r/w r/w r/w r/w r/w r/w r/w r/w 1 1 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 - 5 lop-p rdi-p code[2:0] r/w lop-p (path ? loss of pointer) defect ? rdi-p code: these three read/write bit-fields permit the user to specify the value that the transmit sonet poh processor block will transmit, within the rdi-p bit-fields of the g1 byte (within the ?outbound? sts- 1 spe), whenever (and for the dur ation that) the corresponding receive sonet poh processor bl ock detects and declares the lop-p defect condition. note: in order to enable this featur e, the user must set bit 4 (transmit rdi-p upon lop-p) within this register to ?1?. 4 transmit rdi-p upon lop-p r/w transmit the rdi-p indicator upon declaration of the lop-p defect condition: this read/write bit-field permi ts the user to configure the transmit sonet poh processor block to automatically transmit the rdi-p code (as configured in bits 7 through 5 ? within this register) towards the remote pte whenever (and for the duration that) the corresponding receive sonet poh processor block declares the lop-p defect condition. 0 ? configures the transmit sone t poh processor block to not automatically transmit the rdi-p indicator whenever (and for the duration that) the corresponding receive sonet poh processor block declares the lop-p defect condition. 1 ? configures the transmit sonet poh processor block to automatically transmit the rdi-p indicator whenever (and for the duration that) the corresponding receive sonet poh processor block declares the lop-p defect condition. note: the transmit sonet poh processor block will transmit the rdi-p indicator (in response to the receive sonet poh processor block declaring the lop-p defect condition) by setting the rdi-p bit- fields (within each outbound sts-1 spe) to the contents within the ?lop-p rdi-p code[2:0]? bit-fi elds within this register. 3 - 1 ais-p rdi-p code[2:0] r/w ais-p (path ? ais) defect ? rdi-p code: these three read/write bit-fields permit the user to specify the value that the transmit sonet poh processor block will transmit, within the rdi-p bit-fields of the g1 byte (within the ?outbound? sts- 1 spe), whenever (and for the dur ation that) the corresponding receive sonet poh processor bl ock detects and declares the ais-p defect condition. note: in order to enable this featur e, the user must set bit 0 (transmit rdi-p upon ais-p) within this register to ?1?. 0 transmit rdi-p upon ais-p r/w transmit the rdi-p indicator upon declaration of the ais-p defect condition: this read/write bit-field permi ts the user to configure the transmit sonet poh processor block to automaticall y transmit the
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 609 rdi-p code (as configured in bits 7 through 5 ? within this register) towards the remote pte whenever (and for the duration that) the corresponding receive sonet poh processor block declares the ais-p defect condition. 0 ? configures the transmit sone t poh processor block to not automatically transmit the rdi-p indicator whenever (and for the duration that) the corresponding receive sonet poh processor block declares the ais-p defect condition. 1 ? configures the transmit sonet poh processor block to automatically transmit the rdi-p indicator whenever (and for the duration that) the corresponding receive sonet poh processor block declares the ais-p defect condition. note: the transmit sonet poh processor block will transmit the rdi-p indicator (in response to the receive sonet poh processor block declaring the ais-p defect condition) by setting the rdi-p bit- field (within each outbo und sts-1 spe) to the contents within the ?ais-p rdi-p code[2:0]? bit-fi elds within this register.
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 610 table 441: transmit sonet path ? serial port control register (address location= 0xn9cf) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 unused txpoh clock speed[4:0] r/o r/o r/o r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 - 4 unused r/o 3 - 0 txpoh_clock_s peed[7:0] r/w txpohclk output clock signal speed: these read/write bit-fields permit the user to specify the frequency of the ?txpohclk output clock signal. the formula that relates the contents of these register bits to the ?txpohclk? frequency is presented below. freq = 19.44 /[2 * (txpoh_clock_speed + 1) note: for sts-3/stm-1 applications, the frequency of the rxpohclk output signal must be in the range of 0.304mhz to 9.72mhz
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 611 1.12 ds3/e3 mapper block control block the register map for the ds3/e3 mapper block is pres ented in the table below. additionally, a detailed description of each of the ?ds3/e3 map per? block registers is presented below. in order to provide some orientation for the reader, an illustration of the functional block diagram for the XRT94L33, with the ?ds3/e3 mapper? block ?highlighted? is presented below in figure 9 figure 9: illustration of the functi onal block diagram of the XRT94L33 (whenever it has been configured to operate in the 3-channel ds3/sts-1 to sts-3 mode), with the ds3/e3 mapper block ?high-lighted?. ds3/e3 framer block ds3/e3 framer block rx sts-1 pointer justification block rx sts-1 pointer justification block rx sts-1 poh block rx sts-1 poh block tx sts-1 poh block tx sts-1 poh block tx sts-1 pointer justification block tx sts-1 pointer justification block tx sts-1 toh block tx sts-1 toh block rx sts-1 toh block rx sts-1 toh block ds3/e3 jitter attenuator block ds3/e3 jitter attenuator block ds3/e3 mapper block ds3/e3 mapper block tx sonet poh processor block tx sonet poh processor block tx sts-3 toh processor block tx sts-3 toh processor block sts-3 telecom bus block sts-3 telecom bus block tx/rx line i/f block (primary) tx/rx line i/f block (primary) tx/rx line i/f block (aps) tx/rx line i/f block (aps) clock synthesizer block clock synthesizer block channel 1 to channels 2 ? 3 microprocessor interface microprocessor interface jtag test port jtag test port rx sonet poh processor block rx sonet poh processor block rx sts-3 toh processor block rx sts-3 toh processor block from channels 2 ? 3 rx sts-3 toh processor block (primary) rx sts-3 toh processor block (primary)
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 612 ds3/e3 mapper block control registers table 442: ds3/e3 mapper block ? register address map a ddress l ocation r egister n ame d efault v alue 0xna00 ? 0xnb00 unused 0x00 0xnb01 mapper control register ? byte 2 0x00 0xnb02 mapper control register ? byte 1 0x03 0xnb03 mapper control register ? byte 0 0x80 0xnb04, 0xnb05 unused 0x00 0xnb06 receive mapper status register ? byte 1 0x03 0xnb07 receive mapper status register ? byte 0 0x00 0xnb08 ? 0xnb0a unused 0x00 0xnb0b receive mapper interrupt status register ? byte 0 0x00 0xnb0c ? 0xnb0e unused 0x00 0xnb0f receive mapper interrupt enable register ? byte 0 0x00 0xnb10 ? 0xnb12 unused 0x00 0xnb13 t3/e3 routing register 0x00 0xnb14 ? 0xnb16 reserved 0x00 0xnb17 jitter attenuator ? clock source routing register 0x00 0xnb18 ? 0xnbff reserved 0x00
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 613 1.12.1 ds3/e3 mapper block co ntrol register description table 443: mapper control register ? byte 2 (a ddress location= 0xnb01, where n ranges from 0x02 to 0x04) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 sts-1 poh pass thru sts-1 remote loop-back sts-1 local loop-back sts-1 toh insert loop-timing sts-3 poh pass thru receive (ingress) sts-1 enable transmit (egress) sts-1 enable r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 sts-1 poh pass thru r/w sts-1 poh (path overhead) pass-thru: this read/write bit-field permits the user to configure the transmit sts- 1 circuitry (within this particular channel) to operate in the ?sts-1 poh pass-thru? mode. if the user confi gures the channel to operate in the ?sts-1 poh pass-thru? mode, then the transmit (or egress direction) sts-1 circuitry will use the ?upstream? receive sonet poh processor block as the source for the poh byte s within each outbound sts-1 spe. in the ?sts-1 poh pass thru? mode, the transmit sts-1 poh processor block will be disabled and will not assume the responsibility for computing and inserting the poh byte values into the ?poh byte-positions? within the ?transmit (or egress direction) sts-1 spes. the poh bytes (within these sts-1 spes) will pass from the receive sonet poh processor block to the transmit sts-1 toh processor block without modification. if the user does not configure the tr ansmit sts-1 circuitry to operate in the ?sts-1 poh pass-thru? mode, then the poh bytes (within these sts- 1 spes) will undergo ?modification? as they pass from the receive sonet poh processor block to the transmit sts-1 toh processor block (via the transmit sts-1 poh processor block). 0 ? configures the transmit sts-1 circ uitry to not operate in the ?sts-1 poh pass-thru? mode. 1 ? configures the transmit sts-1 circ uitry to operate in the ?sts-1 poh pass-thru? mode. notes: 1. the ?sts-1 poh pass-thru? mode will be disabled, if the channel is configured to operate in the loop-timing mode. 2. the ?sts-1 poh pass-thru? mode is very useful for those applications in which the XRT94L33 device is han dling sts-1 data-stream that is transporting vt-mapped t1/e1 data-streams (in which it is imperative that the user retain the value of the h4 byte). 3. this register bit is only active if a given channel (on the ?slow-speed? side of the XRT94L33 device) has been configured to operate in the sts-1 mode. this register bit is not active if a given channel has been configured to operate in the ds3/e3 mode. 6 sts-1 remote loop-back r/w sts-1 remote loop-back operation: this read/write bit-field permits t he user to configure the channel to operate in the remote loop-back mode. 0 ? no loop-back mode 1 ? remote loop-back mode
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 614 in this case, the receive (ingress) sts-1 signal will be looped back out into the transmit (egress) sts-1 signal path. 5 sts-1 local loop-back r/w sts-1 local loop-back operation: this read/write bit-field permits t he user to configure the channel to operate in the local loop-back mode. 0 ? no loop-back mode. 1 ? local loop-back mode in this case, the transmit (egress) sts-1 signal will be looped back into the receive (ingress) sts-1 signal path. 4 sts-1 toh insert r/w sts-1 toh (transport overhead) insert: this read/write bit-field permits the user to configure each transmit sts-1 toh processor block to acc ept its toh data from the ?txpoh? input pins. 0 ? disables this feature. 1 ? enables this feature. note: the user must also configure the transmit section of a given channel to operate in the sts-1 mode, by setting bit 0 (transmit egress sts-1 enable) to ?1?. 3 loop-timing r/w loop-timing mode: this read/write bit-field permits the user to configure the transmit sts- 1 circuitry (e.g., the transmit sts-1 poh and toh processor blocks) to operate in the loop-timing mode. if the user opts to configure the transmit sts-1 circuitry (within this particular channel) to operate in the loop-timing mode, then the transmit sts-1 circuitry will use the recovered clock signal (within the corresponding receive sts-1 toh and poh processor blocks) as its timing reference. if the user opts to not configure the transmit sts-1 circuitry into the ?loop-timing? mode, then the transmit sts-1 circuitry will use a 51.84mhz clock signal (that is ultimately der ived from the 155.52mhz or 19.44mhz clock signal, that is being applied to the receive sts-3 pecl interface or receive sts-3 telecom bus interface block) as its timing source 0 ? configures the transmit sts-1 toh and poh processor blocks to operate in the ?local-timing? mode. 1 ? configures the transmit sts-1 toh and poh processor blocks to operate in the loop-timing mode 2 sts-3 poh pass-thru r/w sts-3 poh (path overhead) pass-thru: this read/write bit-field permits the user to configure the transmit sts- 3 circuitry (within this particular channel) to operate in the ?sts-3 poh pass-thru? mode. if the user confi gures the channel to operate in the ?sts-3 poh pass-thru? mode, then t he transmit sts-3 circuitry will use the (upstream) receive sts-1 poh processor block as the source for the poh bytes within each outbound sts-1 spe. in the ?sts-3 poh pass thru? mode, the transmit sonet poh processor block will be disabled and will not assume the responsibility for computing and iinserting the poh byte values into the ?poh byte-positions? within these ?transmit sts- 3 toh processor-block desitined? sts-1 spes. the poh bytes (within these sts-1 spes) will pass from t he receive sts-1 poh processor block to the transmit sts-3 toh processor block without modification. if the user does not configure the tr ansmit sts-3 circuitry to operate in the ?sts-3 poh pass-thru? mode, then the poh bytes (within these sts- 1 spes) will undergo ?modification? as they pass from the receive sts-1 poh processor block to the transmit sts-3 toh processor block ( via the
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 615 transmit sonet poh processor block). 0 ? configures the transmit sts-3 circ uitry to not operate in the ?sts-3 poh pass-thru? mode. 1 ? configures the transmit sts-3 circ uitry to operate in the ?sts-3 poh pass-thru? mode. notes: 1. the ?sts-3 poh pass-thru? mode is very useful for those applications in which the XRT94L33 device is handling sts-1 data-stream that is transporting vt-mapped t1/e1 data-streams (in which it is imperative that t he user retain the value of the h4 byte). 2. this register bit is only active if a given channel (on the ?slow- speed? side of the XRT94L33 device) has been configured to operate in the sts-1 mode. this re gister bit is not active if a given channel has been configured to operate in the ds3/e3 mode. 1 receive (ingress) sts-1 enable r/w receive (ingress) sts-1 enable: this read/write bit-field permits the user to configure the ingress path (of the channel) to operate in either the sts-1 mode, or in the ds3/e3 mode. 0 ? ingress direction of channel wi ll operate in the ds3/e3 mode. 1 ? ingress direction of channel will operate in the sts-1 mode. 0 transmit (egress) sts-1 enable r/w transmit (egress) sts-1 enable: this read/write bit-field permits the user to configure the egress path (of the channel) to operate in either the sts-1 mode, or in the ds3/e3 mode. 0 ? egress direction of channel will operate in the ds3/e3 mode 1 ? egress direction of channel will operate in the sts-1 mode.
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 616 table 444: mapper control register ? byte 1 (address location= 0xnb02) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 unused sts-1 clk_in invert (ingress direction) sts-1 clk_out invert (egress direction) default r default o r/o r/o r/o r/o r/w r/w r/w r/w 0 0 0 0 0 1 1 1 b it n umber n ame t ype d escription 7 - 4 unused r/o 3 sts-1 clk_in invert (ingress direction) r/w sts-1 clk_in invert (ingress direction): this read/write bit-field permits the user to configure the ds3/e3 mapper block (of channel n), within the XRT94L33; to sample and latch the ?rxds3pos_n? input pins (pin b14. c 21. ag15) upon either the rising or falling edge of ?rxds3lineclk_n? (pin d14, a24, af14). 0 ? ?rxds3pos_n? is sampled upon the falling edge of the ?rxds3lineclk_n?. 1 ? ?rxds3pos_n? is sampled upon the rising edge of the ?rxds3lineclk_n? 2 sts-1 clk_out invert (egress direction) r/w sts-1 clk_out invert (egress direction): this read/write bit-field permits the user to configure the ds3/e3 mapper block (of channel n), within the XRT94L33, to update the ?txds3pos_n? output pins (pin b18, g 24, ag9) upon either the rising or falling edge of the ?txds3lineclk _n? (pin c17, e25, af10) 0 ? ?txds3pos_n? is updated upon the rising edge of ?txds3lineclk_n?. the user should insure that the liu ic will sample the output data upon the falling edge of the ?txds3lineclk_n? 1 ? ?txds3pos_n? is updated upon the falling edge of ?txds3lineclk_n?. the user should insure that the liu ic will sample the output data upon the rising edge of ?txds3lineclk_n? note: this bit-field is only active if the ds3/e3 mapper block has been configured to operate in the egress path. 1 default r r/w default r value: when a ds3 signal is mapped into a sts-1 spe (in sonet) or a vc-3 (in sdh), there are numerous bits that ar e also stuffed into the sts-1 spe or the vc-3 in order to accommodate the frequency differences between ds3 and an sts-1 spe or an sdh vc-3. one such bit is referred to as an ?r ? bit. currently, the standards do not define a ?use? for these bits. hence, this bit can be used as a proprietary communication link between two pieces of equipment. this read/write bit-field permits the us er to set the value for the ?r? bits in the outbound sts-1 spe or sdh vc-3. note: the XRT94L33 includes a corresponding ?read-only? register bit, in which one can obtain the value for the ?r? bits in the incoming sts-1 spe or sdh vc-3. th is register bit is located in bit 1 (received r) within the ?receive mapper status register ? byte 1( address location= 0xnb06).
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 617 0 default o r/w default o value: when a ds3 signal is mapped into a sts-1 spe (in sonet) or a vc-3 (in sdh), there are numerous bits that ar e also stuffed into the sts-1 spe or the vc-3 in order to accommodate the frequency differences between ds3 and an sts-1 spe or an sdh vc-3. one such bit, is referred to as an ?o? bit. currently, the standards do not define a ?use? for these bits. hence, this bit can be used as a proprietary communication link between two pieces of equipment. this read/write bit-field permits the us er to set the value for the ?o? bits in the outbound sts-1 spe or sdh vc-3. note: the XRT94L33 includes a corresponding ?read-only? register bit, in which one can obtain the value for the ?o? bits in the incoming sts-1 spe or sdh vc-3. th is register bit is located in bit 0 (received o) within the ?receive mapper status register ? byte 1 (address location= 0xnb06).
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 618 table 445: mapper control register ? byte 0 (address location= 0xnb03) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 ja reset* unused level 2 monitor unused jitter attenuator enable r/w r/o r/o r/o r/o r/w r/o r/w 1 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 ja_reset* r/w ja fifo reset: a ?1? to ?0? transition, within this bit-field commands the fifo_read and fifo_write pointers (within the jitter attenuator fifo) to be reset to their default positions. note: after the user has commanded t he reset to the jitter attenuator circuit, the user must set this bit-field back to ?1? in order to permit proper operation. 6 - 3 unused r/o 2 level 2 monitor r/w level 2 monitor enable: this read/write bit-field permits the user to enable the ?level 2? feature, within the ds3/e3 mapper block. if t he user enables this feature, then the channel will perform ?performance moni toring? of the ds3 data, being carried by the receive (or ingress) sts-1 signal. the location of this monitoring will be between the receive sts-1 toh processor block and the receive sts-1 poh processor block. this sts-1 signal will still proceed onto the ?recei ve sts-1 poh processor? block, intact. 0 ? disables the level 2 monitor feature. 1 ? enables the level 2 monitor feature. note: this feature is only usef ul if the ingress sts-1 signal is carrying a ds3 signal. this feature would not be of any use if the sts-1 signal were carrying vt-mapped ds1 or e1 signals, for instance. 1 unused r/o 0 jitter attenuator enable r/w jitter attenuator enable: these two read/write bit-fields permits the user to either enable or disable the jitter attenuator circuit within the ma pper block, as indicated below. 0 ? disables the jitter attenuator circuit. 1 ? enables the jitter attenuator circuit.
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 619 table 446: receive mapper status regist er ? byte 1 (address location= 0xnb06) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 unused received_r received_o r/o r/o r/o r/o r/o r/o r/o r/o 0 0 0 0 0 0 1 1 b it n umber n ame t ype d escription 7 - 2 unused r/o 1 received r r/w incoming ?r? value: when a ds3 signal is de-mapped from an sts-1 spe (in sonet) or a vc-3 (in sdh), there are numerous bits that were also stuffed into the sts-1 spe or the vc-3 in order to accommodate the frequency differences between ds3 and an sts-1 spe or an sdh vc-3. one such bit is referred to as an ?r? bi t. currently, the standards do not define a ?use? for these bits. hence, this bit can be used as a proprietary communication link between two pieces of equipment. this read-only bit-field contains the va lue of the ?r? bits within the most recently received sts-1 spe or sdh vc-3. note: the XRT94L33 includes a corresponding ?read/write? register bit, in which one can set the value for the ?r? bits, in the ?outbound? sts-1 spe or sdh vc-3. this register bit is located in bit 1 (default r) within the ?mapper control register ? byte 1? (address location= 0xnb02) 0 received o r/w incoming ?o? value: when a ds3 signal is de-mapped from an sts-1 spe (in sonet) or a vc-3 (in sdh), there are numerous bits that were also stuffed into the sts-1 spe or the vc-3 in order to accommodate the frequency differences between ds3 and an sts-1 spe or an sdh vc-3. one such bit is referred to as an ?o? bit. currently, the standards do not define a ?use? for these bits. hence, this bit can be used as a proprietary communication link between two pieces of equipment. this read-only bit-field contains the va lue of the ?o? bits within the most recently received sts-1 spe or sdh vc-3. note: the XRT94L33 includes a corresponding ?read/write? register bit, in which one can set the value for the ?r? bits, in the ?outbound? sts-1 spe or sdh vc-3. this register bit is located in bit 1 (default r) within the ?mapper control register ? byte 1? (address location= 0xnb02)
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 620 table 447: receive mapper status regist er ? byte 0 (address location= 0xnb07) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 receive sts-1 overrun condition receive sts-1 underrun condition transmit sts-1 overrun condition transmit sts-1 underrun condition receive ds3/e3 overrun condition receive ds3/e3 underrun condition transmit ds3/e3 overrun condition transmit ds3/e3 underrun condition r/o r/o r/o r/o r/o r/o r/o r/o 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 receive sts-1 overrun indicator r/o receive sts-1 overrun indicator: this read-only bit-field indicates whether or not the channel is declaring a ?receive sts-1 overrun? condition. a ?receive sts-1 overrun? condition will only occur if data is arriving into the receive sts-1 poh processor blocks at a much faster rate, than that being removed, by the transmit sonet poh processor block. 0 ? indicates that the channel is not declaring the ?receive sts-1 overrun? condition. 1 ? indicates that the channel is currently declaring the ?receive sts-1 overrun? condition. note: 1. there will invariably be a timing mismat ch between the clock signal driving the receive sts-1 poh processor block (e.g., the recovered clock signal from the liu ic) and the transmit sonet poh processor block (which is derived from the clock synthesizer block). minor timing differences are easily handled by pointer adjustments. 2. this condition will only occur if ther e is a major timing mismatch between the two clock signals. this condition can be viewed as an indicator of a fault condition within the source(s) of one of these clock signals. 6 receive sts-1 underrun indicator r/o receive sts-1 underrun indicator: this read-only bit-field indicates whether or not the channel is declaring a ?receive sts-1 underrun? condition. a ?receive sts-1 underrun? condition will only occur if data is arriving into the receive sts-1 poh processor blocks at a much slower rate, than that being removed, by the transmit sonet poh processor block. 0 ? indicates that the channel is not declaring the ?receive sts-1 underrun? condition. 1 ? indicates that the channel is currently declaring the ?receive sts-1 underrun? condition. note: 1. there will invariably be a timing mismat ch between the clock signal driving the receive sts-1 poh processor block (e.g., the recovered clock signal from the liu ic) and the transmit sonet poh processor block (which is derived from the clock synthesizer block). minor timing differences are easily handled by pointer adjustments. 2. this condition will only occur if ther e is a major timing mismatch between the two clock signals. this condition can be viewed as an indicator of a fault condition within the source(s) of one of these clock signals .
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 621 5 transmit sts-1 overrun indicator r/o transmit sts-1 overrun indicator: this read-only bit-field indicates whether or not the channel is declaring a ?transmit sts-1 overrun? condition. a ?transmit sts-1 overrun? condition will only occur if data is arriving into the receive sonet poh processor blocks at a much faster rate , than that being removed, by the transmit sts-1 poh processor block. 0 ? indicates that the channel is not declaring the ?transmit sts-1 overrun? condition. 1 ? indicates that the channel is cu rrently declaring the ?transmit sts-1 overrun? condition. note: 1. in most applications of the XRT94L33 there will typically not be a timing mismatch between the clock signal driv ing the transmit sts-1 poh processor block and the receive sonet poh proce ssor block (each of these blocks are typically driving by a clock signal which is derived from the receive sts-3 clock signal). however, timing differences can exist if the channel is configured to operate in the loop-timing mode. 2. minor timing differences are easily handled by pointer adjustments. 3. this condition will only occur if ther e is a major timing mismatch between the two clock signals. this condition can be viewed as an indicator of a fault condition within the source(s) of one of these clock signals . 4 transmit sts-1 underrun indicator r/o transmit sts-1 underrun indicator: this read-only bit-field indicates whether or not the channel is declaring a ?transmit sts-1 underrun? condition. a ?transmit sts-1 underrun? condition will only occur if data is arriving into the receive sonet poh processor blocks at a much slower rate, than that being removed, by the transmit sts-1 poh processor block. 0 ? indicates that the channel is not declaring the ?transmit sts-1 underrun? condition. 1 ? indicates that the channel is cu rrently declaring the ?transmit sts-1 underrun? condition. note: 1. in most applications of the XRT94L33 there will typically not be a timing mismatch between the clock signal driv ing the transmit sts-1 poh processor block and the receive sonet poh proce ssor block (each of these blocks are typically driving by a clock signal which is derived from the receive sts-3 clock signal). however, timing differences can exist if the channel is configured to operate in the loop-timing mode. 2. minor timing differences are easily handled by pointer adjustments. 3. this condition will only occur if ther e is a major timing mismatch between the two clock signals. this condition can be viewed as an indicator of a fault condition within the source(s) of one of these clock signals. 3 receive ds3/e3 overrun indicator r/o receive ds3/e3 overrun indicator: this read-only bit-field indicates whether or not the channel is declaring a ?receive ds3/e3 overrun? condition. a ?receive ds3/e3 overrun? condition will only occur if data is arriving into the ds3/e3 framer block ( in the in g ress direction ) at a much faster rate, than that
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 622 being removed, by the transmit sonet poh processor block. 0 ? indicates that the channel is not declaring the ?receive ds3/e3 overrun? condition. 1 ? indicates that the channel is curr ently declaring the ?receive ds3/e3 overrun? condition. note: 1. there will invariably be a timing mismat ch between the clock signal driving the ingress direction of the ds3/e3 framer block (e.g., the recovered clock signal from the liu ic) and the transmit sonet poh processor block (which is derived from the clock synthesizer block). minor timing differences are easily handled by pointer adjustments. 2. this condition will only occur if ther e is a major timing mismatch between the two clock signals. this condition can be viewed as an indicator of a fault condition within the source(s) of one of these clock signals. 2 receive ds3/e3 underrun indicator r/o receive ds3/e3 underrun indicator: this read-only bit-field indicates whether or not the channel is declaring a ?receive ds3/e3 underrun? condition. a ?receive ds3/e3 underrun? condition will only occur if data is arriving into the ds3/e3 framer block (in the ingress direction) at a much slower rate, than that being removed, by the transmit sonet poh processor block. 0 ? indicates that the channel is not declaring the ?receive ds3/e3 underrun? condition. 1 ? indicates that the channel is curr ently declaring the ?receive ds3/e3 underrun? condition. note: 1. there will invariably be a timing mismat ch between the clock signal driving the ingress direction of the ds3/e3 framer block (e.g., the recovered clock signal from the liu ic) and the transmit sonet poh processor block (which is derived from the clock synthesizer block). minor timing differences are easily handled by pointer adjustments. 2. this condition will only occur if ther e is a major timing mismatch between the two clock signals. this condition can be viewed as an indicator of a fault condition within the source(s) of one of these clock signals. 1 transmit ds3/e3 overrun indicator r/o transmit ds3/e3 overrun indicator: this read-only bit-field indicates whether or not the channel is declaring a ?transmit ds3/e3 overrun? condition. a ?transmit ds3/e3 overrun? condition will only occur if data is arriving into the receive sonet poh processor blocks at a much faster rate , than that being removed, by the ds3/e3 framer block. 0 ? indicates that the channel is not dec laring the ?transmit ds3/e3 overrun? condition. 1 ? indicates that the channel is curre ntly declaring the ?transmit ds3/e3 overrun? condition. note: 1. in most applications of the XRT94L33 there will typically not be a timing mismatch between the clock signal drivin g the ds3/e3 framer block (in the egress direction) and the receive sone t poh processor block (each of these blocks are typically driving by a clock si gnal which is derived from the receive sts-3 clock signal). however, timin g d i fferences can exist if the channel is confi g ured to o p erate in
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 623 the loop-timing mode. 2. minor timing differences are easily handled by pointer adjustments. 3. this condition will only occur if ther e is a major timing mismatch between the two clock signals. this condition can be viewed as an indicator of a fault condition within the source(s) of one of these clock signals. 0 transmit ds3/e3 underrun indicator r/o transmit ds3/e3 underrun indicator: this read-only bit-field indicates whether or not the channel is declaring a ?transmit ds3/e3 underrun? condition. a ?transmit ds3/e3 underrun? condition will only occur if data is arriving into the receive sonet poh processor blocks at a much slower rate, than that being removed, by the ds3/e3 framer block. 0 ? indicates that the channel is not dec laring the ?transmit ds3/e3 underrun? condition. 1 ? indicates that the channel is curre ntly declaring the ?transmit ds3/e3 underrun? condition. note: 1. in most applications of the xrt94l 33 there will typically not be a timing mismatch between the clock signal drivin g the ds3/e3 framer block (in the egress direction) and the receive sone t poh processor block (each of these blocks are typically driving by a clock si gnal which is derived from the receive sts-3 clock signal). however, timing differences can exist if the channel is configured to operate in the loop-timing mode. 2. minor timing differences are easily handled by pointer adjustments. 3. this condition will only occur if ther e is a major timing mismatch between the two clock signals. this condition can be viewed as an indicator of a fault condition within the source(s) of one of these clock signals.
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 624 table 448: receive mapper interrupt status re gister ? byte 0 (address location= 0xnb0b) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 rx sts-1 overrun interrupt status rx sts-1 underrun interrupt status tx sts-1 overrun interrupt status tx sts-1 underrun interrupt status rx overrun interrupt status rx underrun interrupt status tx overrun interrupt status tx underrun interrupt status rur rur rur rur rur rur rur rur 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 receive sts-1 overrun interrupt status rur receive sts-1 overrun interrupt status: this reset-upon-read bit-field indicates whether or not the ?receive sts-1 overrun? interrupt has occurred si nce the last read of this register. if this interrupt is enabled, then the channel will generate this interrupt anytime it declares a ?receive sts-1 overrun? condition. 0 ? indicates that the ?receive sts-1 overrun? interrupt has not occurred since the last read of this register. 1 ? indicates that the ?receive sts- 1 overrun? interrupt has occurred since the last read of this register. note: the current status of the ?receive sts-1 overrun? condition can be obtained by reading the st ate of bit 7 (receive sts-1 overrun condition) within the ?receive mapper status register ?byte 0 (address location= 0xnb07). 6 receive sts-1 underrun interrupt status rur receive sts-1 underrun interrupt status: this reset-upon-read bit-field indicates whether or not the ?receive sts-1 underrun? interrupt has occu rred since the last read of this register. if this interrupt is enabled, then the channel will generate this interrupt anytime it declares a ?receive sts-1 underrun? condition. 0 ? indicates that the ?receive sts-1 underrun? interrupt has not occurred since the last read of this register. 1 ? indicates that the ?receive sts-1 underrun? interrupt has occurred since the last read of this register. note: the current status of the ?rec eive sts-1 underrun? condition can be obtained by reading the st ate of bit 6 (receive sts-1 underrun condition) within the ?receive mapper status register ?byte 0 (address location= 0xnb07). 5 transmit sts-1 overrun interrupt status rur transmit sts-1 overrun interrupt status: this reset-upon-read bit-field indicates whether or not the ?transmit sts-1 overrun? interrupt has occurred si nce the last read of this register. if this interrupt is enabled, then the channel will generate this interrupt anytime it declares a ?transmi t sts-1 overrun? condition. 0 ? indicates that the ?transmit sts-1 overrun? interrupt has not occurred since the last read of this register. 1 ? indicates that the ?transmit st s-1 overrun? interrupt has occurred since the last read of this register. note: the current status of the ?transmit sts - 1 overrun? condition
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 625 can be obtained by reading the st ate of bit 5 (transmit sts-1 overrun condition) within the ?receive mapper status register ?byte 0 (address location= 0xnb07). 4 transmit sts-1 underrun interrupt status rur transmit sts-1 underrun interrupt status: this reset-upon-read bit-field indicates whether or not the ?transmit sts-1 underrun? interrupt has occu rred since the last read of this register. if this interrupt is enabled, then the channel will generate this interrupt anytime it declares a ?transmi t sts-1 underrun? condition. 0 ? indicates that the ?transmit sts-1 underrun? interrupt has not occurred since the last read of this register. 1 ? indicates that the ?transmit sts-1 underrun? interrupt has occurred since the last read of this register. note: the current status of the ?transmit sts-1 overrun? condition can be obtained by reading the st ate of bit 4 (transmit sts-1 underrun condition) within the ?receive mapper status register ?byte 0 (address location= 0xnb07). 3 receive ds3/e3 overrun interrupt status rur receive ds3/e3 overrun interrupt status: this reset-upon-read bit-field indicates whether or not the ?receive ds3/e3 overrun? interrupt has occurred since the last read of this register. if this interrupt is enabled, then the channel will generate this interrupt anytime it declares a ?receive ds3/e3 overrun? condition. 0 ? indicates that the ?receive ds 3/e3 overrun? interrupt has not occurred since the last read of this register. 1 ? indicates that the ?receive ds3/ e3 overrun? interrupt has occurred since the last read of this register. note: the current status of the ?receive ds3/e3 overrun? condition can be obtained by reading the state of bit 3 (receive ds3/e3 overrun condition) within the ?receive mapper status register ?byte 0 (address location= 0xnb07). 2 receive ds3/e3 underrun interrupt status rur receive ds3/e3 underrun interrupt status: this reset-upon-read bit-field indicates whether or not the ?receive ds3/e3 underrun? interrupt has occu rred since the last read of this register. if this interrupt is enabled, then the channel will generate this interrupt anytime it declares a ?receive ds3/e3 underrun? condition. 0 ? indicates that the ?receive ds 3/e3 underrun? interrupt has not occurred since the last read of this register. 1 ? indicates that the ?receive ds3/e3 underrun? interrupt has occurred since the last read of this register. note: the current status of the ?receive ds3/e3 underrun? condition can be obtained by reading the state of bit 2 (receive ds3/e3 underrun condition) within the ?receive mapper status register ?byte 0 (address location= 0xnb07). 1 transmit ds3/e3 overrun interrupt status rur transmit ds3/e3 overrun interrupt status: this reset-upon-read bit-field indicates whether or not the ?transmit ds3/e3 overrun? interrupt has occurred since the last read of this register. if this interru p t is enabled, then the channel will g enerate this interru p t
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 626 anytime it declares a ?transmit ds3/e3 overrun? condition. 0 ? indicates that the ?transmit ds 3/e3 overrun? interrupt has not occurred since the last read of this register. 1 ? indicates that the ?transmit ds3/e3 overrun? interrupt has occurred since the last read of this register. note: the current status of the ?transmit ds3/e3 overrun? condition can be obtained by reading the state of bit 1 (transmit ds3/e3 overrun condition) within the ?receive mapper status register ?byte 0 (address location= 0xnb07). 0 transmit ds3/e3 underrun interrupt status rur transmit ds3/e3 underrun interrupt status: this reset-upon-read bit-field indicates whether or not the ?transmit ds3/e3 underrun? interrupt has occu rred since the last read of this register. if this interrupt is enabled, then the channel will generate this interrupt anytime it declares a ?transmit ds3/e3 underrun? condition. 0 ? indicates that the ?transmit ds 3/e3 underrun? interrupt has not occurred since the last read of this register. 1 ? indicates that the ?transmit ds3/e3 underrun? interrupt has occurred since the last read of this register. note: the current status of the ?transmit ds3/e3 overrun? condition can be obtained by reading the state of bit 0 (transmit ds3/e3 underrun condition) within the ?receive mapper status register ?byte 0 (address location= 0xnb07).
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 627 table 449: receive mapper interrupt enable register ? byte 0 (address location= 0xnb0f) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 receive sts-1 overrun interrupt enable receive sts-1 underrun interrupt enable transmit sts-1 overrun interrupt enable transmit sts-1 underrun interrupt enable receive overrun interrupt enable receive underrun interrupt enable transmit overrun interrupt enable transmit underrun interrupt enable r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 receive sts-1 overrun interrupt enable r/w receive sts-1 overrun interrupt enable: this read/write bit-field permits the user to either enable or disable the ?receive sts-1 overrun? interrupt. if this interrupt is enabled, then the channel will generate an interrupt if the ?receive sts-1 overrun? condition is declared. 0 ? disables this interrupt. 1 ? enables this interrupt. 6 receive sts-1 underrun interrupt enable r/w receive sts-1 underrun interrupt enable: this read/write bit-field permits the user to either enable or disable the ?receive sts-1 underrun? interrupt. if this interrupt is enabled, then the channel will generate an interrupt if the ?receive sts-1 underru n? condition is declared. 0 ? disables this interrupt. 1 ? enables this interrupt. 5 transmit sts-1 overrun interrupt enable r/w transmit sts-1 overrun interrupt enable: this read/write bit-field permits the user to either enable or disable the ?transmit sts-1 overrun? interrupt. if this interrupt is enabled, then the channel will generate an interrupt if the ?transmit sts-1 overr un? condition is declared. 0 ? disables this interrupt. 1 ? enables this interrupt. 4 transmit sts-1 underrun interrupt enable r/w transmit sts-1 underrun interrupt enable: this read/write bit-field permits the user to either enable or disable the ?transmit sts-1 underrun? interrupt. if this interrupt is enabled, then the channel will generate an interrupt if the ?transmit sts-1 underr un? condition is declared. 0 ? disables this interrupt. 1 ? enables this interrupt. 3 receive ds3/e3 overrun interrupt enable r/w receive ds3/e3 overrun interrupt enable: this read/write bit-field permits the user to either enable or disable the ?receive ds3/e3 overrun? interrupt. if this interrupt is enabled, then the channel will generate an interrupt if the ?receive ds3/e3 ove rrun? condition is declared.
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 628 0 ? disables this interrupt. 1 ? enables this interrupt. 2 receive ds3/e3 underrun interrupt enable r/w receive ds3/e3 underrun interrupt enable: this read/write bit-field permits the user to either enable or disable the ?receive ds3/e3 underrun? interrupt. if this interrupt is enabled, then the channel will generate an interrupt if the ?receive ds3/e3 under run? condition is declared. 0 ? disables this interrupt. 1 ? enables this interrupt. 1 transmit ds3/e3 overrun interrupt enable r/w transmit ds3/e3 overrun interrupt enable: this read/write bit-field permits the user to either enable or disable the ?transmit ds3/e3 overrun? interrupt. if this interrupt is enabled, then the channel will generate an interrupt if the ?transmit ds3/e3 ove rrun? condition is declared. 0 ? disables this interrupt. 1 ? enables this interrupt. 0 transmit ds3/e3 underrun interrupt enable r/w transmit ds3/e3 underrun interrupt enable: this read/write bit-field permits the user to either enable or disable the ?transmit ds3/e3 underrun? interrupt. if this interrupt is enabled, then the channel will generate an interrupt if the ?transmit ds3/e3 unde rrun? condition is declared. 0 ? disables this interrupt. 1 ? enables this interrupt.
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 629 table 450: mapper control register ? t3/e3 rout ing register byte (address location= 0xnb13) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 txsrc[1:0] txdes[1:0] rxsrc[1:0] rxdes[1:0] r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 table 146: mapper control register ? jitter a ttenuator clock source control/routing? register (address location= 0xnb17, where n ranges in value from 0x02 to 0x04) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 unused ja source[1:0] r/o r/o r/o r/o r/o r/o r/w r/w 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 - 2 unused r/o 1 - 0 ja source[1:0] r/w jitter attenuator configuration/orientation: this read/write bit-field permits the user to configure the jitter attenuator to operate in either in the ingress direction, the egress direction or be by-passed altogether, as depicted below. ja source[1:0] resuting jitter attenuator configuration 00 by-passed 01 jitter attenuator is in egress direction 10 jitter attenuator is in ingress direction 11 do not use note: for most applications, we reco mmend that the user set these two bits to the value of ?[0, 1]?.
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 630 1.13 receive sts-1 toh and poh processor block the register map for the receive sts-1 toh and poh pr ocessor block is presented in the table below. additionally, a detailed description of each of the ?recei ve sts-1 toh and poh processor? block registers is presented below. in order to provide some orientation for the reader, an illustration of the functional block diagram for the XRT94L33, with the ?receive sts-1 toh and poh processor blocks ?highlighted? is presented below in figure 10 figure 10: illustration of the functional block diagram of the XRT94L33 (whenever it has been configured to operate in the 3-channel ds3/sts-1 to sts-3 mode), with the receive sts-1 toh and poh processor blocks ?high-lighted?. ds3/e3 framer block ds3/e3 framer block rx sts-1 pointer justification block rx sts-1 pointer justification block rx sts-1 poh block rx sts-1 poh block tx sts-1 poh block tx sts-1 poh block tx sts-1 pointer justification block tx sts-1 pointer justification block tx sts-1 toh block tx sts-1 toh block rx sts-1 toh block rx sts-1 toh block ds3/e3 jitter attenuator block ds3/e3 jitter attenuator block ds3/e3 mapper block ds3/e3 mapper block tx sonet poh processor block tx sonet poh processor block tx sts-3 toh processor block tx sts-3 toh processor block sts-3 telecom bus block sts-3 telecom bus block tx/rx line i/f block (primary) tx/rx line i/f block (primary) tx/rx line i/f block (aps) tx/rx line i/f block (aps) clock synthesizer block clock synthesizer block channel 1 to channels 2 ? 3 microprocessor interface microprocessor interface jtag test port jtag test port rx sonet poh processor block rx sonet poh processor block rx sts-3 toh processor block rx sts-3 toh processor block from channels 2 ? 3 rx sts-3 toh processor block (primary) rx sts-3 toh processor block (primary)
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 631 receive sts-1 toh and poh processor block register table 451: receive sts-1 toh and poh processor block control register address map a ddress l ocation r egister n ame d efault v alues 0xn000 ? 0xn102 reserved 0x00 0xn103 receive sts-1 transport control register ? byte 0 0x00 0xn104 ? 0xn105 reserved 0x00 0xn106 receive sts-1 transport status register ? byte 1 0x00 0xn107 receive sts-1 transport status register ? byte 0 0x02 0xn108 reserved 0x00 0xn109 receive sts-1 transport interrupt status register ? byte 2 0x00 0xn10a receive sts-1 transport interrupt status register ? byte 1 0x00 0xn10b receive sts-1 transport interrupt status register ? byte 0 0x00 0xn10c reserved 0x00 0xn10d receive sts-1 transport interrupt enable register ? byte 2 0x00 0xn10e receive sts-1 transport interrupt enable register ? byte 1 0x00 0xn10f receive sts-1 transport interrupt enable register ? byte 0 0x00 0xn110 receive sts-1 transport b1 byte error count ? byte 3 0x00 0xn111 receive sts-1 transport b1 byte error count ? byte 2 0x00 0xn112 receive sts-1 transport b1 byte error count ? byte 1 0x00 0xn113 receive sts-1 transport b1 byte error count ? byte 0 0x00 0xn114 receive sts-1 transport b2 byte error count ? byte 3 0x00 0xn115 receive sts-1 transport b2 byte error count ? byte 2 0x00 0xn116 receive sts-1 transport b2 byte error count ? byte 1 0x00 0xn117 receive sts-1 transport b2 byte error count ? byte 0 0x00 0xn118 receive sts-1 transport rei-l error count ? byte 3 0x00 0xn119 receive sts-1 transport rei-l error count ? byte 2 0x00 0xn11a receive sts-1 transport rei-l error count ? byte 1 0x00 0xn11b receive sts-1 transport rei-l error count ? byte 0 0x00 0xn11c reserved 0x00 0xn11d ? 0xn11e reserved 0x00 0xn11f receive sts-1 transport ? received k1 byte value register 0x00 0xn120 ? 0xn122 reserved 0x00 0xn123 receive sts-1 transport ? received k2 byte value register 0x00
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 632 a ddress l ocation r egister n ame d efault v alues 0xn124 ? 0xn126 reserved 0x00 0xn127 receive sts-1 transport ? received s1 byte value register 0x00 0xn128 ? 0xn12d reserved 0x00 0xn12e receive sts-1 transport ? los threshold value ? msb 0xff 0xn12f receive sts-1 transport ? los threshold value ? lsb 0xff 0xn130 reserved 0x00 0xn131 receive sts-1 transport ? receive sf set monitor interval ? byte 2 0x00 0xn132 receive sts-1 transport ? receive sf set monitor interval ? byte 1 0x00 0xn133 receive sts-1 transport ? receive sf set monitor interval ? byte 0 0x00 0xn134, 0xn135 reserved 0x00 0xn136 receive sts-1 transport ? receive sf set threshold ? byte 1 0x00 0xn137 receive sts-1 transport ? receive sf set threshold ? byte 0 0x00 0xn138 ? 0xn139 reserved 0x00 0xn13a receive sts-1 transport ? receive sf clear threshold ? byte 1 0x00 0xn13b receive sts-1 transport ? receive sf clear threshold ? byte 0 0x00 0xn13c reserved 0x00 0xn13d receive sts-1 transport ? receive sd set monitor interval ? byte 2 0x00 0xn13e receive sts-1 transport ? receive sd set monitor interval ? byte 1 0x00 0xn13f receive sts-1 transport ? receive sd set monitor interval ? byte 0 0x00 0xn140 ? 0xn141 reserved 0x00 0xn142 receive sts-1 transport ? receive sd set threshold ? byte 1 0x00 0xn143 receive sts-1 transport ? receive sd set threshold ? byte 0 0x00 0xn144, 0xn145 reserved 0x00 0x46 0xn146 receive sts-1 transport ? receive sd clear threshold ? byte 1 0x00 0xn147 receive sts-1 transport ? receive sd clear threshold ? byte 0 0x00 0xn14b ? 0xn14a reserved 0x00 0xn14b receive sts-1 transport ? force sef condition 0x00 0xn14c ? 0xn14e reserved 0x00 0xn14f receive sts-1 transport ? receive j0 byte trace buffer control register 0x00 0xn150 ? 0xn151 reserved 0xn152 receive sts-1 transport ? receive sd burst error count tolerance ? byte 1 0x00
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 633 a ddress l ocation r egister n ame d efault v alues 0xn153 receive sts-1 transport ? receive sd burst error count tolerance ? byte 0 0x00 0xn154, 0xn155 reserved 0x00 0xn156 receive sts-1 transport ? receive sf burst error count tolerance ? byte 1 0x00 0xn157 receive sts-1 transport ? receive sf burst error count tolerance ? byte 0 0x00 0xn158 reserved 0x00 0xn159 receive sts-1 transport ? receive sd clear monitor interval ? byte 2 0x00 0xn15a receive sts-1 transport ? receive sd clear monitor interval ? byte 1 0x00 0xn15b receive sts-1 transport ? receive sd clear monitor interval ? byte 0 0x00 0xn15c reserved 0x00 0xn15d receive sts-1 transport ? receive sf clear monitor interval ? byte 2 0x00 0xn15e receive sts-1 transport ? receive sf clear monitor interval ? byte 1 0x00 0xn15f receive sts-1 transport ? receive sf clear monitor interval ? byte 0 0x00 0xn160 ? 0xn162 reserved 0x00 0xn163 receive sts-1 transport ? auto ais control register 0x00 0xn164 ? 0xn16a reserved 0x00 0x6b 0xn16b receive sts-1 transport ? auto ais (in downstream sts-1s) control register 0x00 0x6c ? 0x82 0xn16c ? 0xn182 reserved 0x00 0xn183 receive sts-1 path ? control register ? byte 2 0x00 0xn184 - 0xn185 reserved 0x00 0xn186 receive sts-1 path ? control register ? byte 1 0xn187 receive sts-1 path ? status register ? byte 0 0x00 0xn188 reserved 0x00 0xn189 receive sts-1 path ? interrupt status register ? byte 2 0x00 0xn18a receive sts-1 path ? interrupt status register ? byte 1 0x00 0xn18b receive sts-1 path ? interrupt status register ? byte 0 0x00 0xn18c reserved 0x00 0xn18d receive sts-1 path ? interrupt enable register ? byte 2 0x00 0xn18e receive sts-1 path ? interrupt enable register ? byte 1 0x00 0xn18f receive sts-1 path ? interrupt enable register ? byte 0 0x00 0xn190 ? 0xn192 reserved 0x00 0xn193 receive sts-1 path ? sonet receive rdi-p register 0x00
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 634 a ddress l ocation r egister n ame d efault v alues 0xn194, 0xn195 reserved 0x00 0xn196 receive sts-1 path ? received path label value (c2 byte) register 0x00 0xn197 receive sts-1 path ? expected path label value (c2 byte) register 0x00 0xn198 receive sts-1 path ? b3 error count register ? byte 3 0x00 0xn199 receive sts-1 path ? b3 error count register ? byte 2 0x00 0xn19a receive sts-1 path ? b3 error count register ? byte 1 0x00 0xn19b receive sts-1 path ? b3 error count register ? byte 0 0x00 0xn19c receive sts-1 path ? rei-p error count register ? byte 3 0x00 0xn19d receive sts-1 path ? rei-p error count register ? byte 2 0x00 0xn19e receive sts-1 path ? rei-p error count register ? byte 1 0x00 0xn19f receive sts-1 path ? rei-p error count register ? byte 0 0x00 0xn1a0 ? 0xn1a5 reserved 0x00 0xn1a6 receive sts-1 path ? pointer value register ? byte 1 0x00 0xn1a7 receive sts-1 path ? pointer value register ? byte 0 0x00 0xn1a8 ? 0xn1ba reserved 0x00 0xn1bb receive sts-1 path ? auto ais control register 0x00 0xn1bc ? 0xn1be reserved 0x00 0xn1bf receive sts-1 path ? serial port control register 0x00 0xn1c0 ? 0xn1c2 reserved 0x00 0xn1c3 receive sts-1 path ? sonet receive auto alarm register ? byte 0 0x00 0xn1c4 ? 0xn1d2 reserved 0xn1d3 receive sts-1 path ? receive j1 byte capture register 0x00 0xn1c4 ? 0xn1c6 reserved 0x00 0xn1d7 receive sts-1 path ? receive b3 byte capture register 0x00 0xn1d8 ? 0xn1da reserved 0x00 0xn1db receive sts-1 path ? receive c2 byte capture register 0x00 0xn1dc ?0xn1de reserved 0x00 0xn1df receive sts-1 path ? receive g1 byte capture register 0x00 0xn1e0 ? 0xn1e2 reserved 0x00 0xn1e3 receive sts-1 path ? receive f2 byte capture register 0x00 0xn1e4 ? 0xn1e6 reserved 0x00 0xn1e7 receive sts-1 path ? receive h4 byte capture register 0x00
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 635 a ddress l ocation r egister n ame d efault v alues 0xn1e8 ? 0xn1ea reserved 0x00 0xn1eb receive sts-1 path ? receive z3 byte capture register 0x00 0xn1ec ? 0xn1ee reserved 0x00 0xn1ef receive sts-1 path ? receive z4 (k3) byte capture register 0x00 0xn1f0 ? 0xn1f2 reserved 0x00 0xn1f3 receive sts-1 path ? receive z5 byte capture register 0x00 0xn1f6 ? 0xn1ff reserved 0x00
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 636 1.13.1 receive sts-1 toh and poh pr ocessor block register description table 452: receive sts-1 transport control register ? byte 0 (address location = 0xn103, where n ranges in value from 0x05 to 0x07) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 unused sf defect condition detect enable sd defect condition detect enable descramble disable unused rei-l error type b2 error type b1 error type r/o r/w r/w r/w r/o r/w r/w r/w 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 unused r/o 6 sf defect condition detect enable r/w signal failure (sf) defect condition detect enable: this read/write bit-field permits the user to enable or disable sf defect detection and declaration by the receive sts-1 toh processor block. 0 ? configures the receive sts-1 toh processor block to not declare nor clear the sf defect condition per the ?user-specified sf defect declaration and clearance? criteria. 1 ? configures the receive sts-1 toh processor block to declare and clear the sf defect condition per the ?user-specified sf defect declaration and clearance? criteria. 5 sd defect condition detect enable r/w signal degrade (sd) defect condition detect enable: this read/write bit-field permits the user to enable or disable sd detection and declaration by the receive sts-1 toh processor block. 0 ? configures the receive sts-1 toh processor block to not declare nor clear the sd defect condition per the ?user-specified sd defect declaration and clearance? criteria. 1 ? configures the receive sts-1 toh processor block to declare and clear the sd defect condition per the ?use r-specified sd defect declaration and clearance? criteria. 4 descramble disable r/w de-scramble disable: this read/write bit-field permits the user to either enable or disable de- scrambling by the receive sts-1 toh processor block, associated with channel n. 0 ? de-scrambling is enabled. 1 ? de-scrambling is disabled. 3 unused r/o 2 rei-l error type r/w rei-l error type: this read/write bit-field permits the user to specify how the receive sts- 1 toh processor block will count (or tally) rei-l events, for performance monitoring purposes. the user can configure the receive sts-1 toh processor block to increment rei-l events on either a ?per-bit? or ?per-frame? basis. if the user configures the receive sts-1 toh processor block to increment rei-l events on a ?per-bit? basis, then it will incrememt the ?receive sts-1 transport rei-l error co unt? register by the value of the lower nibble within the m0/m1 byte of the incoming sts-1 data-stream.
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 637 if the user configures the receive st s-1 toh processor block to increment rei-l events on a ?per-frame? basis, then it will increment the ?receive sts- 1 transport rei-l error count? register each time it receives an sts-1 frame, in which the lower nibble of t he m0/m1 byte is set to a ?non-zero? value. 0 ? configures the receive sts-1 toh processor block to count or tally rei-l events on a per-bit basis. 1 ? configures the receive sts-1 toh processor block to count or tally rei-l events on a per-frame basis. 1 b2 error type r/w b2 error type: this read/write bit-field permits the user to specify how the ?receive sts-1 toh processor block will count (or tally) b2 byte errors, for performance monitoring purposes. the user can configure the receive sts- 1 toh processor block to increment b2 byte errors on either a ?per-bit? or a ?per-frame? basis. if the user confi gures the receive sts-1 toh processor block to increment b2 byte errors on a ?per-bit? basis, then it will increment the ?receive transport b2 byte error co unt? register by the number of bits (within the b2 byte valu e) that is in error. if the user configures the receive st s-1 toh processor block to increment b2 byte errors on a ?per-frame? basis, then it will increment the ?receive transport b2 byte error count? register each time it receives an sts-1 frame that contains an erred b2 byte. 0 ? configures the receive sts-1 toh processor block to count b2 byte errors on a ?per-bit? basis. 1 ? configures the receive sts-1 toh processor block to count b2 byte errors on a ?per-frame? basis. 0 b1 error type r/w b1 error type: this read/write bit-field permits the user to specify how the receive sts- 1 toh processor block will count (or tall y) b1 byte errors, for performance monitoring purposes. the user can configure the receive sts-1 toh processor block to increment b1 byte errors on either a ?per-bit? or ?per- frame? basis. if the user configures the receive sts-1 toh processor block to increment b1 byte errors on a ?per-bit? basis, then it will increment the ?receive transport b1 byte error count? register by the number of bits (within the b1 byte valu e) that is in error. if the user configures the receive st s-1 toh processor block to increment b1 byte errors on a ?per-frame? basis, then it will increment the ?receive transport b1 byte error count? register each time it receives an sts-1 frame that contains an erred b1 byte. 0 ? configures the receive sts-1 toh processor block to count b1 byte errors on a ?per-bit? basis. 1 ? configures the receive sts-1 toh processor block to count b1 byte errors on a ?per-frame? basis.
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 638 table 453: receive sts-1 transport status register ? byte 1 (address location= 0xn106, where n ranges in value from 0x05 to 0x07) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 unused section trace message (j0) mismatch defect declared section trace message (j0) unstable defect declared ais-l defect declared r/o r/o r/o r/o r/o r/o r/o r/o 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 ? 3 unused r/o 2 section trace message mismatch defect declared r/o section trace message mismatch defect declared: this read-only bit-field indicates whether or not the receive sts-1 toh processor block is currently declaring the section trace mismatch defect condition. the receive sts-1 toh processor block will declare the section trace message mismatch defect condit ion, whenever it accepts a section trace message (via the j0 byte, within the incoming sts-1 data-stream) that differs from the ?expected section trace message?. 0 ? indicates that the section trace message mismatch defect condition is not currently being declared. 1 ? indicates that the section trace message mismatch defect condition is currently being declared. 1 section trace message unstable defect declared r/o section trace message unstable defect declared: this read-only bit-field indicates whether or not the receive sts-1 toh processor block is currently declaring the section trace message unstable defect condition. the receive sts- 1 toh processor block will declare the section trace message unstable defect condition, whenever the ?section trace message unstable? counter reaches the value 8. the ?section trace message unstable? counter will be incremen ted for each time that it receives a section trace message that differs from the ?expected section trace message?. the ?section trace message unstable? counter is cleared to ?0? whenever the receive sts-3 toh processor block has received a given section trace message 3 (or 5) consecutive times. note: receiving a given section trace message 3 (or 5) consecutive times also sets this bit-field to ?0?. 0 ? section trace message unstable defect condition is not currently being declared. 1 ? section trace message unstable defect condition is currently being declared. 0 ais-l defect detected r/o ais-l defect declared: this read-only bit-field indicates whether or not the receive sts-1 toh processor block is currently declaring th e ais-l (line ais) defect condition. the receive sts-1 toh processor bl ock will declare the ais-l defect condition within the incoming sts-1 data stream if bits 6, 7 and 8 (e.g., the least significant bits, within the k2 byte) are set to the value ?[1, 1, 1]? for five consecutive sts-1 frames. 0 ? indicates that the ais- l defect condition is not currently being declared.
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 639 1 ? indicates that the ais-l defect c ondition is currently being declared.
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 640 table 454: receive sts-1 transport status register ? byte 0 (address location = 0xn107, where n ranges in value from 0x05 to 0x07) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 rdi-l defect declared s1 byte unstable defect declared k1, k2 byte unstable defect declared sf defect declared sd defect declared lof defect detected sef defect declared los defect declared r/o r/o r/o r/o r/o r/o r/o r/o 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 rdi-l defect declared r/o rdi-l defect declared indicator: this read-only bit-field indicates whether or not the receive sts-1 toh processor block is detecting the rdi-l (line-remote defect indicator) defect condition, within the incoming sts-1 signal. the receive sts-1 toh processor block will declare the rdi-l defect condition whenever bits 6, 7 and 8 (e.g., the three least significant bits) of the k2 byte contains the ?1, 1, 0? pattern in 5 consecutive incoming sts-1 frames. 0 ? indicates that the rdi-l defect condition is not currently being declared. 1 ? indicates that the rdi-l defect c ondition is currently being declared. 6 s1 byte unstable defect declared r/o s1 byte unstable defect declared: this read-only bit-field indicates whether or not the receive sts-1 toh processor block is currently declaring the ?s1 byte unstable? defect condition. the receive sts-1 toh processor block will declare the ?s1 byte unstable? defect condition whenever the ?s1 byte unstable counter? reaches the value 32. the ?s1 byte unstable counter? is incremented for each time that the receive sts-1 toh processor block receives an sts-1 frame that contains an s1 byte that differs from the previously received s1 byte. the ?s1 byte unstable counter? is cleared to ?0? when the same s1 byte is received for 8 consecutive sts-1 frames. note: receiving a given s1 byte, in 8 consecutive sts-1 frames also sets this bit-field to ?0?. 0 ? indicates that the s1 byte unstab le defect condition is not currently being declared. 1 ? indicates that the s1 byte unstab le defect condition is currently being declared. 5 k1, k2 byte unstable defect declared r/o k1, k2 byte unstable defect declared: this read-only bit-field indicates whether or not the receive sts-1 toh processor block is currently declaring the ?k1, k2 byte unstable? defect condition. the receive sts-1 toh proc essor block will declare the ?k1, k2 byte unstable? defect condition whenever the receive sts-1 toh processor block fails to receive the same set of k1, k2 bytes, in 12 consecutive incoming sts-1 frames. the ?k1, k2 byte unstable? defect condition is cleared whenever the receive sts-1 toh processor block has received a given set of k1, k2 byte values within three consecutive incoming sts-1 frames. 0 ? indicates that the k1, k2 byte unst able defect condition is not currently being declared. 1 ? indicates that the k1, k2 byte unstabel defect condition is currently being declared.
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 641 4 sf defect declared r/o sf (signal failure) defect declared: this read-only bit-field indicates whether or not the receive sts-1 toh processor block is currently declaring the sf defect condition. the receive sts-1 toh processor block will declare the sf defect condition anytime it has determined that the number of b2 byte er rors (measured over a user-selected period of time) exceeds a certain ?user-s pecified b2 byte error? threshold. 0 ? indicates that the sf defect condi tion is not currently being declared. this bit is set to ?0? when the number of b2 byte errors (accumulated over a given interval of time) does not exceed t he ?sf defect declaration? threshold. 1 ? indicates that the sf defect c ondition is currently being declared. this bit is set to ?1? when the number of b2 errors (accumulated over a given interval of time) does exceed the ?s f defect declaration? threshold. 3 sd defect declared r/o sd (signal degrade) defect declared: this read-only bit-field indicates whether or not the receive sts-1 toh processor block is currently declaring the sd defect condition. the receive sts-1 toh processor block will declare the sd defect condition anytime it has determined that the number of b2 byte errors (measured over a user- selected period of time) exceeds a certain ?user-specified b2 byte error? threshold. 0 ? indicates that the sd defect condi tion is not currently being declared. this bit is set to ?0? when the number of b2 errors (accumulated over a given interval of time) does not exceed the ?sd declaration? threshold. 1 ? indicates that the sd defect c ondition is currently being declared. this bit is set to ?1? when the number of b2 errors (accumulated over a given interval of time) does exceed the ?s d defect declaration? threshold. 2 lof defect declared r/o lof (loss of frame) defect declared: this read-only bit-field indicates whether or not the receive sts-1 toh processor block is currently declaring the lof defect condition. the receive sts-1 toh processor block will declare the lof defect cond ition if it has been declaring the sef condition for 24 consecutive sts-1 frame periods. once the lof defect is declared, th en the receive sts-1 toh processor block will clear the lof defect if it has not been declaring the sef condition for 3ms (or 24 consecutive sts-1 frame periods). 0 ? indicates that the receive sts-1 toh processor block is not currently declaring the lof defect condition. 1 ? indicates that the receive sts- 1 toh processor block is currently declaring the lof defect condition. 1 sef defect declared r/o sef (severely errored frame) defect declared: this read-only bit-field indicates whether or not the receive sts-1 toh processor block is currently declaring the sef defect condition. the receive sts-1 toh processor block will declare the sef defect condition if it detects framing alignment byte errors in four consecutive sts-1 frames. once the receive toh processor block declares the sef defect condition, the receive sts-1 toh processor block will then clear the sef defect condition if it detects two consecutive sts-1 frames wi th un-erred framing alignment bytes. if the receive toh processor block declares the sef defect condition for 24 consecutive sts-1 frame peri ods, then it will declare the lof defect condition. 0 ? indicates that the receive sts-1 toh processor block is not currently declaring the sef defect condition. 1 ? indicates that the receive sts- 1 toh processor block is currently declaring the sef defect condition.
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 642 0 los defect declared r/o los (loss of signal) defect declared: this read-only bit-field indicates whether or not the receive sts-1 toh processor block is currently declaring the los (loss of signal) defect condition. the receive sts-1 toh processor block will declare the los defect condition if it detects ?los_t hreshold[15:0]? consecutive ?all zero? bytes in the incoming sts-1 data stream. note: the user can set the ?los_threshold[15:0]? value by writing the appropriate data into the ?receive sts-1 transport ? los threshold value? register (address location= 0xn12e and 0xn12f, where n ranges in value from 0x05 to 0x07). 0 ? indicates that the receive sts-1 toh processor block is not currently declaring the los defect condition. 1 ? indicates that the receive sts- 1 toh processor block is currently declaring the los defect condition.
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 643 table 455: receive sts-1 transport interrupt status register ? byte 2 (address location= 0xn109, where n ranges in value from 0x05 to 0x07) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 unused change of ais-l defect condition interrupt status change of rdi-l defect condition interrupt status r/o r/o r/o r/o r/o r/o rur rur 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 - 2 unused r/o 1 change of ais-l defect condition interrupt status rur change of ais-l (line ais) defect condition interrupt status: this reset-upon-read bit-field indicates whether or not the ?change of ais-l defect condition? interrupt has occurred since the last read of this register. the receive sts-1 toh processor block will generate this interrupt in response to either of the following occurrences. ? whenever the receive sts-1 toh processor block declares the ais-l defect condition. ? whenever the receive sts-1 toh processor block clears the ais-l defect condition. 0 ? indicates that the ?change of ais- l defect condition? interrupt has not occurred since the last read of this register. 1 ? indicates that the ?change of ais- l defect condition? interrupt has occurred since the last read of this register. note: the user can obtain the current state of the ais-l defect condition by reading the cont ents of bit 0 (ais-l defect declared) within the ?receive sts-1 transport status register ? byte 1? (address location= 0xn106, where n ranges in value from 0x05 to 0x07). 0 change of rdi-l defect condition interrupt status rur change of rdi-l (line - remote defect indicator) defect condition interrupt status: this reset-upon-read bit-field indicates whether or not the ?change of rdi-l defect condition? interrupt has occurred since the last read of this register. the receive sts-1 toh processor block will generate this interrupt in response to either of the following occurrences. ? whenever the receive sts-1 toh processor block declares the rdi-l defect condition. ? whenever the receive sts-1 toh processor block clears the rdi-l defect condition. 0 ? indicates that the ?change of rdi-l defect condition? interrupt has not occurred since the last read of this register. 1 ? indicates that the ?change of rdi-l defect condition? interrupt has occurred since the last read of this register. note: the user can obtain the current state of the rdi-l defect condition by reading out the st ate of bit 7 (rdi-l defect declared) within the ?receive sts-1 transport status register ? byte 0? (address location= 0xn107, where n ranges in value from 0x05 to 0x07).
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 644 table 456: receive sts-1 transport interrupt stat us register ? byte 1 (address location= 0xn10a, where n ranges in value from 0x05 to 0x07) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 new s1 byte interrupt status change in s1 byte unstable defect condition interrupt status change in section trace message unstable defect condition interrupt status new section trace message interrupt status change in section trace message mismatch defect declared interrupt status unused change in k1, k2 byte unstable defect condtion interrupt status new k1k2 byte value interrupt status rur rur rur rur rur r/o rur rur 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 new s1 byte value interrupt status rur new s1 byte value interrupt status: this reset-upon-read bit-field indicates whether or not the ?new s1 byte value? interrupt has occurred since the last read of this register. the receive sts-1 toh processor block will generate the ?new s1 byte value? interrupt, anytime it has ?accepted? a new s1 byte, from the incoming sts-1 data- stream. 0 ? indicates that the ?new s1 byte value? interrupt has not occurred since the last read of this register. 1 ? indicates that the ?new s1 byte value? interrupt has occurred since the last read of this register. note: the user can obtain the val ue for this most recently accepted value of the s1 byte by reading the ?receive sts-1 transport s1 byte value? register (address location= 0xn127). 6 change in s1 byte unstable defect condition interrupt status rur change in s1 byte unstable defect condition interrupt status: this reset-upon-read bit-field indicates whether or not the ?change in s1 byte unstable defect condition? interrupt has occurred since the last read of this register. the receive sts-1 toh processor block will generate this interrupt in response to either of the following events. ? whenever the receive sts-1 toh processor block declares the ?s1 byte unstable? defect condition. ? whenever the receive sts-1 toh processor block clears the ?s1 byte unstable? defect condition. 0 ? indicates that the ?change in s1 byte unstable defect condition? interrupt has occurr ed since the last read of this register. 1 ? indicates that the ?change in s1 byte unstable defect condition? interrupt has not occurred since the last read of this register. note: the user can obtain the current ?s1 byte unstable defect? condition by reading the contents of bit 6 (s1 byte unstable defect declared) within the ?receive sts - 1 trans p ort status re g ister ? b y te 0? ( address
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 645 location= 0xn107, where n ranges in value from 0x05 to 0x07). 5 change in section trace message unstable defect condition interrupt status rur change in section trace messag e unstable defect condition interrupt status: this reset-upon-read bit-field indicates whether or not the ?change in section trace message unstable? defect condition interrupt has occurred since the last read of this register. the receive sts-1 toh processor block will generate this interrupt in response to either of the following events. ? whenever the receive sts-1 toh processor block declares the ?section trace message unstable defect? condition. ? whenever the receive sts-1 toh processor block clear the ?section trace message unstable defect? condition. 0 ? indicates that the ?change in section trace message unstable defect? condition interrupt has not occurred since the last read of this register. 1 ? indicates that the ?change in section trace message unstable defect? condition interr upt has occurred since the last read of this register. 4 new section trace message interrupt status rur new section trace message interrupt status: this reset-upon-read bit-field indicates whether or not the ?new section trace message? interrupt has occurred since the last read of this register. the receive sts-1 toh processor block will generate this interrupt anytime it has accepted a new ?section trace? message within the incoming sts-1 data- stream. 0 ? indicates that the ?new section trace message interrupt? has not occurred since the la st read of this register. 1 ? indicates that the ?new section trace message interrupt? has occurred since the last read of this register. note: the user can read out the contents of the ?receive section trace message buffer?, which is located at address locations 0xn300 through 0xn33f (where n ranges in value from 0x05 to 0x07). 3 change in section trace mismatch defect condition interrupt status rur change in section trace message mismatch defect condition? interrupt status: this reset-upon-read bit-field indicates whether or not the ?change in section trace mismatch defect condition? interrupt has occurred since the last read of this register. the receive sts-1 toh processor block will generate this interrupt in response to either of the following events. ? whenever the receive sts-1 toh processor block declares the ?section trace message mismatch? defect condition ? whenever the receive sts-1 toh processor block clears the ?section trace mismatch? defect condition. 0 ? indicates that the ?change in section trace message mismatch defect condition? interrupt has not occurred since the last read of this register. 1 ? indicates that the ?change in section trace message mismatch defect condition? interrupt has occurred since the last read of this register. note: the user can determine whether the ?section trace
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 646 message mismatch? condition is currently ?cleared? or ?declared? by reading the state of bit 2 (section trace message mismatch defect declared) within the ?receive sts-1 transport status register ? byte 1 (address location= 0xn106). 2 unused r/o 1 change in k1, k2 byte unstable defect condition interrupt status rur change in k1, k2 byte unstable defect condition interrupt status: this reset-upon-read bit-field indicates whether or not the ?change in k1, k2 byte unstable defect condition? interrupt has occurred since the last read of this register. the receive sts-1 toh processor block will generate this interrupt in response to either of the following events. ? whenever the receive sts-1 toh processor block declares the ?k1, k2 byte unstable defect? condition. ? whenever the receive sts-1 toh processor block clears the ?k1, k2 byte unstable defect? condition. 0 ? indicates that the ?change of k1, k2 byte unstable defect condition? interrupt has not occurred since the last read of this register. 1 ? indicates that the ?change of k1, k2 byte unstable defect condition? interrupt has occurred since the last read of this register. note: the user can determine whether the ?k1, k2 byte unstable defect condition? is currently being declared or cleared by reading out the contents of bit 5 (k1, k2 byte unstable defect decl ared), within the ?receive sts-1 transport status register ? byte 0? (address location= 0xn107). 0 new k1, k2 byte value interrupt status rur new k1, k2 byte value interrupt status: this reset-upon-read bit-field indicates whether or not the ?new k1, k2 byte value? interrupt has occurred since the last read of this register. the receive sts-1 toh processor block will generate this interrupt whenever its has ?accepted? a new set of k1, k2 byte values from the incoming sts-1 data-stream. 0 ? indicates that the ?new k1, k2 byte value? interrupt has not occurred since the last read of this register. 1 ? indicates that the ?new k1, k2 byte value? interrupt has occurred since the last read of this register. note: the user can obtain the contents of the new k1 byte by reading out the contents of the ?receive sts-1 transport k1 byte value? register (address location= 0xn11f). further, the user can also obtain the contents of the new k2 by te by reading out the contents of the ?receive sts-1 transport k2 byte value? register (address location= 0xn123).
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 647 table 457: receive sts-1 transport interrupt stat us register ? byte 0 (address location= 0xn10b, where n ranges in value from 0x05 to 0x07) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 change of sf defect condition interrupt status change of sd defect condition interrupt status detection of rei-l event error interrupt status detection of b2 byte error interrupt status detection of b1 byte error interrupt status change of lof defect condition interrupt status change of sef defect interrupt status change of los defect condition interrupt status rur rur rur rur rur rur rur rur 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 change of sf defect condition interrupt status rur change of signal failure (sf) defect condition interrupt status: this reset-upon-read bit-field indicates whether or not the ?change of sf defect condition interrupt? has occurred si nce the last read of this register. the receive sts-1 toh processor block will generate this interrupt in response to either of the following events. ? whenever the receive sts-1 toh processor block declares the sf defect condition. ? whenever the receive sts-1 toh processor block clears the sf defect condition. 0 - indicates that the ?change of sf defect condition interrupt? has not occurred since the last read of this register. 1 ? indicates that the ?change of sf defect condition interrupt? has occurred since the last read of this register. note: the user can determine whether or not the sf defect condition is currently being declared by reading out the state of bit 4( sf defect declared) within the ?receive st s-1 transport status register ? byte 0 (address location= 0xn107). 6 change of sd defect condition interrupt status rur change of signal degrade (sd) defect condition interrupt status: this reset-upon-read bit-field indicates whether or not the ?change of sd defect condition interrupt? has occurred si nce the last read of this register. the receive sts-1 toh processor block will generate this interrupt in response to either of the following events. ? whenver the receive sts-1 toh processor block declares the sd defect condition. ? whenever the receive sts-1 toh processor block clears the sd defect condition. 0 ? indicates that the ?change of sd defect condition interrupt? has not occurred since the last read of this register. 1 ? indicates that the ?change of sd defect condition interrupt? has occurred since the last read of this register. note: the user can determine whether or not the sd defect condition is currently being declareds by r eading out the state of bit 3 (sd defect declared) within the ?receive sts-1 transport status register ? byte 0 (address location= 0xn107). 5 detection of rei-l event interrupt status rur detection of rei-l (line ? remote error indicator) event interrupt status: this reset-u p on-read bit-field indicates whether or not the ?detection of
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 648 rei-l event? interrupt has occurred since the last read of this register. the receive sts-1 toh processor block will generate this interrupt anytime it detects an rei-l event within the incoming sts-1 data-stream. 0 - indicates that the ?detection of rei-l event? interrupt has not occurred since the last read of this register. 1 ? indicates that the ?d etection of rei-l event? in terrupt has occurred since the last read of this register. 4 detection of b2 byte error interrupt status rur det ection of b2 byte error interrupt status: this reset-upon-read bit-field indicates whether or not the ?detection of b2 byte error interrupt? has occurred since the last read of this register. the receive sts-1 toh processor block will generate this interrupt anytime it detects a b2 byte error within the incoming sts-1 data-stream. 0 ? indicates that the ?detection of b2 byte error interrupt? has not occurred since the last read of this register. 1 ? indicates that the ?detection of b2 byte error interrupt? has occurred since the last read of this register. 3 detection of b1 byte error interrupt status rur detection of b1 byte error interrupt status: this reset-upon-read bit-field indicates whether or not the ?detection of b1 byte error interrupt? has occurred since the last read of this register. the receive sts-1 toh processor block will generate this interrupt anytime it detects a b1 byte error within the incoming sts-1 data-stream. 0 - indicates that the ?detection of b1 byte error interrupt? has not occurred since the last read of this register. 1 ? indicates that the ?detection of b1 byte error interrupt? has occurred since the last read of this register 2 change of lof defect condition interrupt status rur change of loss of frame (lof) defect condition interrupt status: this reset-upon-read bit-field indicates whether or not the ?change of lof defect condition? interrupt has occurred since the last read of this register. the receive sts-1 toh processor block will generate this interrupt in response to either of the following events. ? whenever the receive sts-1 toh processor block declares the lof defect condition. ? whenever the receive sts-1 toh processor block clears the lof defect condition. 0 ? indicates that the ?change of lo f defect condition? interrupt has not occurred since the last read of this register. 1 ? indicates that the ?change of lof defect condition? interrupt has occurred since the last read of this register. note: the user can determine whether or not the receive sts-1 toh processor block is currently declaring the lof defect condition by reading out the state of bit 2 (lof defect declared) within the ?receive sts-1 transport status register ? byte 0 (address location= 0xn107). 1 change of sef defect condition interrupt status rur change of sef defect condition interrupt status: this reset-upon-read bit-field indicates whether or not the ?change of sef defect condition? interrupt has occurred since the last read of this register. the receive sts-1 toh processor block will generate this interrupt in response to either of the following events. ? whenever the receive sts-1 toh processor block declares the sef defect condition.
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 649 ? whenever the receive sts-1 toh processor block clears the sef defect condition. 0 ? indicates that the ?change of sef defect condition? interrupt has not occurred since the last read of this register. 1 ? indicates that the ?change of sef defect condition? interrupt has occurred since the last read of this register. note: the user can determine whether or not the receive sts-1 toh processor block is currently declaring the sef defect condition by reading out the state of bit 1 ( sef defect declared) within the ?receive sts-1 transport status register ? byte 0 (address location= 0xn107). 0 change of los defect condition interrupt status rur change of loss of signal (los) defect condition interrupt status: this reset-upon-read bit-field indicates whether or not the ?change of los defect condition? interrupt has occurred since the last read of this register. the receive sts-1 toh proce ssor block will generate this interrupt in response to either of the following events. ? whenever the receive sts-1 toh processor block declares the los defect condition. ? whenever the receive sts-1 toh pr ocessor block clears the los defect condition. 0 ? indicates that the ?change of los defect condition? interrupt has not occurred since the last read of this register. 1 ? indicates that the ?change of lo s defect condition? interrupt has occurred since the last read of this register. note: the user can determine whether or not the receive sts-1 toh processor block is currently declaring the los defect condition by reading out the contents of bit 0 (los defect declared) within the receive sts-1 transport status register ? byte 0 (address location= 0xn107).
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 650 table 458: receive sts-1 transport interrupt enable register ? byte 2 (address location= 0xn10d, where n ranges in value from 0x05 to 0x07) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 unused change of ais-l defect condition interrupt enable change of rdi-l defect condition interrupt enable r/o r/o r/o r/o r/o r/o r/w r/w 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 ? 2 unused r/o 1 change of ais-l defect condition interrupt enable r/w change of ais-l (line ais) defect condition interrupt enable: this read/write bit-field permits the user to either enable or disable the ?change of ais-l defect condition? interrupt. if the user enables this interrupt, then the XRT94L33 will generate an interrupt in response to either of the following conditions. ? when the receive sts-1 toh processor block declares the ?ais-l? defect condition. ? when the receive sts-1 toh processor block clears the ?ais-l? defect condition. 0 ? disables the ?change of ais-l defect condition? interrupt. 1 ? enables the ?change of ais-l defect condition? interrupt. 0 change of rdi-l defect condition interrupt enable r/w change of rdi-l (line remote defect indicator) defect condition interrupt enable: this read/write bit-field permits the user to either enable or disable the ?change of rdi-l defect condition? interrupt. if the user enables this interrupt, then the XRT94L33 will generate an interrupt in response to either of the following conditions. ? when the receive sts-1 toh processor block declares the ?rdi-l? defect condition. ? when the receive sts-1 toh processor block clears the ?rdi-l? defect condition. 0 ? disables the ?change of rdi-l defect condition? interrupt. 1 ? enables the ?change of rdi-l defect condition? interrupt.
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 651 table 459: receive sts-1 transport interrupt enab le register ? byte 1 (address location= 0xn10e, where n ranges in value from 0x05 to 0x07) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 new s1 byte interrupt enable change in s1 byte unstable defect condition interrupt enable change in section trace message unstable defect condition interrupt enable new section trace message interrupt enable change in section trace message mismatch defect condition interrupt enable unused change in k1, k2 byte unstable defect condition interrupt enable new k1k2 byte value interrupt enable r/w r/w r/w r/w r/w r/o r/w r/w 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 new s1 byte value interrupt enable r/w new s1 byte value interrupt enable: this read/write bit-field permits the user to enable or disable the ?new s1 byte value? interrupt. if the user enables this interrupt, then the receive sts-1 toh processor block will generate this interrupt anytime it receives and accepts a new s1 byte value. the receive sts-1 toh processor block will accept a new s1 byte after it has received it for 8 consecutive sts-1 frames. 0 ? disables the ?new s1 byte value? interrupt. 1 ? enables the ?new s1 byte value? interrupt. 6 change in s1 byte unstable defect condition interrupt enable r/w change in s1 byte unstable defect condition interrupt enable: this read/write bit-field permits the user to either enable or disable the ?change in s1 byte unstable defect condition? interrupt. if the user enables this bit-field, then the receive sts-1 toh processor block will generate an interrupt in response to either of the following conditions. ? when the receive sts-1 toh processor block declares the ?s1 byte unstable? defect condition. ? when the receive sts-1 toh processor block clears the ?s1 byte unstable? defect condition. 0 ? disables the ?change in s1 byte unstable defect condition? interrupt. 1 ? enables the ?change in s1 byte unstable defect condition? interrupt. 5 change in section trace message unstable defect condition interrupt enable r/w change in section trace message unstable defect condition interrupt enable: this read/write bit-field permits the user to either enable or disable the ?change in section trace message unstable defect condition? interrupt. if the user enables this interrupt, then the receive sts-1 toh processor block will generate an interrupt in response to either of the following conditions. ? whenever the receive sts-1 toh processor block declares the ?section trace message unstable? defect condition. ? whenever the receive sts-1 toh processor block clears the ?section trace message unstable? defect condition. 0 ? disable the ?change of section trace message unstable defect condition? interrupt.
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 652 1 ? enables the ?change of section trace message unstable defect condition? interrupt. 4 new section trace message interrupt enable r/w new section trace message interrupt enable: this read/write bit-field permits the user to enable or disable the ?new section trace message? interrupt. if t he user enables this interrupt, then the receive sts-1 toh processor block will generate this interrupt anytime it receives and accepts a new section trace message within the incoming sts-1 data-stream. the receive sts-1 toh processor block will accept a new section trace message after it has received it 3 (or 5) consecutive times. 0 ? disables the ?new section trace message? interrupt. 1 ? enables the ?new section trace message? interrupt. 3 change in section trace message mismatch defect condition interrupt enable r/w change in ?section trace mismatch defect condition? interrupt enable: this read/write bit-field permits the user to either enable or disable the ?change in section trace mismatch defect condition? interrupt. if the user enables this interrupt, then the receive sts-1 toh processor block will generate an interrupt in response to either of the following events. a. whenever the receive sts-1 toh processor block declares the ?section trace message mismatch defect? condition. b. whenever the receive sts-1 toh processor block clears the ?section trace message mismatch defect? condition. note: the user can determine whether or not the receive sts-1 toh processor block is currently declaring the ?section trace message mismatch defect? condition by reading the state of bit 2 (section trace message mismatch defect condition declared) within the ?receive sts-1 transport status register ? byte 1 (address location= 0xn106). 2 unused r/o 1 change in k1, k2 byte unstable defect condition interrupt enable r/w change of k1, k2 byte unstable defect condition - interrupt enable: this read/write bit-field permits the user to either enable or disable the ?change of k1, k2 byte unstable defect condition? interrupt. if the user enables this interrupt, then the receive sts-1 toh processor block will generate an interrupt in response to either of the following events. a. whenever the receive sts-1 toh processor block declares the ?k1, k2 byte unstable defect? condition. b. whenever the receive sts-1 toh processor block clears the ?k1, k2 byte unstable defect? condition. 0 ? disables the ?change of k1, k2 byte unstable defect condition? interrupt. 1 ? enables the ?change of k1, k2 byte unstable defect condition? interrupt. 0 new k1k2 byte interrupt enable r/w new k1, k2 byte value interrupt enable: this read/write bit-field permits the user to either enable or disable the ?new k1, k2 byte valu e? interrupt. if the user enables this interrupt, then the receive sts-1 toh processor block will generate this interrupt anytime it receives and accepts a new k1, k2 byte value. the receive sts-1 toh processor block will accept a new k1, k2 byte value, after it has received it within 3 (or 5) consecutive sts-1 frames. 0 ? disables the ?new k1, k2 byte value? interrupt.
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 653 1 ? enables the ?new k1, k2 byte value? interrupt.
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 654 table 460: receive sts-1transport interrupt status register ? byte 0 (address location= 0xn10f, where n ranges in value from 0x05 to 0x07) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 change of sf defect condition interrupt enable change of sd defect condition interrupt enable detection of rei-l event interrupt enable detection of b2 byte error interrupt enable detection of b1 byte error interrupt enable change of lof defect condition interrupt enable change of sef defect condition interrupt enable change of los defect condition interrupt enable r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 change of sf defect condition interrupt enable r/w change of signal failure (sf) defect condition interrupt enable: this read/write bit-field permits the user to either enable or disable the ?change of signal failure (sf) defect condition? interrupt. if the user enables this interrupt, then the XRT94L33 will generate an interrupt in response to any of the following events. ? whenever the receive sts-1 toh processor block declares the sf defect condition. ? whenever the receive sts-1 toh processor block clears the sf defect condition. 0 ? disables the ?change of sf defect condition interrupt?. 1 ? enables the ?change of sf defect condition interrupt?. 6 change of sd defect condition interrupt enable r/w change of signal degrade (sd) defect condition interrupt enable: this read/write bit-field permits the user to either enable or disable the ?change of signal degrade (sd) defect condition? interrupt. if the user enables this interrupt, then the XRT94L33 will generate an interrupt in response to either of the following events. ? whenever the receive sts-1 toh processor blolck declares the sd defect condition. ? whenever the receive sts-1 toh processor block clears the sd defect condition. 0 ? disables the ?change of sd defect condition interrupt?. 1 ? enables the ?change of sd defect condition interrupt?. 5 detection of rei-l event interrupt enable r/w detection of rei-l (line ? remote error indicator) event interrupt enable: this read/write bit-field permits the user to either enable or disable the ?detection of rei-l event? interrupt. if the user enables this interrupt, then the XRT94L33 will generate an interrupt anytime the receive sts-1 toh processor block detects an rei-l condition within the incoming sts-1 data-stream. 0 ? disables the ?detection of rei-l event? interrupt. 1 ? enables the ?detection of rei-l event? interrupt. 4 detection of b2 byte error interrupt enable r/w detection of b2 byte error interrupt enable: this read/write bit-field permits the user to either enable or disable the ?detection of b2 byte error? interrupt. if the user enables this interrupt, then the XRT94L33 will g enerate an interru p t an y time the receive sts-1
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 655 toh processor block detects a b2 byte error within the incoming sts-1 data-stream. 0 ? disables the ?detection of b2 byte error interrupt?. 1 ? enables the ?detection of b2 byte error interrupt?. 3 detection of b1 byte error interrupt enable r/w detection of b1 byte error interrupt enable: this read/write bit-field permits the user to either enable or disable the ?detection of b1 byte error? interrupt. if the user enables this interrupt, then the XRT94L33 will generate an interrupt anytime the receive sts-1 toh processor block detects a b1 byte error within the incoming sts-1 data-stream. 0 ? disables the ?detection of b1 byte error interrupt?. 1 ? enables the ?detection of b1 byte error interrupt?. 2 change of lof defect condition interrupt enable r/w change of loss of frame (lof) defect condition interrupt enable: this read/write bit-field permits the user to either enable or disable the ?change of lof defect condition? interrupt. if the user enables this interrupt, then the XRT94L33 will generate an interrupt in response to either of the following conditions. ? when the receive sts-1 toh processor block declares the ?lof? defect condition. ? when the receive sts-1 toh processor block clears the ?lof? defect condition. 0 ? disables the ?change of lof defect condition interrupt. 1 ? enables the ?change of lof defect condition? interrupt. 1 change of sef defect condition interrupt enable r/w change of sef defect condition interrupt enable: this read/write bit-field permits the user to either enable or disable the ?change of sef defect condition? interrupt. if the user enables this interrupt, then the XRT94L33 will generate an interrupt in response to either of the following conditions. ? when the receive sts-1 toh processor block declares the ?sef? defect condition. ? when the receive sts-1 toh processor block clears the ?sef? defect condition. 0 ? disables the ? change of sef defect condition interrupt?. 1 ? enables the ?change of sef defect condition interrupt?. 0 change of los defect condition interrupt enable r/w change of loss of signal (los) defect condition interrupt enable: this read/write bit-field permits the user to either enable or disable the ?change of lof defect condition? interrupt. if the user enables this interrupt, then the XRT94L33 will generate an interrupt in response to either of the following conditions. ? when the receive sts-1 toh processor block declares the ?lof? defect condition. ? when the receive sts-1 toh processor block clears the ?lof? defect condition. 0 ? disables the ?change of lof defect condition interrupt. 1 ? enables the ?change of lof defect condition? interrupt.
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 656 table 461: receive sts-1 transport ? b1 byte e rror count register ? byte 3 (address location= 0xn110, where n ranges in value from 0x05 to 0x07) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 b1_byte_error_count[31:24] rur rur rur rur rur rur rur rur 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 - 0 b1_byte_error_count[31:24] rur b1 byte error count ? msb: this reset-upon-read register, along with ?receive sts-1 transport ? b1 byte error count register ? bytes 2 through 0; function as a 32 bit counter, wh ich is incremented anytime the receive sts-1 toh processor block detects a b1 byte error. note: 1. if the receive sts-1 toh processor block is configured to count b1 byte errors on a ?per-bit? basis, then it will increment this 32 bit counter by the number of bits, within the b1 byte (of each incoming sts-1 frame) that are in error 2. if the receive sts-1 toh processor block is configured to count b1 byte errors on a ?per-f rame? basis, then it will increment this 32 bit counter each time that it receives an sts-1 frame that contains an erred b1 byte.
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 657 table 462: receive sts-1 transport ? b1 byte e rror count register ? byte 2 (address location= 0xn111, where n ranges in value from 0x05 to 0x07) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 b1_byte_error_count[23:16] rur rur rur rur rur rur rur rur 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 - 0 b1_byte_error_count[23:16] rur b1 byte error count (bits 23 through 16): this reset-upon-read register, along with ?receive sts-1 transport ? b1 byte error count register ? bytes 3, 1 and 0; function as a 32 bit counter, wh ich is incremented anytime the receive sts-1 toh processor block detects a b1 byte error. note: 1. if the receive sts-1 toh processor block is configured to count b1 byte errors on a ?per-bit? basis, then it will increment this 32 bit counter by the number of bits, within the b1 byte (of each incoming sts-1 frame) that are in error. 2. if the receive sts-1 toh processor block is configured to count b1 byte errors on a ?per-f rame? basis, then it will increment this 32 bit counter each time that it receives an sts-1 frame that contains an erred b1 byte.
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 658 table 463: receive sts-1 transport ? b1 byte e rror count register ? byte 1 (address location= 0xn112, where n ranges in value from 0x05 to 0x07) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 b1_byte_error_count[15:8] rur rur rur rur rur rur rur rur 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 - 0 b1_byte_error_count[15:8] rur b1 byte error count ? (bits 15 through 8) this reset-upon-read register, along with ?receive sts-1 transport ? b1 byte error count register ? bytes 3, 2 and 0; function as a 32 bit counter, which is incremented anytime the receive sts-1 toh processor block detects a b1 byte error. note: 1. if the receive sts-1 toh processor block is configured to count b1 byte errors on a ?per-bit? basis, then it will increment this 32 bit counter by the number of bits, within the b1 byte (of each incoming sts-1 frame) that are in error 2. if the receive sts-1 toh processor block is configured to count b1 byte errors on a ?per-f rame? basis, then it will increment this 32 bit counter each time that it receives an sts-1 frame that contains an erred b1 byte.
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 659 table 464: receive sts-1 transport ? b1 byte e rror count register ? byte 0 (address location= 0xn113, where n ranges in value from 0x05 to 0x07) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 b1_byte_error_count[7:0] rur rur rur rur rur rur rur rur 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 - 0 b1_byte_error_count[7:0] rur b1 byte error count ? lsb: this reset-upon-read register, along with ?receive sts-1 transport ? b1 byte error count register ? bytes 3 through 1; function as a 32 bit counter, which is incremented anytime the receive sts-1 toh processor block detects a b1 byte error. note: 1. if the receive sts-1 toh processor block is configured to count b1 byte errors on a ?per-bit? basis, then it will increment this 32 bit counter by the number of bits, within the b1 byte (of each incoming sts-1 frame) that are in error. 2. if the receive sts-1 toh processor block is configured to count b1 byte errors on a ?per-f rame? basis, then it will increment this 32 bit counter each time that it receives an sts-1 frame that contains an erred b1 byte.
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 660 table 465: receive sts-1 transport ? b2 byte e rror count register ? byte 3 (address location= 0xn114, where n ranges in value from 0x05 to 0x07) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 b2_byte_error_count[31:24] rur rur rur rur rur rur rur rur 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 - 0 b2_byte_error_count[31:24] rur b2 byte error count ? msb: this reset-upon-read register, along with ?receive sts-1 transport ? b2 byte error count register ? bytes 2 through 0; function as a 32 bit counter, which is incremented anytime the receive sts-1 toh processor block detects a b2 byte error. note: 1. if the receive sts-1 toh processor block is configured to count b2 byte errors on a ?per-bit? basis, then it will increment this 32 bit counter by the number of bi ts, within the b2 byte (of each incoming sts-1 frame) that are in error. 2. if the receive sts-1 toh processor block is configured to count b2 byte errors on a ?per-f rame? basis, then it will increment this 32 bit counter each time that it receives an sts-1 frame that contains an erred b2 byte.
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 661 table 466: receive sts-1 transport ? b2 byte e rror count register ? byte 2 (address location= 0xn115, where n ranges in value from 0x05 to 0x07) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 b2_byte_error_count[23:16] rur rur rur rur rur rur rur rur 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 - 0 b2_byte_error_count[23:16] rur b2 byte error count (bits 23 through 16): this reset-upon-read register, along with ?receive transport ? b2 byte error count register ? bytes 3, 1 and 0; function as a 32 bit counter, which is incremented anytime the receive sts-1 toh processor block detects a b2 byte error. note: 1. if the receive sts-1 toh processor block is configured to count b2 byte errors on a ?per-bit? basis, then it will increment this 32 bit counter by the number of bits, within the b2 byte (of each incoming sts-1 frame) that are in error. 2. if the receive sts-1 toh processor block is configured to count b2 byte errors on a ?per-bit? basis, then it will increment this 32 bit counter each time that it receives an sts-1 frame that contains an erred b2 byte.
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 662 table 467: receive sts-1 transport ? b2 byte e rror count register ? byte 1 (address location= 0xn116, where n ranges in value from 0x05 to 0x07) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 b2_byte_error_count[15:8] rur rur rur rur rur rur rur rur 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 - 0 b2_byte_error_count[15:8] rur b2 byte error count ? (bits 15 through 8) this reset-upon-read register, along with ?receive transport ? b2 byte error count register ? bytes 3, 2 and 0; function as a 32 bit counter, which is incremented anytime the receive sts-1 toh processor block detects a b2 byte error. note: 1. if the receive sts-1 toh processror block is configured to count b2 byte errors on a ?per-bit? basis, then it will increment this 32 bit counter by the number of bits, within the b2 byte (of each incoming sts-1 frame) that are in error. 2. if the receive sts-1 toh processor block is configured to count b2 byte errors on a ?per-fra me? basis, then it will increment this 32 bit counter each time that it receives an sts-1 frame that contains an erred b2 byte.
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 663 table 468: receive sts-1 transport ? b2 byte e rror count register ? byte 0 (address location= 0xn117, where n ranges in value from 0x05 to 0x07) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 b2_byte_error_count[7:0] rur rur rur rur rur rur rur rur 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 - 0 b2_byte_error_count[7:0] rur b2 byte error count ? lsb: this reset-upon-read register, along with ?receive transport ? b2 byte error count register ? bytes 3 through 1; function as a 32 bit counter, which is increment ed anytime the receive sts-1 toh processor block detects a b2 byte error. note: 1. if the receive sts-1 toh processor block is confiuged to count b2 byte errors on a ?per-bit? basis, then it will increment this 32 bit counter by the number of bits, within the b2 byte (of each incoming sts-1 frame) that are in error. 2. if the receive sts-1 toh proce ssor block is configured to count b2 byte errors on a ?per-frame? basis, then it will increment this 32 bit counter each time that it rece ives an sts-1 frame that contains an erred b2 byte.
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 664 table 469: receive sts-1 transport ? rei-l event count register ? byte 3 (address location = 0xn118, where n ranges in value from 0x05 to 0x07) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 rei-l_event_count[31:24] rur rur rur rur rur rur rur rur 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 - 0 rei-l event count[31:24] rur rei-l event count ? msb: this reset-upon-read register, along with ?receive sts-1 transport ? rei-l event count register ? bytes 2 through 0; function as a 32 bit counter, which is incremented anytime the receive sts-1 toh processor block detects a line - remote error indicator event within the incoming sts-1 data-stream. note: 1. if the receive sts-1 toh processor block is configured to count rei-l events on a ?per-bit? basi s, then it will increment this 32 bit counter by the nibble-value within the rei-l field of the m0 byte within each incoming sts-1 frame. 2. if the receive sts-1 toh processor block is configured to count rei-l events on a ?per-fra me? basis, then it will increment this 32 bit counter each time that it receives an sts-1 frame that contains a ?non-zero? rei-l value.
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 665 table 470: receive sts-1 transport ? rei-l event count register ? byte 2 (address location= 0xn119, where n ranges in value from 0x05 to 0x07) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 rei-l_event_count[23:16] rur rur rur rur rur rur rur rur 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 - 0 rei-l event count[23:16] rur rei-l event count (bits 23 through 16): this reset-upon-read register, along with ?receive sts-1 transport ? rei-l event count re gister ? bytes 3, 1 and 0; function as a 32 bit counter, which is incremented anytime the receive sts-1 toh processor block detects a line ? remote error indicator event within the incoming sts-1 data-stream. note: 1. if the receive sts-1 toh processor block is configured to count rei-l events on a ?per-bit? basis, then it will increment this 32 bit counter by the nibble-value within the rei-l field of the m0 byte within each incoming sts-1 frame. 2. if the receive sts-1 toh processor block is configured to count rei-l events on a ?per-frame ? basis, then it will increment this 32 bit counter each time that it receives an sts-1 frame that contains a ?non-zero? rei-l value.
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 666 table 471: receive sts-1 transport ? rei-l event count register ? byte 1 (address location= 0xn11a, where n ranges in value from 0x05 to 0x07) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 rei-l_event_count[15:8] rur rur rur rur rur rur rur rur 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 - 0 rei-l event count[15:8] rur rei-l event count ? (bits 15 through 8) this reset-upon-read register, along with ?receive sts-1 transport ? rei-l event count register ? bytes 3, 2 and 0; function as a 32 bit counter, which is incremented anytime the receive sts- 1 toh processor block detects a line ?remote error indicator event within the incoming sts-1 data-stream. note: 1. if the receive sts-1 toh proce ssor block is configured to count rei-l events on a ?per-bit? basis, then it will increment this 32 bit counter by the nibble-value within the rei-l field of the m0 byte within each incoming sts-1 frame. 2. if the receive sts-1 toh proce ssor block is configured to count rei-l events on a ?per-frame? basis, then it will increment this 32 bit counter each time that it receiv es an sts-1 frame that contains a ?non-zero? rei-l value.
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 667 table 472: receive sts-1 transport ? rei-l event count register ? byte 0 (address location= 0xn11b, where n ranges in value from 0x05 to 0x07) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 rei-l_event_count[7:0] rur rur rur rur rur rur rur rur 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 - 0 rei-l event count[7:0] rur rei-l event count ? lsb: this reset-upon-read register, along with ?receive sts-1 transport ? rei-l event count register ? bytes 3 through 1; function as a 32 bit counter, which is incremented anytime the receive sts-1 toh processor block detects a line ? remote error indicator event within the incoming sts-1 data-stream. note: 1. if the receive sts-1 toh processor block is configured to count rei-l events on a ?per-bit? basis, then it will increment this 32 bit counter by the nibble-value within the rei-l field of the m0 byte. 2. if the receive sts-1 toh processor block is configured to count rei-l events on a ?per-frame? basis, then it will increment this 32 bit counter each time that it receives an sts-1 frame that contains a ?non-zero? rei-l value.
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 668 table 473: receive sts-1 transport ? received k1 byte value register (address location= 0xn11f, where n ranges in value from 0x05 to 0x07) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 filtered_k1_byte_value[7:0] r/o r/o r/o r/o r/o r/o r/o r/o 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 ? 0 filtered_k1_byte_value[7:0] r/o filtered/accepted k1 byte value: these read-only bit-fields contain the value of the most recently ?filtered? k1 byte value that the receive sts-1 toh processor block has received. these bit-fields are valid if the k1/k2 pair (to which it belongs) has been received for 3 consecutive sts-1 frames. this register should be polled by software in order to determine various aps codes. table 474: receive sts-1transport ? received k2 by te value register (address location= 0xn123, where n ranges in value from 0x05 to 0x07) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 filtered_k2_byte_value[7:0] r/o r/o r/o r/o r/o r/o r/o r/o 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 ? 0 filtered_k2_byte_value[7:0] r/o filtered/accepted k2 byte value: these read-only bit-fields contain the value of the most recently ?filtered? k2 byte va lue that the receive sts-1 toh processor block has received. these bit-fields are valid if the k1/k2 pair (to which it belongs) has been received for 3 consecutive sts-1 frames. this register should be polled by software in order to determine various aps codes.
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 669 table 475: receive sts-1 transport ? received s1 byte value register (address location= 0xn127, where n ranges in value from 0x05 to 0x07) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 filtered_s1_byte_value[7:0] r/o r/o r/o r/o r/o r/o r/o r/o 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 ? 0 filtered_s1_byte_value[7:0] r/o filtered/accepted s1 byte value: these read-only bit-fields contain the value of the most recently ?filtered? s1 byte value that the receive sts-1 toh processor block has received. these bit-fields are valid if it has been received for 8 consecutive sts-1 frames. table 476: receive sts-1 transport ? los threshol d value - msb (address location= 0xn12e, where n ranges in value from 0x05 to 0x07) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 los_threshold[15:8] r/w r/w r/w r/w r/w r/w r/w r/w 1 1 1 1 1 1 1 1 b it n umber n ame t ype d escription 7 - 0 los_threshold[15:8] r/w los threshold value ? msb: these read/write bits, along the contents of the ?receive sts-1 transport ? los threshold value ? lsb? register specify the number of consecut ive (all zero) bytes that the receive sts-1 toh processor block must detect before it can declare the los defect condition.
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 670 table 477: receive sts-1 transport ? los threshold value - lsb (address location= 0xn12f, where n ranges in value from 0x05 to 0x07) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 los_threshold[7:0] r/w r/w r/w r/w r/w r/w r/w r/w 1 1 1 1 1 1 1 1 b it n umber n ame t ype d escription 7 - 0 los_threshold[7:0] r/w los threshold value ? lsb: these read/write bits, along the contents of the ?receive sts-1transport ? los threshold value ? msb? register specify the number of consecut ive (all zero) bytes that the receive sts-1 toh processor block must detect before it can declare the los defect condition.
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 671 table 478: receive sts-1 transport ? receive sf set monitor interval ? byte 2 (address location= 0xn131, where n ranges in value from 0x05 to 0x07) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 sf_set_monitor_window[23:16] r/w r/w r/w r/w r/w r/w r/w r/w 1 1 1 1 1 1 1 1 b it n umber n ame t ype d escription 7 - 0 sf_set_monitor_window[23:1 6] r/w sf_set_monitor_interval ? msb: these read/write bits, along the contents of the ?receive sts-1 transport ? sf set monitor interval ? byte 1 and byte 0? registers permit the user to specify the length of the ?monitoring period? (in terms of ms) for sf (signal failure) defect declaration. when the receive sts-1 toh processor block is checking the incoming sts-1 signal in order to determine if it should declare the sf defect condition, it will accumulate b2 byte errors throughout the user- specified ?sf defect declarat ion monitoring period?. if, during this ?sf defect declaration monitoring period?, the receive sts-1 toh processor block accumulates more b2 byte erro rs than that specified within the ?receive sts-1 transport sf set threshold? register, then the receive sts-1 toh processor block will declare the sf defect condition. notes: 1. the value that the user writes into these three (3) ?sf set monitor window? registers, specifies t he duration of the ?sf defect? declaration monitoring period?, in terms of ms. 2. this particular register byte contains the ?msb? (most significant byte) value of the three registers that sp ecify the ?sf defect declaration monitoring period?.
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 672 table 479: receive sts-1 transport ? receive sf set monitor interval ? byte 1 (address location= 0xn132, where n ranges in value from 0x05 to 0x07) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 sf_set_monitor_window[15:8] r/w r/w r/w r/w r/w r/w r/w r/w 1 1 1 1 1 1 1 1 b it n umber n ame t ype d escription 7 - 0 sf_set_monitor_window[15:8] r/w sf_set_monitor_interval (bits 15 through 8): these read/write bits, along the contents of the ?receive sts-1 transport ? sf set monitor interval ? byte 2 and byte 0? registers permit the user to specify the length of the ?monitoring period? (in terms of ms) for sf (signal failure) defect declaration. when the receive sts-1 toh processor block is checking the incoming sts-1 signal in order to determine if it should declare the sf defect condition, it will accumulate b2 byte errors throughout the user- specified ?sf defect declaration monitoring period?. if, during this ?sf defect declaration monitoring period? the receive sts-1 toh processor block accumulate more b2 byte errors than that specified within the ?receive sts-1 transport sf set threshold? register, then the receive sts-1 toh processor block will declare the sf defect condition. note: the value that the user writes into these three (3) ?sf set monitor window? registers, specifies the duration of the ?sf defect declaration? monitoring period, in terms of ms.
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 673 table 480: receive sts-1 transport ? receive sf set monitor interval ? byte 0 (address location= 0xn133, where n ranges in value from 0x05 to 0x07) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 sf_set_monitor_window[7:0] r/w r/w r/w r/w r/w r/w r/w r/w 1 1 1 1 1 1 1 1 b it n umber n ame t ype d escription 7 - 0 sf_set_monitor_window[7:0 ] r/w sf_set_monitor_interval ? lsb: these read/write bits, along the contents of the ?receive sts-1 transport ? sf set monitor interval ? byte 2 and byte 1? registers permit the user to specify the length of the ?monitoring period? (in terms of ms) for sf (signal failure) defect declaration. when the receive sts-1 toh processor block is checking the incoming sts-1 signal in order to determine if it should declare the sf defect condition, it will accumulate b2 byte errors throughout the user-specified ?sf defect declaration monitori ng period?. if, during this ?sf defect declaration monitoring period?, the receive sts-1 toh processor block accumulates more b2 byte errors than that specified within the ?receive sts-1 transport sf set threshold? register, then the receive sts-1 toh processor block will declare the sf defect condition. notes: 1. the value that the user writes into these three (3) ?sf set monitor window? registers, specifies the duration of the ?sf defect declaration? monitoring period, in terms of ms. 2. this particular register byte contains the ?lsb? (least significant byte) value of the three registers that specify the ?sf defect declaration monitoring period?.
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 674 table 481: receive sts-1 transport ? receive sf set threshold ? byte 1 (address location= 0xn136, where n ranges in value from 0x05 to 0x07) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 sf_set_threshold[15:8] r/w r/w r/w r/w r/w r/w r/w r/w 1 1 1 1 1 1 1 1 b it n umber n ame t ype d escription 7 - 0 sf_set_threshold[15:8] r/w sf_set_threshold ? msb: these read/write bits, along the contents of the ?receive sts-1 transport ? sf set threshold ? byte 0? registers permit the user to specify the number of b2 byte errors that will cause the receive sts-1 toh processor block to declare the sf (signal failure) defect condition. when the receive sts-1 toh processor block is checking the incoming sts-1 signal in order to determine if it should declare the sf defect condition, it wi ll accumulate b2 byte errors throughout the ?sf defect declaration monitoring period?. if the number of accumulated b2 byte errors exceeds that value, which is programmed into this and the ?receive sts-1 transport sf set threshold ? byte 0? register, then the receive sts-1 toh processor block will declare the sf defect condition.
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 675 table 482: receive sts-1 transport ? receive sf set threshold ? byte 0 (address location= 0xn137, where n ranges in value from 0x05 to 0x07) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 sf_set_threshold[7:0] r/w r/w r/w r/w r/w r/w r/w r/w 1 1 1 1 1 1 1 1 b it n umber n ame t ype d escription 7 - 0 sf_set_threshold[7:0] r/w sf_set_threshold ? lsb: these read/write bits, along the contents of the ?receive sts-1 transport ? sf set threshold ? byte 1? registers permit the user to specify the number of b2 byte errors that will cause the receive sts-1 toh processor block to declare the sf (signal failure) defect condition. when the receive sts-1 toh processor block is checking the incoming sts-1 signal in order to determine if it should declare the sf defect condition, it will accumulate b2 byte errors throughout the ?sf defect monito ring period?. if the number of accumulated b2 byte errors exceeds that which has been programmed into this and the ?receive sts-1 transport sf set threshold ? byte 1? register, then the receive sts-1 toh processor block will declare the sf defect condition.
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 676 table 483: receive sts-1 transport ? receive sf clear threshold ? byte 1 (address location= 0xn13a, where n ranges in value from 0x05 to 0x07) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 sf_clear_threshold[15:8] r/w r/w r/w r/w r/w r/w r/w r/w 1 1 1 1 1 1 1 1 b it n umber n ame t ype d escription 7 - 0 sf_clear_threshold [15:8] r/w sf_clear_threshold ? msb: these read/write bits, along the contents of the ?receive sts-1 transport ? sf clear threshold ? byte 0? registers permit the user to specify the upper limit for the number of b2 bit errors that will cause the receive sts-1 toh processor block to clear the sf (signal failure) defect condition. when the receive sts-1 toh processor block is checking the incoming sts-1 signal in order to determine if it should clear the sf defect condition, it will accumulate b2 byte errors throughout the ?sf defect clearance monitoring period?. if the number of accumulated b2 byte errors is less than that programmed into this and the ?receive sts-1 transport sf clear threshold ? byte 0? register, then the receive sts-1 toh processor block clear the sf defect condition. table 484: receive sts-1 transport ? receive sf clear threshold ? byte 0 (address location= 0xn13b, where n ranges in value from 0x05 to 0x07) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 sf_clear_threshold[7:0] r/w r/w r/w r/w r/w r/w r/w r/w 1 1 1 1 1 1 1 1 b it n umber n ame t ype d escription 7 - 0 sf_clear_threshold [7:0] r/w sf_clear_threshold ? lsb: these read/write bits, along the contents of the ?receive sts-1 transport ? sf clear threshold ? byte 1? registers permit the user to specify the upper limit for the number of b2 bit errors that will cause the receive sts-1 toh processor block to clear the sf (signal failure) defect condition. when the receive sts-1 toh processor block is checking the incoming sts-1 signal in order to determine if it should clear the sf defect condition, it will accumulate b2 byte errors throughout the ?sf defect clearance monitoring period?. if the number of accumulated b2 byte errors is less than that programmed into this and the ?receive sts-1 transport sf clear threshold ? byte 1? register, then the receive sts-1 toh processor block will clear the sf defect condition.
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 677 table 485: receive sts-1 transport ? receive sd set monitor interval ? byte 2 (address location= 0xn13d, where n ranges in value from 0x05 to 0x07) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 sd_set_monitor_window[23:16] r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7-0 sd_set_monitor_window [23:16] r/w sd_set_monitor_interval ? msb: these read/write bits, along the contents of the ?receive sts-1 transport ? sd set monitor interval ? byte 1 and byte 0? registers permit the user to specify the length of the ?monitoring period? (in terms of ms) for sd (signal degrade) defect declaration. when the receive sts-1 toh processor block is checking the incoming sts-1 signal in order to determine if it should declare the sd defect condition, it will accumulate b2 byte errors throughout the user-spec ified ?sd defect declaration monitoring period?. if, during th is ?sd defect declaration monitoring period?, the receive sts-1 toh processor block accumulates more b2 byte errors than that specified within the ?receive sts-1 transport sd set threshold? register, then the receive sts-1 toh processor block will declare the sd defect condition. notes: 1. the value that the user wr ites into these three (3) ?sd set monitor window? registers, specifies the duration of the ?sd defect declaration monitoring period?, in terms of ms. 2. this particular register by te contains the ?msb? (most significant byte) value of the three registers that specify the ?sd defect declaration monitoring period?.
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 678 table 486: receive sts-1 transport ? receive sd set monitor interval ? byte 1 (address location= 0xn13e, where n ranges in value from 0x05 to 0x07) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 sd_set_monitor_window[15:8] r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7-0 sd_set_monitor_window [15:8] r/w sd_set_monitor_interval ? bits 15 through 8: these read/write bits, along the contents of the ?receive sts-1 transport ? sd set monitor interval ? byte 2 and byte 0? registers permit the user to specify the length of the ?monitoring period? (in terms of ms) for sd (signal degrade) defect declaration. when the receive sts-1 toh processor block is checking the incoming sts-1 signal in order to determine it it should declare the sd defect condition, it will accumulate b2 byte errors throughout the user-spec ified ?sd defect declaration monitoring period?. if, during th is ?sd defect declaration monitoring period? the receive sts-1 toh processor block accumulates more b2 byte errors than that specified within the ?receive sts-1 transport sd set threshold? register, then the receive sts-1 toh processor block will declare the sd defect condition. note: the value that the user writes into these three (3) ?sd set monitor window? registers, specifies the duration of the ?sd defect declaration? monitoring period, in terms of ms.
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 679 table 487: receive sts-1 transport ? receive sd set monitor interval ? byte 0 (address location= 0xn13f, where n ranges in value from 0x05 to 0x07) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 sd_set_monitor_window[7:0] r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7-0 sd_set_monitor_window [7:0] r/w sd_set_monitor_interval ? lsb: these read/write bits, along the contents of the ?receive sts-1 transport ? sd set monitor interval ? byte 2 and byte 1? registers permit the user to specify the length of the ?monitoring period? (in terms of ms) for sd (signal degrade) defect declaration. when the receive sts-1 toh processor block is checking the incoming sts-1 signal in order to determine if it should declare the sd defect condition, it will accumulate b2 byte errors throughout the user-spec ified ?sd defect declaration monitoring period?. if, during th is ?sd defect declaration monitoring period?, the receive sts-1 toh processor block accumulates more b2 byte errors than that specified within the ?receive sts-1 transport sd set threshold? register, then the receive sts-1 toh processor block will declare the sd defect condition. notes: 1. the value that the user wr ites into these three (3) ?sd set monitor window? registers, specifies the duration of the ?sd defect declaration? monitoring period, in terms of ms. 2. this particular register byte contains the ?lsb? (least significant byte) value of the three registers that specify the ?sd defect declaration monitoring period?.
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 680 table 488: receive sts-1 transport ? receive sd set threshold ? byte 1 (address location= 0xn142, where n ranges in value from 0x05 to 0x07) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 sd_set_threshold[15:8] r/w r/w r/w r/w r/w r/w r/w r/w 1 1 1 1 1 1 1 1 b it n umber n ame t ype d escription 7 - 0 sd_set_threshold[15:8] r/w sd_set_threshold ? msb: these read/write bits, along the contents of the ?receive sts-1 transport ? sd set threshold ? byte 0? registers permit the user to specify the number of b2 bit errors that will cause the receive sts-1 toh processor block to declare the sd (signal degrade) defect condition. when the receive sts-1 toh processor block is checking the incoming sts-1 signal in order to determine if it should declare the sd defect condition, it will accumulate b2 byte errors throughout the ?sd defect declaration monitoring period?. if the number of accumulated b2 byte errors exceeds that value, which is programmed into this and the ?receive sts-1 transport sd set threshold ? byte 0? register, then the receive sts-1 toh processor block will declare the sd defect condition.
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 681 table 489: receive sts-1 transport ? receive sd set threshold ? byte 0 (address location= 0xn143, where n ranges in value from 0x05 to 0x07) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 sd_set_threshold[7:0] r/w r/w r/w r/w r/w r/w r/w r/w 1 1 1 1 1 1 1 1 b it n umber n ame t ype d escription 7 - 0 sd_set_threshold[7:0] r/w sd_set_threshold ? lsb: these read/write bits, along the contents of the ?receive sts-1 transport ? sd set threshold ? byte 1? registers permit the user to specify the number of b2 bit errors that will cause the receive sts-1 toh processor block to declare an sd (signal degrade) defect condition. when the receive sts-1 toh processor block is checking the incoming sts-1 signal in order to determine if it should declare the sd defect condition, it will accumulate b2 byte errors throughout the ?sd defect monito ring period?. if the number of accumulated b2 byte errors exceeds that which has been programmed into this and the ?receive sts-1 transport sd set threshold ? byte 1? register, then the receive sts-1 toh processor block will declare the sd defect condition. table 490: receive sts-1 transport ? receive sd clear threshold ? byte 1 (address location= 0xn146, where n ranges in value from 0x05 to 0x07) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 sd_clear_threshold[15:8] r/w r/w r/w r/w r/w r/w r/w r/w 1 1 1 1 1 1 1 1 b it n umber n ame t ype d escription 7 - 0 sd_clear_threshold [15:8] r/w sd_clear_threshold ? msb: these read/write bits, along the contents of the ?receive sts-1 transport ? sd clear threshold ? byte 0? registers permit the user to specify the upp er limit for the number of b2 byte errors that will cause the receive sts-1 toh processor block to clear the sd (signal degrade) defect condition. when the receive sts-1 toh processor block is checking the incoming sts-1 signal in order to determine if it should clear the sd defect condition, it will accumulate b2 byte errors throughout the ?sd defect clearance monitoring period?. if the number of accumulated b2 byte errors is less than that programmed into this and the ?receive sts-1 transport sd clear threshold ? byte 0? register, then the receive sts-1 toh processor block will clear the sd defect condition.
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 682 table 491: receive sts-1 transport ? receive sd clear threshold ? byte 1 (address location= 0xn147, where n ranges in value from 0x05 to 0x07) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 sd_clear_threshold[7:0] r/w r/w r/w r/w r/w r/w r/w r/w 1 1 1 1 1 1 1 1 b it n umber n ame t ype d escription 7 - 0 sd_clear_threshold[7:0] r/w sd_clear_threshold ? lsb: these read/write bits, along the contents of the ?receive sts-1 transport ? sd clear threshold ? byte 1? registers permit the user to specify the upper limit for the number of b2 byte errors that will cause the receive sts-1 toh processor block to clear the sd (signal degrade) defect condition. when the receive sts-1 toh processor block is checking the incoming sts-1 signal in order to determine if it should clear the sd defect condition, it will accumulate b2 byte errors throughout the ?sd defect clearance monitoring period?. if the number of accumulated b2 byte errors is less than that programmed into th is and the ?receive sts-1 transport sd clear threshold ? byte 1? register, then the receive sts-1 toh processor block will clear the sd defect condition. table 492: receive sts-1 transport ? force sef defect condition register (address location= 0xn14b, where n ranges in value from 0x05 to 0x07) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 unused sef force r/o r/o r/o r/o r/o r/o r/o r/w 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 ? 1 unused r/o 0 sef force r/w sef defect condition force: this read/write bit-field permits the user to force the receive sts-1 toh processor block (within the corresponding channel) to declare the sef defect condition. the receive sts-1 toh processor block will then attempt to reacquire framing. writing a ?1? into this bit-field conf igures the receive sts-1 toh processor block to declare the sef defect. the receive sts-1 toh processor block will automatically set this bit-field to ?0? once it has reacquired framing (e.g., has detected two consecutive sts-1 fr ames with the correct a1 and a2 bytes).
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 683 table 493: receive sts-1 transport ? receive section trace message buffer control register (address location= 0xn14f, where n ranges in value from 0x05 to 0x07) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 unused receive section trace message buffer read select receive section trace message accept threshold section trace message alignment type receive section trace message length[1:0] r/o r/o r/o r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 ? 5 unused r/o 4 receive section trace message buffer read select r/w receive section trace message buffer read selection: this read/write bit-field permits a user to specify which of the following receive section trace message buffer segments that the microprocessor will read out, whenever it reads out the c ontents of the receive section trace message buffer. a. the ?actual? receive section trace message buffer. the ?actual? receive section trace message buffer contains the contents of the most recently received (and accepted) section trace message via the incoming sts-1 data-stream. b. the ?expected? receive section trace message buffer. the ?expected? receive section trace message buffer contains the contents of the section trace messa ge that the user ?expects? to receive. the contents of this parti cular buffer is usually specified by the user. 0 ? executing a read to the receive section trace message buffer address space, will return contents within the ?actual? receive section trace message? buffer. 1 ? executing a read to the receive section trace message buffer address space will return contents within the ?expected? receive section trace message buffer?. note: in the case of the receive sts-3 toh processor block, the ?receive section trace message buffer? is located at address location 0xn300 through 0xn33f (where n ranges in value from 0x05 through 0x07). 3 receive section trace message accept threshold r/w receive section trace message accept threshold: this read/write bit-field permits a user to select the number of consecutive times that the receive sts-1 toh pr ocessor block must receive a given section trace message, before it is a ccepted, as described below. once a given ?section trace message? has been accepted then it can be read out of the ?actual receive section trace message? buffer. 0 ? configures the receive sts-1 toh processor block to accept the incoming section trace message after it has received it the third time in succession. 1 ? configures the receive sts-1 toh processor block to accept the incoming section trace message after it has received in the fifth time in succession.
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 684 2 section trace message alignment type r/w section trace message alignment type: this read/write bit-field permits a user to specify how the receive sts-1 toh processor block will locate the boundary of the incoming section trace message within the incoming sts-1 data-stream, as indicated below. 0 ? configures the receive sts-1 toh pr ocessor block to expect the section trace message boundary to be denoted by a ?line feed? character. 1 ? configures the receive sts-1 toh pr ocessor block to expect the section trace message boundary to be denoted by the presence of a ?1? in the msb (most significant bit) of the very first byte (within the incoming section trace message). in this case, all of the remaining bytes (within the incoming section trace message) will each have a ?0? within their msbs. 1 - 0 receive section trace message length[1:0] r/w receive section trace message length[1:0]: these read/write bit-fields permit the user to specify the length of the section trace message that the rece ive sts-1 toh processor block will accept and load into the ?actual? receive section trace message buffer. the relationship between the content of t hese bit-fields and the corresponding receive section trace message length is presented below. receive section trace message length[1:0] resulting receive section trace message length (in terms of bytes) 00 1 byte 01 16 bytes 10/11 64 bytes
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 685 table 494: receive sts-1 transport ? receive sd burst error tolerance ? byte 1 (address location= 0xn152, where n ranges in value from 0x05 to 0x07) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 sd_burst_tolerance[15:8] r/w r/w r/w r/w r/w r/w r/w r/w 1 1 1 1 1 1 1 1 b it n umber n ame t ype d escription 7 - 0 sd_burst_tolerance [15:8] r/w sd_burst_tolerance ? msb: these read/write bits, along with the contents of the ?receive sts-1 transport ? sd burst tolerance ? byte 0? registers permit the user to s pecify the maximum number of b2 bit errors that the corresponding receive sts-1 toh processor block can accumulate during a single sub-interval period (e.g., an sts-1 frame period), when determining whether or not to declare the sd (signal degrade) defect condition. note: the purpose of this feature is to permit the user to provide some level of b2 by te error burst filtering, when the receive sts-1 toh processor block is accumulating b2 byte errors in order to declare the sd defect condition. the user can implement this feature in order to configure the receive sts-1 toh processor block to detect b2 bit errors in multiple ?sub-interval? periods before it will declare the sd defect condition.
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 686 table 495: receive sts-1 transport ? receive sd burst error tolerance ? byte 0 (address location= 0xn153, where n ranges in value from 0x05 to 0x07) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 sd_burst_tolerance[7:0] r/w r/w r/w r/w r/w r/w r/w r/w 1 1 1 1 1 1 1 1 b it n umber n ame t ype d escription 7 - 0 sd_burst_tolerance[7:0] r/w sd_burst_tolerance ? lsb: these read/write bits, along with the contents of the ?receive sts-1 transport ? sd burst tolerance ? byte 1? registers permit the user to specify the maximum number of b2 bit errors that the corresponding receive sts-1 toh processor block can accumulate during a single sub-interval period (e.g., an sts-1 frame period), when determining whether or not to declare the sd (signal degrade) defect condition. note: the purpose of this feature is to permit the user to provide some level of b2 byte error burst filtering, when the receive sts-1 toh processor block is accumulating b2 byte errors in order to declare the sd defect condition. the user can implement this feature in order to conf igure the receive sts-1 toh processor block to detect b2 bit errors in multiple ?sub-interval? periods before it will declare the sd defect condition.
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 687 table 496: receive sts-1 transport ? receive sf burst error tolerance ? byte 1 (address location= 0xn156, where n ranges in value from 0x05 to 0x07) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 sf_burst_tolerance[15:8] r/w r/w r/w r/w r/w r/w r/w r/w 1 1 1 1 1 1 1 1 b it n umber n ame t ype d escription 7 - 0 sf_burst_tolerance[15:8] r/w sf_burst_tolerance ? msb: these read/write bits, along with the contents of the ?receive sts-1 transport ? sf burst tolerance ? byte 0? registers permit the user to specify the maximum number of b2 bit errors that the corresponding receive sts-1 toh processor block can accumulate during a single sub-interval period (e.g., an sts-1 frame period), when determining whether or not to declare the sf (signal failure) defect condition. note: the purpose of this feature is to permit the user to provide some level of b2 by te error burst filtering, when the receive sts-1 toh processor block is accumulating b2 byte errors in order to declare the sf defect condition. the user can implement this feature in order to configure the receive sts-1 toh processor block to detect b2 bit errors in multiple ?sub-interval? per iods before it will declare the sf defect condition.
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 688 table 497: receive sts-1 transport ? receive sf burst error tolerance ? byte 0 (address location= 0xn157, where n ranges in value from 0x05 to 0x07) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 sf_burst_tolerance[7:0] r/w r/w r/w r/w r/w r/w r/w r/w 1 1 1 1 1 1 1 1 b it n umber n ame t ype d escription 7 - 0 sf_burst_tolerance[7:0] r/w sf_burst_tolerance ? lsb: these read/write bits, along with the contents of the ?receive sts-1 transport ? sf burst tolerance ? byte 1? registers permit the user to specify the maximum number of b2 bit errors that the corresponding receive sts-1 toh processor block can accumulate during a single sub-interval period (e.g., an sts-1 frame period), when determining whether or not to declare the sf (signal failure) defect condition. note: the purpose of this feature is to permit the user to provide some level of b2 byte error bur st filtering, when the receive sts-1 toh processor block is accumulating b2 byte errors in order to declare the sf defect condition. the user can implement this feature in order to configure the receive sts-1 toh processor block to detect b2 bit errors in multiple ?sub- interval? periods before it will declare the sf defect condition.
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 689 table 498: receive sts-1 transport ? receive sd cl ear monitor interval ? byte 2 (address location= 0xn159, where n ranges in value from 0x05 to 0x07) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 sd_clear_monitor_window[23:16] r/w r/w r/w r/w r/w r/w r/w r/w 1 1 1 1 1 1 1 1 b it n umber n ame t ype d escription 7 - 0 sd_clear_monitor_window [23:16] r/w sd_clear_monitor_interval ? msb: these read/write bits, along the contents of the ?receive sts-1 transport ? sd clear monitor interval ? byte 1 and byte 0? registers permit the user to specify the length of the ?monitoring period? (in terms of ms) for sd (signal degrade) defect clearance. when the receive sts-1 toh processor block is checking the incoming sts-1 signal in order to determine if it should clear the sd defect condition, it will accumulate b2 byte errors throughout the user-specified ?sd defect clearance? monitoring period. if, during this ?sd defect clearance? monitoring period, the receive sts-1 toh processor block accumulates less b2 byte errors than that programmed into the ?receive sts-1 transport sd clear threshold? register, then the receive sts-1 toh processor block will clear the sd defect condition. notes: 1. the value that the user writes into these three (3) ?sd clear monitor window? registers, specifies the duration of the ?s d defect clearance monitoring period?, in terms of ms. 2. this particular register byte contains the ?msb? (most significant byte) value of the three registers that specifiy the ?sd defect clearance monitoring? period.
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 690 table 499: receive sts-1 transport ? receive sd cl ear monitor interval ? byte 1 (address location= 0xn15a, where n ranges in value from 0x05 to 0x07) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 sd_clear_monitor_window[15:8] r/w r/w r/w r/w r/w r/w r/w r/w 1 1 1 1 1 1 1 1 b it n umber n ame t ype d escription 7 - 0 sd_clear_monitor_window [15:8] r/w sd_clear_monitor_interval ? bits 15 through 8: these read/write bits, along the contents of the ?receive sts-1 transport ? sd clear monitor interval ? byte 2 and byte 0? registers permit the user to specify the length of the ?monitoring period? (in terms of ms) for sd (signal degrade) defect clearance. when the receive sts-1 toh processor block is checking the incoming sts-1 signal in order to determine if it should clear the sd defect condition, it will accumulate b2 byte errors throughout the user-specified ?sd defect clearance? monitori ng period. if, during this ?sd defect clearance monitoring period?, the receive sts-1 toh processor block accumulates less b2 byte errors than that programmed into the ?receive sts-1 transport sd clear threshold? register, then the receive sts-1 toh processor block will clear the sd defect condition. notes: the value that the user writes into these three (3) ?sd clear monitor window? registers, specifies the duration of the ?sd defect clearance monitoring period?, in terms of ms.
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 691 table 500: receive sts-1 transport ? receive sd cl ear monitor interval ? byte 0 (address location= 0xn15b, where n ranges in value from 0x05 to 0x07) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 sd_clear_monitor_window[7:0] r/w r/w r/w r/w r/w r/w r/w r/w 1 1 1 1 1 1 1 1 b it n umber n ame t ype d escription 7 - 0 sd_clear_monitor_window [7:0] r/w sd_clear_monitor_interval ? lsb: these read/write bits, along the contents of the ?receive sts-1 transport ? sd clear monitor interval ? byte 2 and byte 1? registers permit the user to specify the length of the ?monitoring period? (in terms of ms) for sd (signal degrade) defect clearance. when the receive sts-1 toh processor block is checking the incoming sts-1 signal in order to determine if it should clear the sd defect condition, it will accumulate b2 byte errors throughout the user-specified ?sd defect clearance? monitoring period. if, during this ?sd defect clearance monitoring period, the receive sts-1 toh processor block accumulates less b2 byte errors than that programmed into the ?receive sts-1 transport sd clear threshold? register, then the receive sts-1 toh processor block will clear the sd defect condition. notes: 1. the value that the user writes into these three (3) ?sd clear monitor window? registers, specifies the duration of the ?sd defect clearance monitoring period?, in terms of ms. 2. this particular register byte contains the ?lsb? (least significant byte) value of the three registers that specify the ?sd defect clearance monitoring? period.
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 692 table 501: receive sts-1 transport ? receive sf cl ear monitor interval ? byte 2 (address location= 0xn15d, where n ranges in value from 0x05 to 0x07) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 sf_clear_monitor_window[23:16] r/w r/w r/w r/w r/w r/w r/w r/w 1 1 1 1 1 1 1 1 b it n umber n ame t ype d escription 7 - 0 sf_clear_monitor_window [23:16] r/w sf_clear_monitor_interval ? msb: these read/write bits, along the contents of the ?receive sts-1 transport ? sf clear monitor interval ? byte 1 and byte 0? registers permit the user to specify the length of the ?monitoring period? (in terms of ms) for sf (signal failure) defect clearance. when the receive sts-1 toh processor block is checking the incoming sts-1 signal in order to determine if it should clear the sf defect condition, it will accumulate b2 byte errors throughout the user-spe cified ?sf defect clearance? monitoring period. if, during this ?sf defect clearance? monitoring period, the receive sts-1 toh processor block accumulates less b2 byte errors than that programmed into the ?receive sts-1 transport sf clear threshold? register, then the receive sts-1 toh processor block will clear the sf defect condition. notes: 1. the value that the user writes into these three (3) ?sf clear monitor window? registers, specifies the duration of the ?sf defect clearance monitoring period?, in terms of ms. 2. this particular register byte contains the ?msb? (most significant byte) value of the three registers that specify the ?sf defect clearance monitoring? period.
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 693 table 502: receive sts-1 transport ? receive sf cl ear monitor interval ? byte 1 (address location= 0xn15e, where n ranges in value from 0x05 to 0x07) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 sf_clear_monitor_window[15:8] r/w r/w r/w r/w r/w r/w r/w r/w 1 1 1 1 1 1 1 1 b it n umber n ame t ype d escription 7 - 0 sf_clear_monitor_window [15:8] r/w sf_clear_monitor_interval ? bits 15 through 8: these read/write bits, along the contents of the ?receive sts-1 transport ? sf clear monitor interval ? byte 2 and byte 0? registers permit the user to specify the length of the ?monitoring period? (in terms of ms) for sf (signal failure) defect clearance. when the receive sts-1 toh processor block is checking the incoming sts-1 signal in order to determine if it should clear the sf defect condition, it will accumulate b2 byte errors throughout the user-specified ?sf defect clearance? moni toring period. if, during this ?sf defect clearance? monitoring period, the receive sts-1 toh processor block accumulates less b2 byte errors than that programmed into the ?receive sts-1 transport sf clear threshold? register, then the receive sts-1 toh processor block will clear the sf defect condition. notes: the value that the user writes into these three (3) ?sf clear monitor window? registers, specifies the duration of the ?sf defect clearance monitoring period?, in terms of ms.
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 694 table 503: receive sts-1 transport ? receive sf cl ear monitor interval ? byte 0 (address location= 0xn15f, where n ranges in value from 0x05 to 0x07) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 sf_clear_monitor_window[7:0] r/w r/w r/w r/w r/w r/w r/w r/w 1 1 1 1 1 1 1 1 b it n umber n ame t ype d escription 7 - 0 sf_clear_monitor_window [7:0] r/w sf_clear_monitor_interval ? lsb: these read/write bits, along the contents of the ?receive sts-1 transport ? sf clear monitor interval ? byte 2 and byte 1? registers permit the user to specify the length of the ?monitoring period? (in terms of ms) for sf (signal failure) defect clearance. when the receive sts-1 toh processor block is checking the incoming sts-1 signal in order to determine if it should clear the sf defec t condition, it will accumulate b2 byte errors throughout the user-specified ?sf defect clearance? moni toring period. if, duri ng this ?sf defect clearance monitoring? period, the receive sts-1 toh processor block accumulates less b2 byte errors than that programmed into the ?receive sts-1 transport sf clear threshold? register, then the receive sts-1 toh processor block will clear the sf defect condition. notes: 1. the value that the user writes into these three (3) ?sf clear monitor window? registers, specifies the duration of the ?sf defect clearance monitoring period?, in terms of ms. 2. this particular register byte contains the ?lsb? (least significant byte) value of the three registers that specify the ?sf defect clearance monitoring? period.
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 695 table 504: receive sts-1 transport ? auto ais c ontrol register (address location= 0xn163, where n ranges in value from 0x05 to 0x07) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 transmit ais-p (down- stream) upon section trace message unstable transmit ais-p (down- stream) upon section trace message mismatch transmit ais-p (down- stream) upon sf transmit ais-p (down- stream) upon sd unused transmit ais-p (down- stream) upon lof transmit ais-p (down- stream) upon los transmit ais-p (down- stream) enable r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 transmit ais-p (down- stream) upon section trace message unstable r/w transmit path ais upon declaration of the section trace message unstable defect condition: this read/write bit-field permits the user to configure the receive sts-1 toh processor block to autom atically transmit the path ais (ais-p) indicator via the ?downs tream? traffic (e .g., towards the corresponding receive sts-1 poh processor block), anytime it declares the section trace message un stable defect condition within the ?incoming? sts-1 data-stream. 0 ? does not configure the receiv e sts-1 toh processor block to automatically transmit the ais-p indicator (via the ?downstream? traffic) whenever (and for the durat ion that) it declares the ?section trace message unstable? defect condition. 1 ? configures the receive sts-1 toh processor block to automatically transmit the ais-p indicator (via the ?downstream? traffic) whenever (and for the durat ion that) it declares the ?section trace message unstable? defect condition. note: the user must also set bit 0 (transmit ais-p enable) to ?1? to configure the receive sts-1 toh processor block to automatically transmit the ais-p indicator, in response to this defect condition. 6 transmit ais-p (down- stream) upon section trace message mismatch r/w transmit path ais (ais-p) upon declaration of the section trace message mismatch defect condition: this read/write bit-field permits the user to configure the receive sts-1 toh processor block to autom atically transmit the path ais (ais-p) indicator via the ?downs tream? traffic (e .g., towards the corresponding receive sts-1 poh pr ocessor blocks), anytime (and for the duration that) it declar es the section trace message mismatch defect condition within the ?incoming? sts-1 data stream. 0 ? does not configure the receiv e sts-1 toh processor block to automatically transmit the ais-p indicator (via the ?downstream? traffic) whenever it declares t he ?section trace mismatch? defect condition. 1 ? configures the receive sts-1 toh processor block to automatically transmit the ais-p indicator (via the ?downstream? traffic) whenever (and for the durat ion that) it declares the ?section trace message mismatch? defect condition. note: the user must also set bit 0 ( transmit ais - p enable ) to ?1?
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 696 to configure the receive sts-1 toh processor block to automatically transmit the ais-p indicator, in response to this defect condition. 5 transmit ais-p (down- stream) upon sf r/w transmit path ais upon declaration of the signal failure (sf) defect condition: this read/write bit-field permits the user to configure the receive sts-1 toh processor block to automatically transmit a path ais (ais-p) indicator via the ?downs tream? traffic (e .g., towards the corresponding receive sts-1 poh processor block), anytime (and for the duration that) it decla res the sf defect condition. 0 ? does not configure the receiv e sts-1 toh processor block to transmit the ais-p indicator (via the ?downstream? traffic) upon declaration of the sf defect. 1 ? configures the receive sts-1 toh processor block to automatically transmit the ais-p indicator (via the ?downstream? traffic) anytime (and for the durati on that) it declares the sf defect condition. note: the user must also set bit 0 (transmit ais-p enable) to ?1? to configure the receive sts-1 toh processor block to automatically transmit the ais-p indicator, in response to this defect condition. 4 transmit ais-p (down- stream) upon sd r/w transmit path ais upon declaration of the signal degrade (sd) defect: this read/write bit-field permits the user to configure the receive sts-1 toh processor block to automatically transmit a path ais (ais-p) indicator via the ?downs tream? traffic (e .g., towards the corresponding receive sts-1 poh processor block) anytime (and for the duration that) it decla res the sd defect condition. 0 ? does not configure the receiv e sts-1 toh processor block to transmit the ais-p indicator (via the ?downstream? traffic) upon declaration of the sd defect. 1 ? configures the receive sts-1 toh processor block to automatically transmit the ais-p indicator (via the ?downstream? traffic) anytime (and for the duration that) it declares the sd defect condition. note: the user must also set bit 0 (transmit ais-p enable) to ?1? to configure the receive sts-1 toh processor block to automatically transmit the ais-p indicator, in response to this defect condition. 3 unused r/o 2 transmit ais-p (down- stream) upon lof r/w transmit path ais upon declaration of the loss of frame (lof) defect: this read/write bit-field permits the user to configure the receive sts-1 toh processor block to automatically transmit a path ais (ais-p) indicator via the ?downs tream? traffic (e .g., towards the corresponding receive sts-1 poh processor block), anytime (and for the duration that) it decla res the lof defect condition. 0 ? does not configure the receiv e sts-1 toh processor block to transmit the ais-p indicator (via the ?downstream? traffic) upon declaration of the lof defect. 1 ? configures the receive sts-1 toh processor block to automatically transmit the ais-p indicator (via the ?downstream? traffic ) an y time ( and for the duration that ) it declares the lof defect
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 697 condition. note: the user must also set bit 0 (transmit ais-p enable) to ?1? to configure the receive sts-1 toh processor block to automatically transmit the ais-p indicator, in response to this defect condition. 1 transmit ais-p (down- stream) upon los r/w transmit path ais upon declaration of the loss of signal (los) defect: this read/write bit-field permits the user to configure the receive sts-1 toh processor block to automatically transmit a path ais (ais-p) indicator via the ?downs tream? traffic (e .g., towards the corresponding receive sts-1 poh processor block), anytime (and for the duration that) it decla res the los defect condition. 0 ? does not configure the receiv e sts-1 toh processor block to transmit the ais-p indicator (via th e ?downstream? traffic) anytime it declares the los defect condition. 1 ? configures the receive sts-1 toh processor block to automatically transmit the ais-p indicator (via the ?downstream? traffic) anytime (and for the durati on that) it declares the los defect condition. note: the user must also set bit 0 (transmit ais-p enable) to ?1? to configure the receive sts-1 toh processor block to automatically transmit the ais-p indicator, in response to this defect condition. 0 auto ais r/w automatic transmission of ais-p enable: this read/write bit-field serves two purposes. it permits the user to configure the receive sts-1 toh processor block to automatically transmit the path ais (ais-p) indicator, via the down-stream traffic (e.g., towards the receive sts-1 poh processor block), upon detection of an sf, sd, section trace mismatch, section trace unstable, lof or los defect conditions. it also permits the user to configure the receive sts-1 toh processor block to automatically transmit a path ais (ais-p) indicator via the ?downstream? traffi c (e.g., towards the receive sts- 1 poh processor block) anytime it declares the ais-l defect condition within the ?incoming? sts-1 datastream. 0 ? configures the receive sts-1 toh processor block to not automatically transmit the ais-p indicator (via the ?downstream? traffic) upon declaration of the ais- l defect condition or any of the ?above-mentioned? defect conditions. 1 ? configures the receive sts-1 toh processor block to automatically transmit the ais-p indicator (via the ?downstream? traffic) upon declaration of the ai s-l defect or any of the ?above- mentioned? defect conditions. note: the user must also set the corresponding bit-fields (within this register) to ?1? in order to configure the receive sts-1 toh processor block to automatically transmit the ais-p indicator upon declaration of a given alarm/defect condition.
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 698 table 505: receive sts-1 transport ? auto ais (in downstream sts-1s) control register (address location= 0xn16b, where n ranges in value from 0x05 to 0x07) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 unused transmit ais- p (via downstream sts-1s) upon los transmit ais- p (via downstream sts-1s) upon lof transmit ais- p (via downstream sts-1s) upon sd transmit ais- p (via downstream sts-1s) upon sf unused transmit ais-p (via downstream sts-1s) enable r/o r/o r/w r/w r/w r/w r/o r/w 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 - 6 unused r/o 5 transmit ais-p (via downstream sts-1s) upon los r/w transmit ais-p (via downstream sts-1s) upon declaration of the los (loss of signal) defect condition: this read/write bit-field permits the user to configure the transmit sonet poh processor block (in the corresponding channel) to automatically transmit the ais-p (path ais) indicator via the ?downstream? sts-1 signal (within the outbound sts-3 signal), anytime (and for the duration that) the re ceive sts-1 toh processor block declares the los defect condition. 0 ? does not configure the corresponding transmit sonet poh processor blocks to automatically tr ansmit the ais-p indicator via the ?downstream? sts-1 signal (within the outbound sts-3 signal), anytime the receive sts-1 toh processor block declares the los defect condition. 1 ? configures the corresponding transmit sonet poh processor blocks to automatically transmi t the ais-p indicator via the ?downstream? sts-1 signals (within the outbound sts-3 signal), anytime (and for the duration that ) the receive sts-1 toh processor block declares the los defect condition. note: 1. in the ?long-run? the function of this bit-field is exactly the same as that of bit 1 (transmit ais-p down-stream ? upon los), within the receive sts-1 transport ? auto ais control register (address location= 0xn163). the only differenc e is that this register bit will cause the corresponding ?downstream? transmit sonet poh processor block to immediately begin to transmit the ais-p condition whenever the receive sts-1 toh processor block declares the los defect. this will permit the user to easily comply with the telcordia gr- 253-core requirements of an ne transmitting the ais-p indicator downstream within 125us of the ne declaring the los defect. in the case of bit 1 (transmit ais-p downstream ? upon los), several sonet frame periods are required (after the receive sts-1 toh processor block has declared the los defect), before the corresponding transmit sonet poh processor block will begin the process of transmitting the ais-p indicator. 2. in addition to setting this bit-field to ?1?, the user must also set bit 0 (transmit ais-p via downstream sts-1s enable) within this register, in order enable this feature. 4 transmit ais-p (via downstream sts-1s) upon lof r/w transmit ais-p (via downstream sts-1s) upon declaration of the lof (loss of frame) defect condition:
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 699 this read/write bit-field permits the user to configure the transmit sonet poh processor block (in the corresponding channel) to automatically transmit the ais-p (path ais) indicator via the ?downstream? sts-1 signal (within the outbound sts-3 signal), anytime (and for the duration that) the re ceive sts-1 toh processor block declares the lof defect condition. 0 ? does not configure the corresponding transmit sonet poh processor block to automatically tr ansmit the ais-p indicator via the ?downstream? sts-1 signals (within the outbound sts-3 signal), anytime the receive sts-1 toh pr ocessor block declares the lof defect condition. 1 ? configures the corresponding transmit sonet poh processor block to automatically transmit the ais-p indicator via the ?downstream? sts-1 signals (within the outbound sts-3 signal), anytime (and for the duration that) the receive sts-1 to h processor block declares the lof defect condition. note: 1. in the ?long-run? the function of this bit-field is exactly the same as that of bit 2 (transmit ais-p down-stream ? upon lof), within the receive sts-1 transport ? auto ais control register (address location= 0xn163). the only differenc e is that this register bit will cause the corresponding ?downstream? transmit sonet poh processor blocks to immediately begin to transmit the ais-p condition whenever the receive sts-1 toh processor block declares the lof defect. this will permit the user to easily comply with the telcordia gr-253-core requirements of an ne transmitting the ais-p indicator downstream within 125us of the ne declaring the lof defect. in the case of bit 2 (transmit ais-p downstream ? upon lof), several sonet frame periods are required (after the receive sts-3 toh processor block has declared the los defect), before the corresponding transmit sonet poh processor block will begin the process of transmitting the ais-p indicator. 2. in addition to setting this bit-field to ?1?, the user must also set bit 0 (transmit ais-p via downstream sts-1s enable) within this register, in order enable this feature. 3 transmit ais-p (via downstream sts-1s) upon sd r/w transmit ais-p (via downstream sts-1s) upon declaration of the sd (signal degrade) defect condition: this read/write bit-field permits the user to configure the transmit sonet poh processor block (in the corresponding channel) to automatically transmit the ais-p (path ais) indicator via the ?downstream? sts-1 signals (within the outbound sts-3 signal), anytime (and for the duration that ) the receive sts-1 toh processor block declares the sd defect condition. 0 ? does not configures the corresponding transmit sonet poh processor block to automatically tr ansmit the ais-p indicator via the ?downstream? sts-1 signals (within the outbound sts-3 signal), anytime the receive sts-1 toh processor block declares the sd defect condition. 1 ? configures the corresponding transmit sonet poh processor block to automatically transmit the ais-p indicator via the ?downstream? sts-1 signal (within the outbound sts-3 signal), anytime (and for the duration that) the receive sts-1 toh processor block declares the sd defect condition. note: 1. in the ?long-run? the function of this bit-field is exactly the same as that of bit 4 ( transmit ais-p down - stream ? u p on sd ) , within the
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 700 receive sts-1 transport ? auto ais control register (address location= 0xn163). the only differenc e is that this register bit will cause the corresponding ?downstream? transmit sonet poh processor blocks to immediately begin to transmit the ais-p condition whenever the receive sts-1 toh processor block declares the sd defect. this will permit t he user to easily comply with the telcordia gr-253-core requirements of an ne transmitting the ais-p indicator downstream within 125us of the ne declaring the los defect. in the case of bit 1 (transmit ais-p downstream ? upon lof), several sonet frame periods are required (after the receive sts-1 toh processor block has declared the sd defect), before the corresponding transmit sonet poh processor block will begin the process of transmitting the ais-p indicator. 2. in addition to setting this bit-field to ?1?, the user must also set bit 0 (transmit ais-p via downstream sts-1s enable) within this register, in order enable this feature. 2 transmit ais-p (via downstream sts-1s) upon sf r/w transmit ais-p (via downstream sts-1s) upon declaration of the signal failure (sf) defect condition: this read/write bit-field permits the user to configure the transmit sonet poh processor block (in the corresponding channel) to automatically transmit the ais-p (path ais) indicator via the ?downstream? sts-1 signal (within the outbound sts-3 signal), anytime (and for the duration that)) the re ceive sts-1 toh processor block declares the sf defect condition. 0 ? does not configures the corresponding transmit sonet poh processor block to automatically tr ansmit the ais-p indicator via the ?downstream? sts-1 signal (within the outbound sts-3 signal), anytime the receive sts-1 toh processor block declares the sf defect condition. 1 ? configures the corresponding transmit sonet poh processor block to automatically transmit the ais-p indicator via the ?downstream? sts-1 signal (within the outbound sts-3 signal), anytime (and for the duration that) the receive sts-1 toh processor block declares the sf defect condition. note: in the ?long-run? the function of this bit-field is exactly the same as that of bit 5 (transmit ais-p do wn-stream ? upon sf), within the receive sts-1 transport ? auto ais control register (address location= 0xn163). the only differenc e is that this register bit will cause the corresponding ?downstream? transmit sonet poh processor blocks to immediately begin to transmit the ais-p condition whenever the receive sts-1 toh processor block declares the sf defect. this will permit t he user to easily comply with the telcordia gr-253-core requirements of an ne transmitting the ais-p indicator downstream within 125us of the ne declaring the sf defect. in the case of bit 5 (transmit ais-p downstream ? upon sf), several sonet frame periods are required (after the receive sts-1 toh processor block has declared the sf defect), before the corresponding transmit sonet poh processor blocks will begin the process of transmitting the ais-p indicator. 2. in addition to setting this bit-field to ?1?, the user must also set bit 0 (transmit ais-p via downstream sts-1s enable) within this register, in order enable this feature. 1 unused r/o 0 transmit ais-p (via downstream sts-1s ) r/w automatic transmission of ais-p (via the downstream sts-1s) enable :
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 701 enable enable : this read/write bit-field serves two purposes. it permits the user to configure the corresponding transmit sonet poh processor block to automatically transmit the ais-p indicator, via its ?outbound? sts-1 signal (withi n the outbound sts-3 signal), upon declaration of either the sf, sd, los or lof defect conditions via the receive sts-1 toh processor block. it also permits the user to configure the corresponding transmit sonet poh processor block to automatically transmit the ais-p indicator, via its ?outbound? sts-1 signal (withi n the outbound sts-3 signal), upon declaration of the ais-l defect cond ition, via the receive sts-1 toh processor block. 0 ? does not configure the corresponding transmit sonet poh processor block to automatically trans mit the ais-p indicator, whenever the receive sts-1 toh processor blo ck declares either the los, lof, sd, sf or ais-l defect conditions. 1 ? configures the corresponding transmit sonet poh processor block to automatically transmit the ais-p indicator, whenever (and for the duration that) the receive st s-1 toh processor block declares either the los, lof, sd, sf or ais-l defect conditions.
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 702 table 506: receive sts-1 path ? control register ? byte 2 (address location= 0xn183, where n ranges in value from 0x05 to 0x07) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 unused check stuff rdi-p type rei-p error type b3 error type r/o r/o r/o r/o r/w r/w r/w r/w 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 - 4 unused r/o 3 check stuff r/w check (pointer adjustment) stuff select: this read/write bit-field permits the user to enable/disable the sonet standard recommendation that a pointer increment or decrement operation, detected within 3 sonet frames of a pr evious pointer adju stment operation (e.g., negative stuff, positive stuff) is ignored. 0 ? disables this sonet standard implemen tation. in this mode, all pointer- adjustment operations that are detected will be accepted. 1 ? enables this ?sonet standard? implem entation. in this mode, all pointer- adjustment operations that are detected within 3 sonet frame periods of a previous pointer-adjustment operation will be ignored. 2 rdi-p type r/w path - remote defect indicator type select: this read/write bit-field permits the user to configure the receive sts-1 poh processor block to support either the ?single-bit? or the ?enhanced? rdi- p form of signaling, as described below. 0 ? configures the receive sts-1 poh processor block to support single-bit rdi-p. in this mode, the receive sts-1 poh processor block will only monitor bit 5, within the g1 byte (of the incoming spe data), in order to declare and clear the rdi-p defect condition. 1 ? configures the receive sts-1 poh processor block to support enhanced rdi-p (erdi-p). in this mode, the re ceive sts-1 poh processor block will monitor bits 5, 6 and 7, within the g1 byte, in order to declare and clear the rdi-p defect condition. 1 rei-p error type r/w rei-p error type: this read/write bit-field permits the user to specify how the receive sts-1 poh processor block will count (or tally) rei-p events, for performance monitoring purposes. the user can configure the receive sts-1 poh processor block to increment rei-p events on either a ?per-bit? or ?per-frame? basis. if the user configures the receive sts-1 poh processor block to increment rei-p events on a ?per-bit? basis , then it will increment the ?receive sts-1 path rei-p error count? register by the value of the lower nibble within the g1 byte of the incoming sts-1 data-stream. if the user configures the receive sts-1 poh processor block to increment rei-p events on a ?per-frame? basis, then it will increment the ?receive sts-1 path rei-p error count? register each time it receives an sts-1 frame, in which the lower nibble of the g1 byte (bits 1 through 4) are set to a ?non-zero? value. 0 ? configures the receive sts-1 poh pr ocessor block to count or tally rei- p events on a per-bit basis. 1 ? confi g ures the receive sts-1 poh processor block to count or tall y rei-
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 703 p events on a ?per-frame? basis. 0 b3 error type r/w b3 error type: this read/write bit-field permits the user to specify how the receive sts-1 poh processor block will count (or tally) b3 byte errors, for performance monitoring purposes. the user c an configure the receive sts-1 poh processor block to increment b3 byte erro rs on either a ?per-bit? or ?per-frame? basis. if the user configures the receive sts-1 poh processor block to increment b3 byte errors on a ?per-b it? basis, then it will increment the ?receive sts-1 path b3 byte error count? register by the number of bits (within the b3 byte value of the incomi ng sts-1 data-stream) that is in error. if the user configures the receive sts-1 poh processor block to increment b3 byte errors on a ?per-frame? basis, then it will increment the ?receive sts- 1 path - b3 byte error count? regist er each time it receives an sts-1 spe that contains an erred b3 byte. 0 ? configures the receive sts-1 poh processor block to count b3 byte errors on a ?per-bit? basis 1 ? configures the receive sts-1 poh processor block to count b3 byte errors on a ?per-frame? basis.
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 704 table 507: receive sts-1 path ? control register ? byte 1 (address location= 0xn186, where n ranges in value from 0x05 to 0x07) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 unused path trace message unstable defect declared r/o r/o r/o r/o r/o r/o r/o r/o 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 ? 1 unused r/o 0 path trace message unstable defect declared r/o path trace message unstable defect declared: this read-only bit-field indicates wh ether or not the receive sts-1 poh processor block is currently declaring the path trace message unstable defect condition. the receive sts-1 poh proces sor block will declare the path trace message unstable defect condition, whenever the ?path trace message unstable? counter reaches the value ?8?. the ?path trace message unstable? counter will be incremented for each time th at it receives a path trace message that differs from the previously rece ived message. the ?path trace unstable? counter is cleared to ?0? whenever the receive sts-1 poh processor block has received a given path trace message 3 (or 5) consecutive times. note: receiving a given path trace message 3 (or 5) consecutive times also sets this bit-field to ?0?. 0 ? indicates that the receive sts-1 poh processor block is not currently declaring the path trace mess age unstable defect condition. 1 ? indicates that the receive sts-1 poh processor blolck is currently declaring the path trace message un stable defect condition.
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 705 table 508: receive sts-1 path ? sonet receive poh status ? byte 0 (address location= 0xn187, where n ranges in value from 0x05 to 0x07) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 tim-p defect declared c2 byte unstable defect declared uneq-p defect declared plm-p defect declared rdi-p defect declared rdi-p unstable condition lop-p defect declared ais-p defect declared r/o r/o r/o r/o r/o r/o r/o r/o 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 tim-p defect declared r/o trace identification mismatch (tim-p) defect indicator: this read-only bit-field indicates whether or not the receive sts-1 poh processor block is currently declaring t he ?path trace identif ication mismatch? (tim-p) defect condition. the receive sts-1 poh processor block will declare the ?tim-p? defect condition, when none of the received 64- byte string (received via the j1 byte, within the incoming sts-1 data-stream) matches the expected 1, 16 or 64-byte message. the receive sts-1 poh processor block will clear the ?tim-p? defect condition, when 80% of the received 1, 16 or 64-byte string (received via the j1 byte) matches the expected 1, 16 or 64-byte message. 0 ? indicates that the receive sts-1 poh processor block is not currently declaring the tim-p defect condition. 1 ? indicates that the receive sts-1 poh processor block is currently declaring the tim-p defect condition. 6 c2 byte unstable defect declared r/o c2 byte (path signal label byte) unstable defect declared: this read-only bit-field indicates whether or not the receive sts-1 poh processor block is currently declaring t he ?path signal label byte? unstable defect condition. the receive sts-1 poh processor block will declare the c2 (path signal label byte) unstable defect co ndition, whenever the ?c2 byte unstable? counter reaches the value ?5?. the ?c2 byte unstable? counter will be incremented for each time that it receives an spe with a c2 byte value that differs from the previously received c2 byte value. the ?c2 byte unstable? counter is cleared to ?0? whenever the receive sts-1 poh processor block has received 3 (or 5) consecutive spes that each contains the same c2 byte value. note: receiving a given c2 byte value in 3 (or 5) consecutive spes also sets this bit-field to ?0?. 0 ? indicates that the receive sts-1 poh processor block is currently not declaring the c2 (path signal label byte) unstable defect condition. 1 ? indicates that the receive sts-1 poh processor block is currently declaring the c2 (path signal label byte) unstable defect condition. 5 uneq-p defect declared r/o path ? unequipped (uneq-p) defect declared: this read-only bit-field indicates whether or not the receive sts-1 poh processor block is currently declari ng the uneq-p defect condition. the receive sts-1 poh processor block will declare the uneq-p defect condition anytime that it receives at le ast five (5) consecutive sts-1 frames, in which the c2 b y te was set to the value ?0x00? ( which indicates that the spe is
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 706 ?unequipped?). the receive sts-1 poh processor block will clear the uneq-p defect condition, if it receives at least five (5) consecut ive sts-1 frames, in which the c2 byte was set to a value other than 0x00. 0 ? indicates that the receive sts-1 poh processor block is currently not declaring the uneq-p defect condition. 1 ? indicates that the receive sts-1 poh processor block is currently declaring the uneq-p defect condition. note: the receive sts-1 poh processor block will not declare the uneq-p defect condition if it configured to expect to receive sts-1 frames with c2 bytes being set to ?0x00? (e.g ., if the ?receive sts-1 path ? expected path label value? register is set to ?0x00?). 4 plm-p defect declared r/o path payload mismatch (plm-p) defect declared: this read-only bit-field indicates whether or not the receive sts-1 poh processor block is currently decl aring the plm-p defect condition. the receive sts-1 poh processor block will declare the plm-p defect condition, if it receives at least five (5) consecut ive sts-1 frames, in which the c2 byte was set to a value other than that which it is expecting to receive. whenever the receive sts-1 poh processor block is determining whether or not it should declare the plm-p defect, it will check the contents of the following two registers. ? the ?receive sts-1 path ? received path label value? register (address location= 0xn196). ? the ?receive sts-1 path ? expected path label value? register (address location= 0xn197). the ?receive sts-1 path ? expected path label value? register contains the value of the c2 bytes, t hat the receive sts-1 poh pr ocessor blocks expects to receive. the ?receive sts-1 path ? received path label value? register contains the value of the c2 byte, that the receiv e sts-1 poh processor block has most received ?validated? (by receiving this same c2 byte in five consecutive sts-1 frames). the receive sts-1 poh processor block will declare the plm-p defect condition if the contents of these two register do not match. the receive sts-1 poh processor block will clear the plm-p defec t condition if whenever the contents of these two registers do match. 0 ? indicates that the receive sts-1 poh processor block is currently not declaring the plm-p defect condition. 1 ? indicates that the receive sts-1 poh processor block is currently declaring the plm-p defect condition. note: the receive sts-1 poh processor block will clear the plm-p defect, upon declaring the uneq-p defect condition. 3 rdi-p defect declared r/o path remote defect indicator (rdi-p) defect declared: this read-only bit-field indicates whether or not the receive sts-1 poh processor block is currently declaring the rdi-p defect condition. if the receive sts-1 poh processor block is configured to support the ?single-bit rdi-p? function, then it will declare the rdi -p defect condition if bit 5 (within the g1 byte of the incoming sts-1 frame) is set to ?1? for ?rdi-p_thrd? number of incoming consecutive sts-1 spes. if the receive sts-1 poh processor block is configured to support the enhanced rdi-p? ( erdi-p ) function, then it will declare the rdi-p defect condition if bits 5, 6
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 707 and 7 (within the g1 byte of the incoming sts-1 frame) are set to [0, 1, 0], [1, 0, 1] or [1, 1, 0] for ?rdi-p_thrd? number of consecutive sts-1 frames. 0 ? indicates that the receive sts-1 poh processor block is not currently declaring the rdi-p defect condition. 1 ? indicates that the receive sts-1 poh processor block is currently declaring the rdi-p defect condition. note: the user can specify the value for ?rdi-p_thrd? by writing the appropriate data into bits 3 through 0 (rdi-p thrd) within the ?receive sts-1 path ? sonet receive rdi-p register (address location= 0xn193). 2 rdi-p unstable defect declared r/o rdi-p (path ? remote defect indicator) unstable defect declared: this read-only bit-field indicates whether or not the receive sts-1 poh processor block is currently declaring the ?rdi-p unstable? defect condition. the receive sts-1 poh processor block will declare the ?rdi-p unstable? defect condition whenever the ?rdi-p unstab le counter? reaches the value ?rdi-p thrd?. the ?rdi-p unstable? counter is incremented for each time that the receive sts-1 poh processor block receiv es an rdi-p value that differs from that of the previous sts-1 frame. the ? rdi-p unstable? counter is cleared to ?0? whenever the same rdi-p value is received in ?rdi-p_thrd? consecutive sts-1 frames. note: receiving a given rdi-p value, in ?rdi-p_thrd? consecutive sts-1 frames also clears th is bit-field to ?0?. 0 ? indicates that the receive sts-1 poh processor block is not currently declaring the ?rdi-p unstable? defect condition. 1 ? indicates that the receive sts-1 poh processor block is currently declaring the ?rdi-p unstable? defect condition. note: the user can specify the value for ?rdi-p_thrd? by writing the appropriate data into bits 3 through 0 (rdi-p thrd) within the ?receive sts-1 path ? sonet receive rdi-p register (address location= 0xn193). 1 lop-p defect declared r/o loss of pointer indicator (lop-p) defect declared: this read-only bit-field indicates whether or not the receive sts-1 poh processor block is currently declaring the lop-p (loss of pointer) defect condition. the receive sts-1 poh processor block will declare the lop-p defect condition, if it cannot detect a valid pointer (h1 and h2 bytes, within the toh) within 8 to 10 consecutive sonet frames. further, th e receive sts-1 poh processor block will declare the lop-p defect condition, if it detects 8 to 10 consecutive ndf events. the receive sts-1 poh processor block will clear the lop-p defect condition, whenever it detects valid pointer bytes (e.g., the h1 and h2 bytes, within the toh) and normal ndf value for three consecutive incoming sts-1 frames. 0 ? indicates that the receive sts-1 po h processor block is not declaring the lop-p defect condition. 1 ? indicates that the receive sts-1 poh processor block is currently declaring the lop-p defect condition. 0 ais-p defect declared r/o path ais (ais-p) defect declared: this read-only bit-field indicates whether or not the receive sts-1 poh processor block is currently declaring t he ais-p defect condition. the receive sts-1 poh processor block will declare the ais-p defect condition if it detects all of the following conditions within three consecutive incoming sts-1 frames. ? the h1, h2 and h3 bytes are set to an ?all ones? pattern.
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 708 ? the entire spe is set to an ?all ones? pattern. the receive sts-1 poh processor block will clear the ais-p defect condition when it detects a valid sts-1 pointer (h 1 and h2 bytes) and a ?set? or ?normal? ndf for three consecutive sts-1 frames. 0 ? indicates that the receive sts-1 poh processor block is not currently declaring the ais-p defect condition. 1 ? indicates that the receive sts-1 poh processor block is currently declaring the ais-p defect condition. note: the receive sts-1 poh processor block will not declare the lop-p defect condition if it detects an ?all ones? pattern in the h1, h2 and h3 bytes. it will, instead, declare the ais-p defect condition.
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 709 table 509: receive sts-1 path ? sonet receive path interrupt status ? byte 2 (address location= 0xn189, where n ranges in value from 0x05 to 0x07) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 unused detection of ais pointer interrupt status detection of pointer change interrupt status unused change in tim-p defect condition interrupt status change in path trace message unstable defect condition interrupt status r/o r/o r/o rur rur r/o rur rur 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 ? 5 unused r/o 4 detection of ais pointer interrupt status rur detection of ais pointer interrupt status: this reset-upon-read bit-field indicates whether or not the ?detection of ais pointer? interr upt has occurred since the last read of this register. if this interrupt is enabled, then the receive sts-1 poh processor block will generate this interrupt anytime it detects an ?ais pointer? in the incoming sts-1 data stream. note: an ?ais pointer? is defined as a condition in which both the h1 and h2 bytes (within the toh) are each set to an ?all ones? pattern. 0 ? indicates that the ?detecti on of ais pointer? interrupt has not occurred since the last read of this register. 1 ? indicates that the ?detecti on of ais pointer? interrupt has occurred since the last read of this register. 3 detection of pointer change interrupt status rur detection of pointer change interrupt status: this reset-upon-read bit-field indicates whether or not the ?detection of pointer change? interrupt has occurred since the last read of this register. if this interrupt is enabled, then the receive sts-1 poh processor block will generate an interrupt anytime it accepts a new pointer value (e.g., h1 and h2 bytes, in the toh bytes). 0 ? indicates that the ?detection of pointer change? interrupt has not occurred since the last read of this register. 1 ? indicates that the ?detection of pointer change? interrupt has occurred since the last read of this register. 2 unused r/o 1 change in tim-p defect condition interrupt status rur change in tim-p (trace identification mismatch) defect condition interrupt. this reset-upon-read bit-field indicates whether or not the ?change in tim-p? defect condition interrupt has occurred since the last read of this register. if this interrupt is enabled, then the receive sts-1 poh processor block will g enerate an interru p t in res p onse to either of
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 710 the following events. ? whenever the receive sts-1 poh processor block declares the tim-p defect condition. ? whenever the receive sts-1 poh processor block clears the tim-p defect condition. 0 ? indicates that the ?change in tim-p defect condition? interrupt has not occurred since the last read of this register. 1 ? indicates that the ?change in tim-p defect condition? interrupt has occurred since the last read of this register. 0 change in path trace message unstable defect condition interrupt status rur change in ?path trace identification message unstable defect condition? interrupt status: this reset-upon-read bit-field indicates whether or not the ?change in path trace message unstable defect condition? interrupt has occurred since the last read of this register. if this interrupt is enabled, then the receive sts-1 poh processor block will generate this interrupt in response to either of the following events. ? whenever the receive sts-1 poh processor block declare the ?path trace message unst able? defect condition. ? whenever the receive sts-1 poh processor block clears the ?path trace message unstable? defect condition. 0 ? indicates that the ?change in path trace message unstable defect condition? interrupt has not occurred since the last read of this register. 1 ? indicates that the ?change in path trace message unstable defect condition? interrupt has occurred since the last read of this register.
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 711 table 510: receive sts-1 path ? sonet receive path interrupt status ? byte 1 (address location= 0xn18a, where n ranges in value from 0x05 to 0x07) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 new path trace message interrupt status detection of rei-p event interrupt status change in uneq-p defect condition interrupt status change in plm-p defect condition interrupt status new c2 byte interrupt status change in c2 byte unstable defect condition interrupt status change in rdi-p unstable defect condition interrupt status new rdi-p value interrupt status rur rur rur rur rur rur rur rur 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 new path trace message interrupt status rur new path trace message interrupt status: this reset-upon-read bit-field indicates whether or not the ?new path trace message? interrupt has occurred si nce the last read of this register. if this interrupt is enabled, then the receive sts-1 poh processor block will generate an interrupt anyt ime it has accepted (or validated) a new path trace message. 0 ? indicates that the ?new path trace message? interrupt has not occurred since the last read of this register. 1 ? indicates that the ?new path trace message? interrupt has occurred since the last read of this register. 6 detection of rei-p event interrupt status rur detection of rei-p event interrupt status: this reset-upon-read bit-field indicates whether or not the ?detection of rei-p event? interrupt has occurred sinc e the last read of this register. if this interrupt is enabled, then the receive sts-1 poh processor block will generate an interrupt anytime it detects an rei-p event within the incoming sts-1 data-stream. 0 ? indicates that the ?d etection of rei-p event? interrupt has not occurred since the last read of this register. 1 ? indicates that the ?detection of rei-p event? interr upt has occurred since the last read of this register. 5 change in uneq-p defect condition interrupt status rur change in uneq-p (path ? unequipped) defect condition interrupt status: this reset-upon-read bit-field indicates whether or not the ?change in uneq-p defect condition? interrupt has occurred since the last read of this register. if this interrupt is enabled, then the receive sts-1 poh processor block will generate an interrupt in response to either of the following conditions. ? when the receive sts-1 poh processor block declares the uneq-p defect condition. ? when the receive sts-1 poh processor block clears the uneq-p defect condition. 0 ? indicates that the ?change in uneq -p defect condition? interrupt has not occurred since the last read of this register. 1 ? indicates that the ?chan g e in uneq-p defect condition? interru p t has
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 712 occurred since the last read of this register. note: the user can determine if the receive sts-1 poh processor block is currently declaring the uneq-p defect condition by reading out the state of bit 5 (uneq-p defect declared) within the ?receive sts-1 path ? sonet receive poh status ? byte 0? register (address location= 0xn187). 4 change in plm-p defect condition interrupt status rur change in plm-p (path ? payload mismatch) defect condition interrupt status: this reset-upon-read bit indicates whether or not the ?change in plm-p defect condition? interrupt has occurred since the last read of this register. if this interrupt is enabled, then the receive sts-1 poh processor block will generate an interrupt in response to either of the following conditions. ? when the receive sts-1 poh processor block declares the ?plm-p? defect condition. ? when the receive sts-1 poh processor block clears the ?plm-p? defect condition. 0 ? indicates that the ?change in pl m-p defect condition? interrupt has not occurred since the last read of this register. 1 ? indicates that the ?change in pl m-p defect condition? interrupt has occurred since the last read of this register. 3 new c2 byte interrupt status rur new c2 byte interrupt status: this reset-upon-read bit-field indicates whether or not the ?new c2 byte? interrupt has occurred since the last read of this register. if this interrupt is enabled, then the receive sts-1 poh processor block will generate an interrupt anytime it has accepted a new c2 byte. 0 ? indicates that the ?new c2 byte? interrupt has not occurred since the last read of this register. 1 ? indicates that the ?new c2 byte? interrupt has occurred since the last read of this register. 2 change in c2 byte unstable defect condition interrupt status rur change in c2 byte unstable defect condition interrupt status: this reset-upon-read bit-field indicates whether or not the ?change in c2 byte unstable defect condition? interrupt has occurred since the last read of this register. if this interrupt is enabled, then the receive sts-1 poh processor block will generate an interrupt in response to either of the following events. ? when the receive sts-1 poh processor block declares the ?c2 byte unstable? defect condition. ? when the receive sts-1 poh processor block clears the ?c2 byte unstable? defect condition. 0 ? indicates that the ?change in c2 byte unstable defect condition? interrupt has not occurred since the last read of this register. 1 ? indicates that the ?change in c2 byte unstable defect condition? interrupt has occurred since the last read of this register. note: the user can determine whether or not the receive sts-1 poh processor block is currently declaring the ?c2 byte unstable defect condition? by reading out the state of bit 6 (c2 byte unstable defect declared) within the ?receive sts-1 path ? sonet receive poh status ? byte 0? register (address location= 0xn187).
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 713 1 change in rdi- p unstable defect condition interrupt status rur change in rdi-p unstable defect condition interrupt status: this reset-upon-read bit-field indicates whether or not the ?change in rdi-p unstable defect condition? interru pt has occurred since the last read of this register. if this interrupt is enabled, then the receive sts-1 poh processor block will generate an interrupt in response to either of the following conditions. ? when the receive sts-1 poh processor block declares an ?rdi-p unstable? defect condition. ? when the receive sts-1 poh processor block clears the ?rdi-p unstable? defect condition. 0 ? indicates that the ?change in rdi-p unstable defect condition? interrupt has not occurred since the la st read of this register. 1 ? indicates that the ?change in rdi-p unstable defect condition? interrupt has occurred since the last read of this register. note: the user can determine the current state of ?rdi-p unstable defect condition? by reading out the state of bit 2 (rdi-p unstable defect condition) within the ?receive sts-1 path ? sonet receive poh status ? byte 0? register (address location= 0xn187). 0 new rdi-p value interrupt status rur new rdi-p value interrupt status : this reset-upon-read bit-field indicates whether or not the ?new rdi-p value? interrupt has occurred since the last read of this register. if this interrupt is enabled, then the receive sts-1 poh processor block will generate this interrupt anytime it receives and ?validates? a new rdi-p value. 0 ? indicates that the ?new rdi-p value? interrupt has not occurred since the last read of this register. 1 ? indicates that the ?new rdi-p value? interrupt has occurred since the last read of this register. note: the user can obtain the ?new rdi -p value? by reading out the contents of the ?rdi-p accept[2:0]? bit-fields. these bit-fields are located in bits 6 through 4, within the ?receive sts-1 path ? sonet receive rdi-p register? (address location= 0xn193).
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 714 table 511: receive sts-1 path ? sonet receive path interrupt status ? byte 0 (address location= 0xn18b, where n ranges in value 0x05 to 0x07) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 detection of b3 byte error interrupt status detection of new pointer interrupt status detection of unknown pointer interrupt status detection of pointer decrement interrupt status detection of pointer increment interrupt status detection of ndf pointer interrupt status change of lop-p defect condition interrupt status change of ais-p defect condition interrupt status rur rur rur rur rur rur rur rur 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 detection of b3 byte error interrupt status rur detection of b3 byte error interrupt status: this reset-upon-read bit-field indicates whether or not the ?detection of b3 byte error? interr upt has occurred since the last read of this register. if this interrupt is enabled, then the receive sts-1 poh processor block will generate an interrupt anytime it detects a b3 byte error in the incoming sts-1 data stream. 0 ? indicates that the ?detection of b3 byte error? interrupt has not occurred since the last read of this interrupt. 1 ? indicates that the ?detection of b3 byte error? interrupt has occurred since the last read of this interrupt. 6 detection of new pointer interrupt status rur detection of new pointer interrupt status: this reset-upon-read indicates whether the ?detection of new pointer? interrupt has occurred since the last read of this register. if the user enables this interrupt, then the receive sts-1 poh processor block will generate an interrupt anytime it detects a new pointer value in the incoming sts-1 frame. note: pointer adjustments with ndf will not generate this interrupt. 0 ? indicates that the ?detection of new pointer? interrupt has not occurred since the last read of this register. 1 ? indicates that the ?d etection of new pointer? interrupt has occurred since the last read of this register. 5 detection of unknown pointer interrupt status rur detection of unknown pointer interrupt status: this reset-upon-read bit-field indicates whether or not the ?detection of unknown pointer? interrupt has occurred since the last read of this register. if the user enables this interrupt, then the receive sts-1 poh processor block will generate an interrupt anytime that it detects a ?pointer? that does not fit into any of the following categories. ? an increment pointer ? a decrement pointer ? an ndf pointer ? an ais (e.g., all ones) pointer ? new pointer
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 715 0 ? indicates that the ?detection of unknown pointer? interrupt has not occurred since the last read of this register. 1 ? indicates that the ?detection of unknown pointer? interrupt has occurred since the last read of this register. 4 detection of pointer decrement interrupt status rur detection of pointer decrement interrupt status: this reset-upon-read bit-field indicates whether or not the ?detection of pointer decrement? in terrupt has occurred since the last read of this register. if this interrupt is enabled, then the receive sts-1 poh processor block will generate an interrupt anytime it detects a ?pointer decrement? event. 0 ? indicates that the ?detection of pointer decrement? interrupt has not occurred since the last read of this register. 1 ? indicates that the ?detection of pointer decrement? interrupt has occurred since the last read of this register. 3 detection of pointer increment interrupt status rur detection of pointer increment interrupt status: this reset-upon-read bit-field indicates whether or not the ?detection of pointer increment? interrupt has occurred since the last read of this register. if this interrupt is enabled, then the receive sts-1 poh processor block will generate an interrupt anytim e it detects a ?pointer increment? event. 0 ? indicates that the ?detection of pointer increment? interrupt has not occurred since the last read of this register. 1 ? indicates that the ?detection of pointer increment? interrupt has occurred since the last read of this register. 2 detection of ndf pointer interrupt status rur detection of ndf pointer interrupt status: this reset-upon-read bit-field indicates whether or not the ?detection of ndf pointer? interrupt has occurred since the last read of this register. if the user enables this interrupt, then the receive sts-1 poh processor block will generate an interrupt anytime it detects an ndf pointer event. 0 ? indicates that the ?detection of ndf pointer? interrupt has not occurred since the last read of this register. 1 ? indicates that the ?d etection of ndf pointer? interrupt has occurred since the last read of this register. 1 change of lop-p defect condition interrupt status rur change of lop-p defect condition interrupt status: this reset-upon-read bit-field indicates whether or not the ?change in lop-p defect condition? interrupt has occurred since the last read of this register. if the user enables this interrupt, then the receive sts-1 poh processor block will generate an interrupt in response to either of the following events. ? whenever the receive sts-1 poh processor block declares the lop-p defect condition. ? whenever the receive ?sts-1 poh processor? block clears the lop-p defect condition. 0 ? indicates that the ?change in lo p-p defect condition? interrupt has not occurred since the last read of this register. 1 ? indicates that the ?chan g e in lop-p defect condition? interru p t has
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 716 occurred since the last read of this register. note: the user can determine if the receive sts-1 poh processor block is currently declaring the lop-p defect condition by reading out the state of bit 1 (lop-p defect declared) within the ?receive sts-1 path ? sonet receive poh status ? byte 0? register (address location=0xn187). 0 change of ais-p defect condition interrupt status rur change of ais-p defect condition interrupt status: this reset-upon-read bit-field indicates whether or not the ?change of ais-p defect condition? interrupt has occurred since the last read of this register. if this interrupt is enabled, then the receive sts-1 poh processor block will generate an interrupt in response to either of the following events. ? whenever the receive sts-1 poh processor block declares the ais-p defect condition. ? whenever the receive sts-1 poh processor block clears the ais-p defect condition. 0 ? indicates that the ?change of ai s-p defect condition? interrupt has not occurred since the last read of this register. 1 ? indicates that the ?change of ai s-p defect condition? interrupt has occurred since the last read of this register. note: the user can determine if the receive sts-1 poh processor block is currently declaring the ais-p defect condition by reading out the state of bit 0 (a is-p defect de clared) within the ?receive sts-1 path ? sonet receive poh status ? byte 0? register (address location= 0xn187).
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 717 table 512: receive sts-1 path ? sonet receive path interrupt enable ? byte 2 (address location = 0xn18d, where n ranges in value from 0x05 to 0x07) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 unused detection of ais pointer interrupt enable detection of pointer change interrupt enable unused change in tim-p defect condition interrupt enable change in path trace message unstable defect condition interrupt enable r/o r/o r/o r/w r/w r/o r/w r/w 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7-5 unused r/o 4 detection of ais pointer interrupt enable r/w detection of ais pointer interrupt enable: this read/write bit-field permits the user to either enable or disable the ?detection of ais pointer? interrupt. if the user enables this interrupt, then the receive sts-1 poh processor block will generate an interrupt anytime it detects an ?ais pointer?, in the incoming sts-1 data stream. note: an ?ais pointer? is defined as a condition in which both the h1 and h2 bytes (within the toh) are each set to an ?all ones? pattern. 0 ? disables the ?detection of ais pointer? interrupt. 1 ? enables the ?detection of ais pointer? interrupt. 3 detection of pointer change interrupt enable r/w detection of pointer change interrupt enable: this read/write bit-field permits the user to either enable or disable the ?detection of pointer change? interrupt. if this interrupt is enabled, then the receive sts-1 poh processor block will generate an interrupt anytime it has accepted a new pointer value. 0 ? disables the ?detection of pointer chan ge? interrupt. 1 - enables the ?detection of pointer change? interrupt. 2 unused r/o 1 change in tim-p defect condition interrupt enable r/w change in tim-p (trace identification mismatch) defect condition interrupt: this read/write bit-field permits the user to either enable or disable the ?change in tim-p condition? interrupt. if this interrupt is enabled, then the receive sts-1 poh processor block will generate an interrupt in response to either of the following events. ? whenever the receive sts-1 poh processor block declares the tim-p defect condition. ? whenever the receive sts-1 poh processor block clears the tim-p defect condition.
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 718 0 ? disables the ?change in tim-p defect condition? interrupt. 1 ? enables the ?change in tim-p defect condition? interrupt. 0 change in path trace message unstable defect condition interrupt enable r/w change in path trace message? unstable defect condition? interrupt status: this read/write bit-field permits the user to either enable or disable the ?change in path trace message unstable defect condition? interrupt. if this interrupt is enabled, then the receive sts-1 poh processor block will generate an interrupt in response to either of the following events. ? whenever the receive sts-1 poh processor block declares the ?path trace message unstable defect? condition. ? whenever the receive sts-1 poh processor block clears the ?path trace message unstable defect? condition. 0 ? disables the ?change in path trace message unstable defect condition? interrupt. 1 ? enables the ?change in path trace message unstable defect condition? interrupt.
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 719 table 513: receive sts-1 path ? sonet receive path interrupt enable ? byte 1 (address location= 0xn18e, where n ranges in value from 0x05 to 0x07) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 new path trace message interrupt enable detection of rei-p event interrupt enable change in uneq-p defect condition interrupt enable change in plm-p defect condition interrupt enable new c2 byte interrupt enable change in c2 byte unstable defect condition interrupt enable change in rdi-p unstable defect condition interrupt enable new rdi-p value interrupt enable r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 new path trace message interrupt enable r/w new path trace message interrupt enable: this read/write bit-field permits the user to either enable or disable the ?new path trace message? interrupt. if this interrupt is enabled, then the receive sts-1 poh processor block will generate an interrupt anytime it has accepted (or validated) and new path trace message. 0 ? disables the ?new path trace message? interrupt. 1 ? enables the ?new path trace message? interrupt. 6 detection of rei-p event interrupt enable r/w detection of rei-p event interrupt enable: this read/write bit-field permits the user to either enable or disable the ?detection of rei-p event? interrupt. if this interrupt is enabled, then he receive sts-1 poh processor block will generate an interrupt anytime it detects an rei-p event within the coming sts-1 data-stream. 0 ? disables the ?detection of rei-p event? interrupt. 1 ? enables the ?detection of rei-p event? interrupt. 5 change in uneq-p defect condition interrupt enable r/w change in uneq-p (path ? unequipped) defect condition interrupt enable: this read/write bit-field permits the user to either enable or disable the ?change in uneq-p defect condition? interrupt. if this interrupt is enabled, then the receive sts-1 poh processor block will generate an interrupt in response to either of the following conditions. ? whenever the receive sts-1 poh processor block declares the uneq-p defect condition. ? whenever the receive sts-1 poh processor block clears the uneq-p defect condition. 0 ? disables the ?change in uneq-p defect condition? interrupt. 1 ? enables the ?change in uneq-p defect condition? interrupt. 4 change in plm-p defect condition interrupt enable r/w change in plm-p (path ? payload label mismatch) defect condition interrupt enable: this read/write bit permits the user to either enable or disable the ?change in plm-p defect condition? interrupt.
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 720 if this interrupt is enabled, then the receive sts-1 poh processor block will generate an interrupt in response to either of the following conditions. ? whenever the receive sts-1 poh processor block declares the ?plm-p? defect condition. ? whenever the receive sts-1 poh processor block clears the ?plm- p? defect condition. 0 ? disables the ?change in plm-p defect condition? interrupt. 1 ? enables the ?change in plm-p defect condition? interrupt. 3 new c2 byte interrupt enable r/w new c2 byte interrupt enable: this read/write bit-field permits the user to either enable or disable the ?new c2 byte? interrupt. if this interrupt is enabled, then the receive sts-1 poh processor block will generate an interrupt anytime it has accepted a new c2 byte. 0 ? disables the ?new c2 byte? interrupt. 1 ? enables the ?new c2 byte? interrupt. note: the user can obtain the value of this ?new c2? byte by reading the contents of the ?receive sts-1 path ? received path label value? register (address location= 0xn196). 2 change in c2 byte unstable defect condition interrupt enable r/w change in c2 byte unstable defect condition interrupt enable: this read/write bit-field permits the user to either enable or disable the ?change in c2 byte unstable condition? interrupt. if this interrupt is enabled, then the receive sts-1 poh processor block will generate an interrupt in response to either of the following events. ? when the receive sts-1 poh processor block declares the ?c2 byte unstable defect? condition. ? when the receive sts-1 poh processor block clears the ?c2 byte unstable defect? condition. 0 ? disables the ?change in c2 byte unstable defect condition? interrupt. 1 ? enables the ?change in c2 byte unstable defect condition? interrupt. 1 change in rdi-p unstable defect condition interrupt enable r/w change in rdi-p unstable defect condition interrupt enable: this read/write bit-field permits the user to either enable or disable the ?change in rdi-p unstable defect condition? interrupt. if this interrupt is enabled, then the receive sts-1 poh processor block will generate an interrupt in response to either of the following conditions. ? whenever the receive sts-1 poh processor block declares the ?rdi-p unstable defect? condition. ? whenever the receive sts-1 poh processor block clears the ?rdi- p unstable defect? condition. 0 ? disables the ?change in rdi-p unstable defect condition? interrupt. 1 ? enables the ?change in rdi-p unstable defect condition? interrupt. 0 new rdi-p value interrupt enable r/w new rdi-p value interrupt enable: this read/write bit-field p ermits the user to either enable or disable
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 721 interrupt enable the ?new rdi-p value? interrupt. if this interrupt is enabled, then the receive sts-1 poh processor block will generate this interrupt anytime it receives and ?validates? a new rdi-p value. 0 ? disables the ?new rdi-p value? interrupt. 1 ? enable the ?new rdi-p value? interrupt.
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 722 table 514: receive sts-1 path ? sonet receive path interrupt enable ? byte 0 (address location= 0xn18f, where n ranges in value from 0x05 to 0x07) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 detection of b3 byte error interrupt enable detection of new pointer interrupt enable detection of unknown pointer interrupt enable detection of pointer decrement interrupt enable detection of pointer increment interrupt enable detection of ndf pointer interrupt enable change of lop-p defect condition interrupt enable change of ais-p defect condition interrupt enable r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 detection of b3 byte error interrupt enable r/w detection of b3 byte error interrupt enable: this read/write bit-field permits the user to either enable or disable the ?detection of b3 byte error? interrupt. if the user enables this interrupt, then the receive sts-1 poh processor block will ge nerate an interrupt anytime it detects a b3-byte error in the incoming sts-1 data-stream. 0 ? disables the ?detection of b3 byte e rror? interrupt. 1 ? enables the ?detection of b3 byte error? interrupt. 6 detection of new pointer interrupt enable r/w detection of new pointer interrupt enable: this read/write bit-field permits the user to either enable or disable the ?detection of new pointer? interrupt. if the user enables this interrupt, then the receive sts-1 poh processor block will ge nerate an interrupt anytime it detects a new pointer value in the incoming sts-1 frame. note: pointer adjustments with ndf will not generate this interrupt. 0 ? disables the ?detection of new pointer? interrupt. 1 ? enables the ?detection of new pointer? interrupt. 5 detection of unknown pointer interrupt enable r/w detection of unknown pointer interrupt enable: this read/write bit-field permits the user to either enable or disable the ?detection of unknown pointer? interrupt. if the user enables this interrupt, then the receive sts-1 poh processor block will generate an interrupt anytime it detects a ?pointer adjustment? that does not fit into any of the following categories. ? an increment pointer. ? a decrement pointer ? an ndf pointer ? ais pointer ? new pointer. 0 ? disables the ?detection of unknown pointer? interrupt. 1 ? enables the ?detection of unknown pointer? interrupt. 4 detection of pointer decrement interrupt enable r/w detection of pointer decrement interrupt enable: this read/write bit-field permits the user to enable or disable the ?detection of pointer decrement? inte rrupt. if the user enables this interrupt, then the receive sts-1 toh processor block will generate an interrupt anytime it detects a ?pointer-decrement? event.
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 723 0 ? disables the ?detection of pointer decrement? interrupt. 1 ? enables the ?detection of pointer decrement? interrupt. 3 detection of pointer increment interrupt enable r/w detection of pointer increment interrupt enable: this read/write bit-field permits the user to either enable or disable the ?detection of pointer increm ent? interrupt. if the user enables this interrupt, then the receive sts-1 poh processor block will generate an interrupt anytime it detects a ?pointer increment? event. 0 ? disables the ?detection of pointer increment? interrupt. 1 ? enables the ?detection of pointer increment? interrupt. 2 detection of ndf pointer interrupt enable r/w detection of ndf pointer interrupt enable: this read/write bit-field permits the user to either enable or disable the ?detection of ndf pointer? in terrupt. if the user enables this interrupt, then the receive sts-1 poh processor block will ge nerate an interrupt anytime it detects an ndf pointer event. 0 ? disables the ?detection of ndf pointer? interrupt. 1 ? enables the ?detection of ndf pointer? interrupt. 1 change of lop-p defect condition interrupt enable r/w change of lop-p defect condition interrupt enable: this read/write bit-field permits the user to either enable or disable the ?change in lop (loss of pointer)? defect condition interrupt. if the user enables this interrupt, then the receive sts-1 poh processor block will generate an interrupt in response to either of the following events. ? whenever the receive sts-1 poh processor block declares the lop-p defect condition condition. ? whenever the receive sts-1 poh proc essor block clears the lop-p defect condition. 0 ? disable the ?change of lop-p defect condition? interrupt. 1 ? enables the ?change of lop-p defect condition? interrupt. note: the user can determine if the receive sts-1 poh processor block is currently declaring the lop-p defect condition by reading out the contents of bit 1 (lop-p defect declared) within the ?receive sts-1 path ? sonet receive poh status ? byte 0? (address location= 0xn187). 0 change of ais-p defect condition interrupt enable r/w change of ais-p defect condition interrupt enable: this read/write bit-field permits the user to either enable or disable the ?change of ais-p (path ais)? defect conditi on interrupt. if the user enables this interrupt, then the receive sts-1 poh pr ocessor block will generate an interrupt in response to either of the following events. ? whenever the receive sts-1 poh processor block declares the ais-p defect condition. ? whenever the receive sts-1 poh proces sor block clears the ais-p defect condition. 0 ? disables the ?change of ais-p defect condition? interrupt. 1 ? enables the ?change of ais-p defect condition? interrupt. note: the user can determine if the receive sts-1 poh processor block is currently declaring the ais-p defec t condition by reading out the contents of bit 0 (ais-p defect de clared) within the ?receive sts-1 path ? sonet receive poh status ? byte 0? (address location= 0xn187).
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 724
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 725 table 515: receive sts-1 path ? sonet receive rdi -p register (address location= 0xn193, where n ranges in value from 0x05 to 0x07) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 unused rdi-p_accept[2:0] rdi-p threshold[3:0] r/o r/o r/o r/o r/w r/w r/w r/w 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 unused r/o 6 - 4 rdi-p_accept[2:0] r/o accepted rdi-p value: these read-only bit-fields contain the value of the most recently ?accepted? rdi-p (e.g., bits 5, 6 and 7 within the g1 byte) value that has been accepted by the receiv e sts-1 poh processor block. note: a given rdi-p value will be ?accepted? by the receive sts-1 poh processor block, if this rdi-p value has been consistently received in ?rdi-p threshold[3:0]? number of sts-1 frames. 3 - 0 rdi-p threshold[3:0] r/w rdi-p threshold[3:0]: these read/write bit-fields permit the user to defined the ?rdi-p acceptance threshold? for the receive sts-1 poh processor block. the ?rdi-p acceptance threshold? is the number of consecutive sts-1 frames, in which the receive sts-1 poh processor block must receive a given rdi-p value, before it ?accepts? or ?validates? it. the most recently ?accepted? rdi-p value is written into the ?rdi-p accept[2:0]? bit-fields, within this register.
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 726 table 516: receive sts-1 path ? received path label value (address location= 0xn196, where n ranges in value from 0x05 to 0x07) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 received_c2_byte_value[7:0] r/o r/o r/o r/o r/o r/o r/o r/o 1 1 1 1 1 1 1 1 b it n umber n ame t ype d escription 7 ? 0 received c2 byte value[7:0] r/o received ?filtered? c2 byte value: these read-only bit-fields contain the value of the most recently ?accepted? c2 byte, via the receive sts-1 poh processor block. the receive sts-1 poh processor block will ?accept? a c2 byte value (and load it into these bit-fields) if it has received a consistent c2 byte, in five (5) consecutive sts-1 frames. note: the receive sts-1 poh processor block uses this register, along the ?receive sts-1 path ? expected path label value? register (address location = 0xn197), when declaring or clearing the uneq-p and plm-p defect conditions. table 517: receive sts-1 path ? expected path label value (address location= 0xn197, where n ranges in value from 0x05 to 0x07) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 expected_c2_byte_value[7:0] r/w r/w r/w r/w r/w r/w r/w r/w 1 1 1 1 1 1 1 1 b it n umber n ame t ype d escription 7 - 0 expected c2 byte value[7:0] r/w expected c2 byte value: these read/write bit-fields permits the user to specify the c2 (path label byte) value, that the receive sts-1 poh processor block should expect when declaring or clearing the uneq-p and plm-p defect conditions. if the contents of the ?receive d c2 byte value[7:0]? (see ?receive sts-1 path ? received path label value? register) matches the contents in these register, then the receive sts- 1 poh will not declare any defect conditions. note: the receive sts-1 poh processor block uses this register, along with the ?receive sts-1 path ? receive path label value? register (address location = 0xn196), when declaring or clearing the uneq-p and plm-p defect conditions.
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 727 table 518: receive sts-1 path ? b3 byte error c ount register ? byte 3 (address location= 0xn198, where n ranges in value from 0x05 to 0x07) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 b3_byte_error_count[31:24] rur rur rur rur rur rur rur rur 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 - 0 b3_byte_error_count[31:24] rur b3 byte error count ? msb: this reset-upon-read register, along with ?receive sts-1 path ? b3 byte error count register ? bytes 2 through 0; function as a 32 bit counter, which is incremented anytime the receive sts-1 poh processor block detects a b3 byte error. note: 1. if the receive sts-1 poh processor block is configured to count b3 byte errors on a ?per-bit? basis, then it will increment this 32 bit counter by the number of bits, within the b3 byte (of each incoming sts-1 spe) that are in error. 2. if the receive sts-1 poh processor block is configured to count b3 byte errors on a ?per-f rame? basis, then it will increment this 32 bit counter each time that it receives an sts-1 spe that contains an erred b3 byte.
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 728 table 519: receive sts-1 path ? b3 byte error c ount register ? byte 2 (address location= 0xn199, where n ranges in value from 0x05 to 0x07) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 b3_byte_error_count[23:16] rur rur rur rur rur rur rur rur 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 - 0 b3_byte_error_count[23:16] rur b3 byte error count (bits 23 through 16): this reset-upon-read register, along with ?receive sts-1 path ? b3 byte error count register ? bytes 3, 1 and 0; function as a 32 bit counter, which is increm ented anytime the receive sts-1 poh processor block detects a b3 byte error. note: 1. if the receive sts-1 poh processor block is configured to count b3 byte errors on a ?per-bit? basis, then it will increment this 32 bit counter by the number of bits, within the b3 byte (of each incoming sts-1 spe) that are in error. 2. if the receive sts-1 poh processor block is configured to count b3 byte errors on a ?per-f rame? basis, then it will increment this 32-bit counter each time that it receives an sts-1 spe that contains an erred b3 byte.
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 729 table 520: receive sts-1 path ? b3 byte error c ount register ? byte 1 (address location= 0xn19a, wher n ranges in value from 0x05 to 0x07) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 b3_byte_error_count[15:8] rur rur rur rur rur rur rur rur 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 - 0 b3_byte_error_count[15:8] rur b3 byte error count ? (bits 15 through 8): this reset-upon-read register, along with ?receive sts-1 path ? b3 byte error count register ? bytes 3, 2 and 0; function as a 32 bit counter, which is incremented anytime the receive sts-1 poh processor block detects a b3 byte error. note: 1. if the receive sts-1 poh processor block is configured to count b3 byte errors on a ?per-bit? basis, then it will increment this 32-bit counter by the number of bi ts, within the b3 byte (of each incoming sts-1 spe) that are in error. 2. if the receive sts-1 poh processor block is configured to count b3 byte errors on a ?per-f rame? basis, then it will increment this 32-bit counter each time that it receives an sts-1 spe that contains an erred b3 byte.
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 730 table 521: receive sts-1 path ? b3 byte error c ount register ? byte 0 (address location= 0xn19b, where n ranges in value from 0x05 to 0x07) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 b3_byte_error_count[7:0] rur rur rur rur rur rur rur rur 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 - 0 b3_byte_error_count[7:0] rur b3 byte error count - lsb: this reset-upon-read register, along with ?receive sts-1 path ? b3 byte error count register ? bytes 3 through 1; function as a 32 bit counter, which is increment ed anytime the receive sts-1 poh processor block detects a b3 byte error. note: 1. if the receive sts-1 poh processo r block is configured to count b3 byte errors on a ?per-bit? basis, then it will increment this 32 bit counter by the number of bits, within the b3 byte (of each incoming sts-1 spe) that are in error. 2. if the receive sts-1 poh processo r block is configured to count b3 byte errors on a ?per-frame? basis, then it will increment this 32 bit counter each time that it receiv es an sts-1 spe that contains an erred b3 byte.
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 731 table 522: receive sts-1 path ? rei-p event count register ? byte 3 (address location= 0xn19c, where n ranges in value from 0x05 to 0x07) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 rei-p event_count[31:24] rur rur rur rur rur rur rur rur 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 - 0 rei-p event count[31:24] rur rei-p event count ? msb: this reset-upon-read register, along with ?receive sts-1 path ? rei-p event count register ? bytes 2 through 0; function as a 32 bit counter, which is increm ented anytime the receive sts-1 poh processor block detects a path - remote error indicator event within the incomi ng sts-1 spe data-stream. note: 1. if the receive sts-1 poh processor block is configured to count rei-p events on a ?per-bit? basi s, then it will increment this 32-bit counter by the nibble-value within the rei-p field of the incoming g1 byte within each incoming sts-1 spe. 2. if the receive sts-1 poh processor block is configured to count rei-p events on a ?per-frame ? basis, then it will increment this 32-bit counter each time that it receives an sts-1 spe that contains a ?non-zero? rei-p value.
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 732 table 523: receive sts-1 path ? rei-p event count register ? byte 2 (address location= 0xn19d, where n ranges in value from 0x05 to 0x07) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 rei-p_event_count[23:16] rur rur rur rur rur rur rur rur 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 - 0 rei-p event_count[23:16] rur rei-p event count (bits 23 through 16): this reset-upon-read register, along with ?receive sts-1 path ? rei-p event count register ? bytes 3, 1 and 0; function as a 32 bit counter, which is incremented anytime the receive sts-1 poh processor block detects a path ? remote error indicator event within the incoming sts-1 spe data-stream. note: 1. if the receive sts-1 poh processor block is configured to count rei-p events on a ?per-bit? basi s, then it will increment this 32-bit counter by the nibble-value within the rei-p field of the incoming g1 byte within each incoming sts-1 frame. 2. if the receive sts-1 poh processor block is configured to count rei-p events on a ?per-fra me? basis, then it will increment this 32-bit counter each time that it receives an sts-1 spe that contains a ?non-zero? rei-p value.
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 733 table 524: receive sts-1 path ? rei-p event count register ? byte 1 (address location= 0xn19e, where n ranges in value from 0x05 to 0x07) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 rei-p_event_count[15:8] rur rur rur rur rur rur rur rur 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 - 0 rei-p event_count[15:8] rur rei-p event count ? (bits 15 through 8) this reset-upon-read register, along with ?receive sts-1 path ? rei-p event count register ? bytes 3, 2 and 0; function as a 32 bit counter, which is incremented anytime the receive sts-1 poh processor block detects a path ?remote error indicator event within the incomi ng sts-1 spe data-stream. note: 1. if the receive sts-1 poh processor block is configured to count rei-p events on a ?per-bit? bas is, then it will increment this 32-bit counter by the nibble-value within the rei-p field of the incoming g1 byte within each incoming sts-1 spe. 2. if the receive sts-1 poh processor block is configured to count rei-p events on a ?per-frame ? basis, then it will increment this 32-bit counter each time that it receives an sts-1 spe that contains a non-zero rei-p value.
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 734 table 525: receive sts-1 path ? rei-p event count register ? byte 0 (address location= 0xn19f, where n ranges in value from 0x05 to 0x07) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 rei-p_event_count[7:0] rur rur rur rur rur rur rur rur 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 - 0 rei-p_event_count[7:0] rur rei-p event count ? lsb: this reset-upon-read register, along with ?receive sts-1 path ? rei-p event count register ? bytes 3 through 1; function as a 32 bit counter, which is incremented an ytime the receive sts-1 poh processor block detects a path ? remote error indicator event within the incoming sts-1 spe data-stream. note: 1. if the receive sts-1 poh processor block is configured to count rei-p events on a ?per-bit? basis, t hen it will increment this 32 bit counter by the nibble-value within the rei-p field of the incoming g1 byte. 2. if the receive sts-1 poh processor block is configured to count rei-p events on a ?per-frame? basis, then it will increment this 32 bit counter each time that it receiv es an sts-1 spe that contains a ?non- zero? rei-p value.
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 735 table 526: receive sts-1 path ? receive path trace message buffer control register (address location= 0xn1a3, where n ranges in value from 0x05 to 0x07) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 unused new message ready receive path trace message buffer read select receive path trace message accept threshold path trace message alignment type receive path trace message length[1:0] r/o r/o r/o r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 ? 6 unused r/o 5 new message ready r/o new message ready: this read/write bit-field indicates whether or not the receive sts-1 poh processor block has (1) accepted a new receive path trace message, and (2) has loaded this new message into the receive path trace message buffer, since the last read of this register. 0 ? indicates that the receive sts-1 poh processor block has (1) not accepted a new path trace message, nor (2) has the receive sts-1 poh processor block loaded any new message into the receive path trace message buffer, since the last read of this register. 1 ? indicates that the receive sts-1 poh processor block has (1) accepted a new path trace message, and (2) has loaded this new message into the receive path trace message buffer, since the last read of this register. 4 receive path trace message buffer read select r/w receive path trace message buffer read selection: this read/write bit-field permits a user to specify which of the following receive path trace message buffer segments that the microprocessor will read out, whenev er it reads out the contents of the receive path trace message buffer. a. the ?actual? receive path trace message buffer. the ?actual? receive path trace message buffer contains the contents of the most recently received (and accepted) path trace message via the incoming sts-1 data-stream. b. the ?expected? receive path trace message buffer. the ?expected? receive path trace message buffer contains the contents of the path tr ace message that the user ?expects? to receive. the contents of this particular buffer are usually specified by the user. 0 ? executing a read to the receive path trace message buffer, will return contents within the ?actual? receive path trace message buffer. 1 ? executing a read to the receive path trace message buffer will return contents within the ?expected receive path trace message buffer?. note: in the case of the receive st s-1 poh processor block, the ?receive path trace message buffer? is located at address location 0xn500 through 0xn53f.
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 736 3 path trace message accept threshold r/w path trace message accept threshold: this read/write bit-field permits a user to select the number of consecutive times that the rece ive sts-1 poh processor block must receive a given receive path trace message, before it is accepted and loaded into the ?actual? receive path trace message buffer, as described below. 0 ? configures the receive sts-1 poh processor block to accept the incoming path trace message after it has received it the third time in succession. 1 ? configures the receive sonet poh processor block to accept the incoming path trace message after it has received in the fifth time in succession. 2 path trace message alignment type r/o path trace message alignment type: this read/write bit-field permits a user to specify how the receive sts-1 poh processor block will locate the boundary of the incoming path trace message (within the incoming sts-1 data-stream), as indicated below. 0 ? configures the receive sts- 1 poh processor block to expect the path trace message boundary to be denoted by a ?line feed? character. 1 ? configures the receive sts- 1 poh processor block to expect the path trace message boundary to be denoted by the presence of a ?1? in the msb (most significant bit) of the very first byte (within the incoming path trace message). in this case, all of the remaining bytes (within the incoming path trace message) will each have a ?0? within their msbs. 1 ? 0 receive path trace message length[1:0] r/w receive path trace message length[1:0]: these read/write bit-fields permit the user to specify the length of the receive path trace message that the receive sts-1 poh processor block will accept and load into the ?actual? receive path trace message buffer. the relationship between the content of these bit-fields and the corresponding receive path trace message length is presented below. receive path trace message length[1:0] resulting path trace message length (in terms of bytes) 00 1 byte 01 16 bytes 10/11 64 bytes
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 737 table 527: receive sts-1 path ? pointer value ? byte 1 (address location= 0xn1a6, where n ranges in value from 0x05 to 0x07) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 unused current_pointer value msb[9:8] r/o r/o r/o r/o r/o r/o r/o r/o 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 - 2 unused r/o 1 ? 0 current_pointer_value_msb[7:0] r/o current pointer value ? msb: these read-only bit-fields, along with that from the ?receive sts-1 path ? pointe r value ? byte 0? register combine to reflect the current value of the pointer that the ?receive sts-1 poh processor? block is using to locate the spe within the incoming sts-1 data stream. note: these register bits comprise the upper byte value of the pointer value. table 528: receive sts-1 path ? pointer value ? byte 0 (address location= 0xn1a7, where n ranges in value from 0x05 to 0x07) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 current_pointer_value_lsb[7:0] r/o r/o r/o r/o r/o r/o r/o r/o 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 ? 0 current_pointer_value_lsb[7:0] r/o current pointer value ? lsb: these read-only bit-fields, along with that from the ?receive sts-1 path ? pointer value ? byte 1? register combine to reflect the current value of the pointer that the ?receive sts-1 poh processor? block is using to locate the spe within the incoming sts-1 data stream. note: these register bits comprise the lower byte value of the pointer value.
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 738 table 529: receive sts-1 path ? auto ais cont rol register (address location= 0xn1bb, where n ranges in value from 0x05 to 0x07) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 unused transmit ais-p (down- stream) upon c2 byte unstable transmit ais-p (down- stream) upon uneq-p transmit ais-p (down- stream) upon plm- p transmit ais-p (down- stream) upon path trace message unstable transmit ais-p (down- stream) upon tim-p transmit ais-p (down- stream) upon lop-p transmit ais-p (down- stream) enable r/o r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 unused r/o 6 transmit ais-p (downstream) upon c2 byte unstable r/w transmit path ais (downstream, towards the corresponding transmit sonet poh processor block) upon declaration of the unstable c2 byte defect condition: this read/write bit-field permits the user to configure the receive sts-1 poh processor block to automatically transmit the path ais (ais-p) indicator via the ?downs tream? traffic (e .g., towards the corresponding transmit sonet poh processor block), anytime (and for the duration that) it declares the unstable c2 byte defect condition within the ?inc oming? sts-1 data-stream. 0 ? does not configure the receive sts-1 poh processor block to automatically transmit the ais-p indicator (via the ?downstream? traffic, towards the corresponding transmit sonet poh processor block) whenever it declares the ?uns table c2 byte? defect condition. 1 ? configures the receive sts-1 poh processor block to automatically transmit the ais-p indicator (via the ?downstream? traffic, towards the corresponding transmit sonet poh processor block) whenever it declares the ?unstable c2 byte? defect condition. note: the user must also set bit 0 (transmit ais-p enable) to ?1? to configure the receive sts-1 poh processor block to automatically transmit the ais-p indicator, in response to this defect condition. 5 transmit ais-p (downstream) upon uneq-p r/w transmit path ais (downstream, towards the corresponding transmit sonet poh processor block) upon declaration of the uneq-p (path ? unequipped) defect condition: this read/write bit-field permits the user to configure the receive sts-1 poh processor block to automatically transmit the path ais (ais-p) indicator via the ?downs tream? traffic (e .g., towards the corresponding transmit sonet poh processor block), anytime (and for the duration that) it declare s the uneq-p defect condition. 0 ? does not configure the receive sts-1 poh processor block to automatically transmit the ais-p indicator (via the ?downstream? traffic, towards the corresponding transmit sonet poh processor block) whenever it declares the uneq-p defect condition. 1 ? configures the receive sts-1 poh processor block to automatically transmit the ais-p indicator (via the ?downstream? traffic, towards the corresponding transmit sonet poh processor block ) whenever ( and for the duration that ) it declares the uneq-p
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 739 defect condition. note: the user must also set bit 0 (transmit ais-p enable) to ?1? to configure the receive sts-1 poh processor block to automatically transmit the ais-p indicator, in response to this defect condition. 4 transmit ais-p (downstream) upon plm-p r/w transmit path ais (downstream, towards the corresponding transmit sonet poh processor block) upon declaration of the plm-p (path ? payload label mismatch) defect condition: this read/write bit-field permits the user to configure the receive sts-1 poh processor block to automatically transmit the path ais (ais-p) indicator via the ?dow nstream? traffic (e.g., towards corresponding transmit sonet poh processor block), anytime (and for the duration that) it decla res the plm-p defect condition. 0 ? does not configure the receive sts-1 poh processor block to automatically transmit the ais-p indicator (via the ?downstream? traffic, towards the corresponding transmit sonet poh processor block) whenever it declares the plm-p defect condition. 1 ? configures the receive sts-1 poh processor block to automatically transmit the ais-p indicator (via the ?downstream? traffic, towards the corresponding transmit sonet poh processor block) whenever (and for the duration that) it declares the plm-p defect condition. note: the user must also set bit 0 (transmit ais-p enable) to ?1? to configure the receive sts-1 poh processor block to automatically transmit the ais-p indicator, in response to this defect condition. 3 transmit ais-p (downstream) upon path trace message unstable r/w transmit path ais (downstream, towards the corresponding transmit sonet poh processor block) upon declaration of the path trace message unstable defect condition: this read/write bit-field permits the user to configure the receive sts-1 poh processor block to automatically transmit the path ais (ais-p) indicator via the ?downs tream? traffic (e .g., towards the corresponding transmit sonet poh processor blocks), anytime (and for the duration that) it declares the path trace message unstable defect condition within the ?incoming? sts-1 data-stream. 0 ? does not configure the receive sts-1 poh processor block to automatically transmit the ais-p indicator (via the ?downstream? traffic, towards the corresponding transmit sonet poh processor block) whenever it declares t he ?path trace message unstable? defect condition. 1 ? configures the receive sts-1 poh processor block to automatically transmit the ais-p indicator (via the ?downstream? traffic, towards the corresponding transmit sonet poh processor block) whenever it declares t he ?path trace message unstable? defect condition. note: the user must also set bit 0 (transmit ais-p enable) to ?1? to configure the receive sts-1 poh processor block to automatically transmit the ais-p indicator, in response to this defect condition. 2 transmit ais-p (downstream) upon tim-p r/w transmit path ais (downstream towards the corresponding transmit sonet poh processor block) upon declaration of the tim-p (path trace message indent ification mismatch) defect condition: this read/write bit-field permits the user to configure the receive sts-1 poh processor block to automaticall y transmit a path ais
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 740 (ais-p) indicator via the ?downs tream? traffic (e .g., towards the corresponding transmit sonet poh processor blocks), anytime (and for the duration that) it dec lares the tim-p defect condition within the incoming sts-1 data-stream. 0 ? does not configure the receive sts-1 poh processor block to automatically transmit the ais-p indicator (via the ?downstream? traffic towards the corresponding transmit sonet poh processor block) whenever it declares the tim-p defect condition. 1 ? configures the receive sts-1 poh processor block to automatically transmit the ais-p indicator (via the ?downstream? traffic, towards the corresponding transmit sonet poh processor block) whenever (and for the duration that) it declares the tim-p defect condition. note: the user must also set bit 0 (transmit ais-p enable) to ?1? to configure the receive sts-1 poh processor block to automatically transmit the ais-p indicator, in response to this defect condition. 1 transmit ais-p (downstream) upon lop-p r/w transmit path ais (downstream, towards the corresponding transmit sonet poh processor block) upon detection of loss of pointer (lop-p) defect condition: this read/write bit-field permits the user to configure the receive sts-1 poh processor block to automatically transmit the path ais (ais-p) indicator via the ?downs tream? traffic (e .g., towards the corresponding transmit sonet poh processor blocks), anytime (and for the duration that) it declares the lop-p defect condition within the incoming sts-1 data-stream. 0 ? does not configure the receive sts-1 poh processor block to automatically transmit the ais-p indicator (via the ?downstream? traffic, towards the corresponding transmit sonet poh processor block) whenever it declares the lop-p defect condition. 1 ? configures the receive sts-1 poh processor block to automatically transmit the ais-p indicator (via the ?downstream? traffic, towards the corresponding transmit sonet poh processor block) whenever (and for the duration that) it declares the lop-p defect condition. note: the user must also set bit 0 (transmit ais-p enable) to ?1? to configure the receive sts-1 poh processor block to automatically transmit the ais-p indicator, in response to this defect condition. 0 transmit ais-p (downstream) enable r/w automatic transmission of ais-p enable: this read/write bit-field serves two purposes. it permits the user to configure the receive sts-1 poh processor block to automatically transmit the path ais (ais-p) indicator, via the down-stream traffic (e.g., towa rds the corresponding transmit sonet poh processor blocks), upon declaration of either an uneq-p, plm-p, lop-p or los defect condition. it also permits the user to c onfigure the receive sts-1 poh processor block to automatically transmit a path (ais-p) indicator via the ?downstream? traffic (e.g., to wards the corresponding transmit sonet poh processor blocks) anytim e it declares the ais-p defect condition within the ?inc oming ? sts-1 data-stream. 0 ? configures the receive sts- 1 poh processor block to not automatically transmit the ais-p indicator (via the ?downstream? traffic, towards the corresponding transmit sonet poh processor block ) whenever it declares an y of the ?above-mentioned? defect
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 741 conditions. 1 ? configures the receive sts-1 poh processor block to automatically transmit the ais-p indicator (via the ?downstream? traffic, towards the corresponding transmit sonet poh processor block) whenever it declares any of the ?above-mentioned? defect condition. note: the user must also set the corresponding bit-fields (within this register) to ?1? in order to configure the receive sts-1 poh processor block to automa tically transmit the ais-p indicator upon detection of a given alarm/defect condition.
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 742 table 530: receive sts-1 path ? sonet receive au to alarm register ? byte 0 (address location= 0xn1c3, where n ranges in value from 0x05 to 0x07) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 unused transmit ais-p (via downstream sts-1s) upon lop-p transmit ais-p (via downstream sts-1s) upon plm-p unused transmit ais-p (via downstream sts-1s) upon uneq-p transmit ais-p (via downstream sts-1s) upon tim-p transmit ais-p (via downstream sts-1s) upon ais-p unused r/w r/w r/w r/o r/w r/w r/w r/o 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 unused r/w 6 transmit ais-p (via downstream sts-1s) upon lop-p r/o transmit ais-p (via downstream sts-1s) upon declaration of the lop-p defect condition: this read/write bit-field permits the user to configure the transmit sonet poh processor block (within the corresponding channel) to automatically transmit the ais-p (path ais) indicator via the ?downstream? sts-1 signal (within the outbound sts-3 signal), anytime (and for the duration that) the receive sts-1 poh processor block declares the lop-p defect condition. 0 ? does not configure the corresponding transmit sonet poh processor block to automatically transmit the ais-p indicator via the ?downstream? sts-1 signal (within the outbound sts-3 signal), anytime the receive sts-1 poh pr ocessor block declares the lop-p defect condition. 1 ? configures the correspondi ng transmit sonet poh processor block to automatically transmit the ais-p indicator via the ?downstream? sts-1 signal (within the outbound sts-3 signal), anytime (and for the duration that) the receive sts-1 poh processor block declares the lop-p defect condition. 5 transmit ais-p (via downstream sts-1s) upon plm-p r/w transmit ais-p (via downstream sts-1s) upon declaration of the plm-p defect condition: this read/write bit-field permits the user to configure the transmit sonet poh processor block (within the corresponding channel) to automatically transmit the ais-p (path ais) indicator via the ?downstream? sts-1 signal, anytime (and for the duration that) the receive sts-1 poh processor block declares the plm-p defect condition. 0 ? does not configure the corresponding transmit sonet poh processor block to automatically transmit the ais-p indicator via the ?downstream? sts-1 signal (within the outbound sts-3 signal), anytime the receive sts-1 poh pr ocessor block declares the plm-p defect condition. 1 ? configures the correspondi ng transmit sonet poh processor block to automatically transmit the ais-p indicator via the ?downstream? sts-1 signal (within the outbound sts-3 signal), anytime (and for the duration that) the receive sts-1 poh processor block declares the plm-p defect condition. 4 unused r/o 3 transmit ais-p (via r/w transmit ais-p (via downstream sts-1s) upon declaration of the
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 743 downstream sts-1s) upon uneq-p uneq-p defect condition: this read/write bit-field permits the user to configure the transmit sonet poh processor block (within the corresponding channel) to automatically transmit the ais-p (path ais) indicator via the ?downstream? sts-1 signal, (w ithin the outbound sts-3 signal) anytime (and for the duration that) the receive sts-1 poh processor block declares the uneq-p defect condition. 0 ? does not configure the corresponding transmit sonet poh processor block to automatically transmit the ais-p indicator via the ?downstream? sts-1 signal (within the outbound sts-3 signal), anytime the receive sts-1 poh pr ocessor block declares the uneq- p defect condition. 1 ? configures the correspondi ng transmit sonet poh processor block to automatically transmit the ais-p indicator via the ?downstream? sts-1 signal (within the outbound sts-3 signal), anytime (and for the duration that) the receive sts-1 poh processor block declares the uneq-p defect condition. 2 transmit ais-p (via downstream sts-1s) upon tim-p r/w transmit ais-p (via downstream sts-1s) upon declaration of the tim-p defect condition: this read/write bit-field permits the user to configure the transmit sonet poh processor block (within the corresponding channel) to automatically transmit the ais-p (path ais) indicator via the ?downstream? sts-1 signal (within the outbound sts-3 signal), anytime (and for the duration that) the receive sts-1 poh processor block declares the tim-p defect condition. 0 ? does not configure the corresponding transmit sonet poh processor block to automatically transmit the ais-p indicator via the ?downstream? sts-1 signal (within the outbound sts-3 signal), anytime the receive sts-1 poh processor block declares the tim-p defect condition. 1 ? configures the correspondi ng transmit sonet poh processor block to automatically transmit the ais-p indicator via the ?downstream? sts-1 signal (within the outbound sts-3 signal), anytime (and for the duration that) the receive sts-1 poh processor block declares the tim-p defect condition. 1 transmit ais-p (via downstream sts-1s) upon ais-p r/w transmit ais-p (via downstream sts-1s) upon declaration of the ais-p defect condition: this read/write bit-field permits the user to configure the transmit sonet poh processor block (within the corresponding channel) to automatically transmit the ais-p (path ais) indicator via the ?downstream? sts-1 signal (within the outbound sts-3 signal), anytime (and for the duration that) the receive sts-1 poh processor block declares the ais-p defect condition. 0 ? does not configure the corresponding transmit sonet poh processor block to automatically transmit the ais-p indicator via the ?downstream? sts-1 signal (within the outbound sts-3 signal), anytime the receive sts-1 poh proc essor block declares the ais-p defect condition. 1 ? configures the correspondi ng transmit sonet poh processor block to automatically transmit the ais-p indicator via the ?downstream? sts-1 signal a(within the outbound sts-3 signal), anytime (and for the duration that) the receive sts-1 poh processor block declares the ais-p defect condition. 0 unused r/o
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 744 table 531: receive sts-1 path ? receive j1 byte capture register (address location= 0xn1d3, where n ranges in value from 0x05 to 0x07) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 j1_byte_captur ed_value[7:0] r/o r/o r/o r/o r/o r/o r/o r/o 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 ? 0 j1_byte_captured_value[7:0] r/o j1 byte captured value[7:0] these read-only bit-fields contain the value of the j1 byte, within the most recently received sts-1 frame. this particular value is stored in this register for one sts-1 frame period. during the next sts-1 frame period, this value will be overridden with a new j1 byte value. table 532: receive sts-1 path ? receive b3 byte capture register (address location= 0xn1d7, where n ranges in value from 0x05 to 0x07) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 b3_byte_captur ed_value[7:0] r/o r/o r/o r/o r/o r/o r/o r/o 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 ? 0 b3_byte_captured_value[7:0] r/o b3 byte captured value[7:0] these read-only bit-fields contain the value of the b3 byte, within the most recently received sts-1 frame. this particular value is stored in this register for one sts-1 frame period. during the next sts-1 frame period, this value will be overridden with a new b3 byte value.
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 745 table 533: receive sts-1 path ? receive c2 byte capture register (address location= 0xn1db, where n ranges in value from 0x05 to 0x07) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 c2_byte_captured_value[7:0] r/o r/o r/o r/o r/o r/o r/o r/o 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 ? 0 c2_byte_captured_value[7:0] r/o c2 byte captured value[7:0] these read-only bit-fields contain the value of the c2 byte, within the most recently received sts-1 frame. this particular value is stored in this register for one sts-1 frame period. during the next sts-1 frame period, this value will be overridden with a new c2 byte value. table 534: receive sts-1 path ? receive g1 byte capture register (address location= 0xn1df, where n ranges in value from 0x05 to 0x07) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 g1_byte_captured_value[7:0] r/o r/o r/o r/o r/o r/o r/o r/o 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 ? 0 g1_byte_captured_value[7:0] r/o g1 byte captured value[7:0] these read-only bit-fields cont ain the value of the g1 byte, within the most recently received sts-1 frame. this particular value is stored in this register for one sts-1 frame period. during the next sts-1 frame period, this value will be overridden with a new g1 byte value.
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 746 table 535: receive sts-1 path ? receive f2 byte capture register (address location=0xn1e3, where n ranges in value from 0x05 to 0x07) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 f2_byte_captured_value[7:0] r/o r/o r/o r/o r/o r/o r/o r/o 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 ? 0 f2_byte_captured_value[7:0] r/o f2 byte captured value[7:0] these read-only bit-fields contain the value of the f2 byte, within the most recently received sts-1 frame. this particular value is stored in this register for one sts-1 frame period. during the next sts-1 frame period, this value will be overridden with a new f2 byte value. table 536: receive sts-1 path ? receive h4 byte capture register (address location= 0xn1e7, where n ranges in value from 0x05 to 0x07) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 h4_byte_captured_value[7:0] r/o r/o r/o r/o r/o r/o r/o r/o 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 ? 0 h4_byte_captured_value[7:0] r/o h4 byte captured value[7:0] these read-only bit-fields contain the value of the h4 byte, within the most recently received sts-1 frame. this particular value is stored in this register for one sts-1 frame period. during the next sts-1 frame period, this value will be overridden with a new h4 byte value.
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 747 table 537: receive sts-1 path ? receive z3 byte capture register (address location= 0xn1eb, where n ranges in value from 0x05 to 0x07) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 z3_byte_captured_value[7:0] r/o r/o r/o r/o r/o r/o r/o r/o 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 ? 0 z3_byte_captured_value[7:0] r/o z3 byte captured value[7:0] these read-only bit-fields cont ain the value of the z3 byte, within the most recently received sts-1 frame. this particular value is stored in this register for one sts-1 frame period. during the next sts-1 frame period, this value will be overridden with a new z3 byte value. table 538: receive sts-1 path ? receive z4 (k3) byte capture register (address location= 0xn1ef, where n ranges in value from 0x05 to 0x07) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 z4(k3)_byte_capt ured_value[7:0] r/o r/o r/o r/o r/o r/o r/o r/o 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 ? 0 z4(k3)_byte_capt ured_value[7:0] r/o z4 (k3) byte captured value[7:0] these read-only bit-fields contain the value of the z4 (k3) byte, within the most recently received sts-1 frame. this particular value is stored in this register for one sts-1 frame period. during the next sts-1 frame period, this value will be overridden with a new z4 (k3) byte value.
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 748 table 539: receive sts-1 path ? receive z5 byte capture register (address location= 0xn1f3, where n ranges in value from 0x05 to 0x07) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 z5_byte_captured_value[7:0] r/o r/o r/o r/o r/o r/o r/o r/o 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 ? 0 z5_byte_captured_value[7:0] r/o z5 byte captured value[7:0] these read-only bit-fields cont ain the value of the z5 byte, within the most recently received sts-1 frame. this particular value is stored in this register for one sts-1 frame period. during the next sts-1 frame period, this value will be overridden with a new z5 byte value.
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 749 1.14 transmit sts-1 to h and poh processor block the register map for the transmit sts-1 toh and poh pr ocessor blocks are presented in the table below. additionally, a detailed description of each of the ?transmit sts-1 toh and poh processor? block registers is presented below. in order to provide some orientation for the reader, an illustration of the functional block diagram for the XRT94L33, with the ?transmit sts-3 toh processor block ?highlighted? is presented below in figure 4 figure 11: illustration of the functional block diagra m of the XRT94L33, with the transmit sts-1 toh and poh processor blocks ?high-lighted?. ds3/e3 framer block ds3/e3 framer block rx sts-1 pointer justification block rx sts-1 pointer justification block rx sts-1 poh block rx sts-1 poh block tx sts-1 poh block tx sts-1 poh block tx sts-1 pointer justification block tx sts-1 pointer justification block tx sts-1 toh block tx sts-1 toh block rx sts-1 toh block rx sts-1 toh block ds3/e3 jitter attenuator block ds3/e3 jitter attenuator block ds3/e3 mapper block ds3/e3 mapper block tx sonet poh processor block tx sonet poh processor block tx sts-3 toh processor block tx sts-3 toh processor block sts-3 telecom bus block sts-3 telecom bus block tx/rx line i/f block (primary) tx/rx line i/f block (primary) tx/rx line i/f block (aps) tx/rx line i/f block (aps) clock synthesizer block clock synthesizer block channel 1 to channels 2 ? 3 microprocessor interface microprocessor interface jtag test port jtag test port rx sonet poh processor block rx sonet poh processor block rx sts-3 toh processor block rx sts-3 toh processor block from channels 2 ? 3 rx sts-3 toh processor block (primary) rx sts-3 toh processor block (primary)
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 750 transmit sts-1 toh and poh processor block register table 540: transmit sts-1 toh and poh processor block registers ? address map a ddress l ocation r egister n ame d efault v alues 0xn800 ? 0xn901 reserved 0x00 0xn902 transmit sts-1 transport ? sonet transmit control register ? byte 1 0x00 0xn903 transmit sts-1 transport ? sonet transmit control register ? byte 0 0x00 0xn904 ? 0xn915 reserved 0x00 0xn916 reserved 0x00 0xn917 transmit sts-1 transport ? transmit a1 byte error mask ? low register ? byte 0 0x00 0xn918 ? 0xn91e reserved 0x00 0xn91f transmit sts-1 transport ? transmit a2 byte error mask ? low register ? byte 0 0x00 0xn920 ? 0xn921 reserved 0x00 0xn923 transmit sts-1 transport ? b1 byte error mask register 0x00 0xn924 ? 0xn926 reserved 0x00 0xn927 transmit sts-1 transport ? transmit b2 byte error mask register ? byte 0 0x00 0xn928 ? 0xn92a reserved 0x00 0xn92b transmit sts-1 transport ? transmit b2 byte - bit error mask register ? byte 0 0x00 0xn92c ? 0xn92d reserved 0x00 0xn92e transmit sts-1 transport ? k1k2 byte (aps) value register ? byte 1 0x00 0xn92f transmit sts-1 transport ? k1k2 byte (aps) value register ? byte 0 0x00 0xn930 ? 0xn931 reserved 0x00 0xn933 transmit sts-1 transport ? rdi-l control register 0x00 0xn934 ? 0xn936 reserved 0x00 0xn937 transmit sts-1 transport ? m1 byte value register 0x00 0xn938 ? 0xn93a reserved 0x00 0xn93b transmit sts-1 transport ? s1 byte value register 0x00 0xn93c ? 0xn93e reserved 0x00 0xn93f transmit sts-1 transport ? f1 byte value register 0x00 0xn940 ? 0xn942 reserved 0x00 0xn943 transmit sts-1 transport ? e1 byte value register 0x00 0xn944 transmit sts-1 transport ? e2 byte control register 0x00 0xn945 reserved 0x00
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 751 a ddress l ocation r egister n ame d efault v alues 0xn946 transmit sts-1 transport ? e2 byte pointer register 0x00 0xn947 transmit sts-1 transport ? e2 byte value register 0x00 0xn948 ? 0xn94a reserved 0x00 0xn94b transmit sts-1 transport ? transmit j0 byte value register 0x00 0xn94c ? 0xn94e reserved 0x00 0xn94f transmit sts-1 transport ? transmit j0 byte control register 0x00 0xn950 ? 0xn952 reserved 0x00 0xn953 transmit sts-1 transport ? serial port control register 0x00 0xn954 ?0xn9ff reserved 0x00 0xn900 ? 0xn981 reserved 0x00 0xn982 transmit sts-1 path ? sonet control register ? byte 1 0x00 0xn983 transmit sts-1 path ? sonet control register ? byte 0 0x00 0xn984 ? 0xn992 reserved 0x00 0xn993 transmit sts-1 path ? transmit j1 byte value register 0x00 0xn994 ? 0xn996 reserved 0x00 0xn997 transmit sts-1 path ? b3 byte mask register 0x00 0xn998 ? 0xn99a reserved 0x00 0xn99b transmit sts-1 path ? transmit c2 byte value register 0x00 0xn99c ? 0xn99e reserved 0x00 0xn99f transmit sts-1 path ? transmit g1 byte value register 0x00 0xn9a0 ? 0xn9a2 reserved 0x00 0xn9a3 transmit sts-1 path ? transmit f2 byte value register 0x00 0xn9a4 ? 0xn9a6 reserved 0x00 0xn9a7 transmit sts-1 path ? transmit h4 byte value register 0x00 0xn9a8 ? 0xn9aa reserved 0x00 0xn9ab transmit sts-1 path ? transmit z3 byte value register 0x00 0xn9ac ? 0xn9ae reserved 0x00 0xn9af transmit sts-1 path ? transmit z4 byte value register 0x00 0xn9b0 ? 0xn9b2 reserved 0x00 0xn9b3 transmit sts-1 path ? transmit z5 byte value register 0x00 0xn9b4 ? 0xn9b6 reserved 0x00 0xn9b7 transmit sts-1 path ? transmit path control register ? byte 0 0x00
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 752 a ddress l ocation r egister n ame d efault v alues 0xn9b8 ? 0xn9ba reserved 0x00 0xn9bb transmit sts-1 path ? transmit j1 control register 0x00 0xn9bc ? 0xn9be reserved 0x00 0xn9bf transmit sts-1 path ? transmit arbitrary h1 byte pointer register 0x94 0xn9c0 ? 0xn9c2 reserved 0x00 0xn9c3 transmit sts-1 path ? transmit arbitrary h2 byte pointer register 0x00 0xn9c4 ? 0xn9c5 reserved 0x00 0xn9c6 transmit sts-1 path ? transmit po inter byte register ? byte 1 0x02 0xn9c7 transmit sts-1 path ? transmit po inter byte register ? byte 0 0x0a 0xn9c8 reserved 0x00 0xn9c9 transmit sts-1 path ? rdi-p control register ? byte 2 0x40 0xn9ca transmit sts-1 path ? rdi-p control register ? byte 1 0xc0 0xn9cb transmit sts-1 path ? rdi-p control register ? byte 0 0xa0 0xn9cc ? 0xn9ce reserved 0x00 0xn9cf transmit sts-1 path ? transmit path serial port control register 0x00 0xn9d0 ? 0xn9ff reserved 0x00
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 753 1.14.1 transmit sts-1 toh processo r block register description table 541: transmit sts-1 transport ? sonet transm it control register ? byte 1 (address location= 0xn902, where n ranges in value from 5 to 7) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 reserved sts-n overhead insert e2 byte insert method e1 byte insert method f1 byte insert method s1 byte insert method k1k2 byte insert method m1 byte insert method[1] r/o r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 unused r/o 6 sts-n overhead insert r/w sts-n overhead insert: this read/write bit-field permits the user to configure the txtoh input port to insert th e toh for all lower-tributary sts-1s within the outbound sts-3 signal. 0 ? disables this feature. in this mode, the txtoh input port will only accept the toh for the first sts-1 within the outbound sts-3 signal. 1 ? enables this feature. 5 e2 byte insert method r/w e2 byte insert method: this read/write bit-field permits the user to configure the transmit sts-1 toh processor block to use either the contents within the ?transmit sts-1 transport ? e2 byte value? register or the txtoh input port as the source for the e2 by te, within the outbound sts-3 data- stream, as described below. 0 ? configures the transmit sts-1 toh processor block to accept externally supplied data (via the ?txtoh serial input port) and to insert this data into the e2 byte positi on within each outbound sts-3 frame. 1 ? configures the transmit sts-1 toh processor block to insert the contents within the ?transmit sts-1 transport ? e2 byte value? register (address location = 0xn947) into the e2 byte-position, within each outbound sts-3 frame. this configur ation selection permits the user to have software control over the value of the e2 byte within the ?transmit output? sts-3 data-stream. 4 e1 byte insert method r/w e1 byte insert method: this read/write bit-field permits the user to configure the transmit sts-1 toh processor block to use either the contents within the ?transmit sts-1 transport ? e1 byte value? register or the txtoh input port as the source for the e1 byte, within the outbound sts-3 data- stream, as described below. 0 ? configures the transmit sts-1 toh processor block to accept externally supplied data (via the ?txtoh serial input port) and to insert this data into the e1 byte positi on within each outbound sts-3 frame. 1 ? configures the transmit sts-1 toh processor block to insert the contents within the ?transmit sts-1 transport ? e1 byte value? register (address location = 0xn943) into the e1 byte-position, within each outbound sts-3 frame. this configur ation selection permits the user to have software control over the value of the e1 byte within the ?transmit output? sts-3 data-stream.
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 754 3 f1 byte insert method r/w f1 byte insert method: this read/write bit-field permits the user to configure the transmit sts-1 toh processor block to use either the contents within the ?transmit sts-1 transport ? f1 byte value? register or the txtoh input port as the source for the f1 by te, within the outbound sts-3 data- stream, as described below. 0 ? configures the transmit sts-1 toh processor block to accept externally supplied data (via the ?txtoh? serial input port) and to insert this data into the f1 byte positi on within each outbound sts-3 frame. 1 ? configures the transmit sts-1 toh processor block to insert the contents within the ?transmit sts-1 transport ? f1 byte value? register (address location = 0xn93f) into the f1 byte-position, within each outbound sts-3 frame. this configur ation selection permits the user to have software control over the value of the f1 byte within the ?transmit output? sts-3 data-stream. 2 s1 byte insert method r/w s1 byte insert method: this read/write bit-field permits the user to configure the transmit sts-1 toh processor block to use either the contents within the ?transmit sts-1 transport ? s1 byte value? register or the txtoh input port as the source for the e1 byte, within the outbound sts-3 data- stream, as described below. 0 ? configures the transmit sts-1 toh processor block to accept externally supplied data (via the ?txtoh? serial input port) and to insert this data into the s1 byte position within each outbound sts-3 frame. 1 ? configures the transmit sts-1 toh processor block to insert the contents within the ?transmit sts-1 transport ? s1 byte value? register (address location = 0xn93b). this configuration selection permits the user to have software control over the value of the s1 byte within the ?transmit output? sts-3 data-stream. 1 k1k2 byte insert method r/w k1k2 byte insert method: this read/write bit-field permits the user to configure the transmit sts-1 toh processor block to use either the contents within the ?transmit sts-1 transport ? k1 byte value? and ?transmit sts-1 transport ? k2 byte value? register s or the ?txtoh input port as the source for the k1 and k2 bytes, wi thin the outbound sts-3 data-stream, as described below. 0 ? configures the transmit sts-1 toh processor block to accept externally supplied data (via the ?txtoh? serial input port) and to insert this data into the k1 and k2 byte positions within each outbound sts-3 frame. 1 ? configures the transmit sts-1 toh processor block to insert the contents within the ?transmit sts-1 tr ansport ? k1 byte value? register (address location = 0xn92e) and the ?transmit sts-1 transport ? k2 byte value? register (address location = 0xn92f) into the k1 and k2 byte-positions, within each outbound sts-3 frame. this configuration selection permits the user to have soft ware control over the value of the k1 and k2 bytes within the ?transmit output? sts-3 data-stream. 0 m1 byte insert method[1] r/w m1 byte insert method ? bit 1: this read/write bit-field, along with the ?m1 insert method[0]? bit-field (located in the ?transmit sts-1 tr ansport ? sonet control register ? byte 0?) permits the user to specify the source of the contents of the m1 byte, within the ?transmit? output sts-3 data stream. the relationship between these two bit-fields and the corresponding source of the m1 b y te ( within each outbound sts-3 frame ) is p resented
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 755 below. m1 byte insert method[1:0] source of m1 byte 0 0 functions as the rei-l indicator (based upon the number of b2 byte errors that have been detected by the receive sts-3 toh processor block) 0 1 the m1 byte value is obtained from the contents of the ?transmit sts-1 transport ? m1 byte value? regist er (address location = 0xn937). note: this configuration selection permits the user to exercise software control over the contents within the m1 byte, of each outbound sts-3 frame. 1 0 the m1 byte value is obtained from the ?txtoh? serial input port. 1 1 functions as the rei-l bit-field (based upon the number of b2 byte errors that have been detected by the receive sts-3 toh processor block).
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 756 table 542: transmit sts-1 transport ? sonet transm it control register ? byte 0 (address location= 0xn903; where n ranges in value from 5 to 7) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 m1 byte insert method[0] unused force transmission of rdi-l force transmission of ais-l force tranmission of los patttern scrambler enable b2 byte error insert a1a2 byte error insert r/w r/o r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 m1 byte insert method[0] r/w m1 byte insert method ? bit 0: this read/write bit-field, along with the ?m1 insert method[1]? bit- field (located in the ?transmit sts-1 transport ? sonet control register ? byte 1?) permits the us er to specify the source of the contents of the m1 byte, within the ?transmit? output sts-3 data stream. the relationship between these two bit-fields and the corresponding source of the m1 byte (within each outbound sts-3 frame) is presented below. m1 insert method[1:0] source of m1 byte 0 0 functions as the rei-l indicator (based upon the number of b2 byte errors that have been detected by the receive sts-3 toh processor block) 0 1 the m1 byte value is obtained from the contents of the ?transmit sts-1 transport ? m1 byte value? register (address location= 0xn937). note: this configuration selection permits the user to exercise software control over the contents within the m1 byte of each outbound sts-3 frame. 1 0 the m1 byte value is obtained from the ?txtoh? serial input port. 1 1 functions as the rei-l bit-field (based upon the number of b2 byte errors that have been detected by the receive sts-3 toh processor block. 6 unused r/o 5 force transmission of rdi-l r/w force transmission of rdi-l (line - remote defect indicator): this read/write bit-field permits the user to (by software control) force the transmit sts-1 toh processor block to generate and transmit the rdi-l indicator to the remote terminal equipment as described below. 0 ? does not configure the transmit sts-1 toh processor block to generate and transmit the rdi-l indicato r. in this setting, the transmit sts-1 toh processor block will only generate and transmit the rdi-l indicator whenever the receive sts-3 toh processor block is
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 757 declaring a defect condition. 1 ? configures the transmit sts-1 toh processor block to generate and transmit the rdi-l indicator to the remote terminal equipment. in this case, the sts-3 transmitter will force bits 6, 7 and 8 (of the k2 byte) to the value ?1, 1, 0?. note: this bit-field is ignored if the transmit sts-1 toh processor block is transmitting the line ais (ais-l) indicator or the los pattern. 4 force transmission of ais-l r/w force transmission of ais-l (line ais) indicator: this read/write bit-field permits the user to (by software control) force the transmit sts-1 toh processor block to generate and transmit the ais-l indicator to the remote terminal equipment, as described below. 0 ? does not configure the transmit sts-1 toh processor block to generate and transmit the ais-l indicato r. in this case, the transmit sts-1 toh processor block will continue to transmit normal traffic to the remote terminal equipment. 1 ? configures the transmit sts-1 toh processor block to generate and transmit the ais-l indicator to the remote terminal equipment. in this case, the transmit sts-1 toh processor block will force all bits (within the ?outbound? sts-3 frame) with the exception of the section overhead bytes to an ?all ones? pattern. note: this bit-field is ignored if the transmit sts-1 toh processor block is transmitting the los pattern. 3 force transmission of los pattern r/w force transmission of los pattern: this read/write bit-field permits the user to (by software control) force the transmit sts-1 toh proc essor block to transmit the los (loss of signal) pattern to the remo te terminal equipment, as described below. 0 ? does not configure the transmit sts-1 toh processor block to generate and transmit the los pattern. in this case, the transmit sts- 1 toh processor block will continue to transmit ?normal? traffic to the remote terminal equipment. 1 ? configures the transmit sts-1 toh processor block to transmit the los pattern to the remote terminal equipment. in this case, the transmit sts-1 toh processor block will force all bytes (within the ?outbound? sonet frame) to an ?all zeros? pattern. 2 scrambler enable r/w scrambler enable: this read/write bit-field permits the user to either enable or disable the scrambler, within the transmit sts-1 toh processor block circuitry 0 ? disables the scrambler. 1 ? enables the scrambler. 1 b2 byte error insert r/w transmit b2 byte error insert enable: this read/write bit-field permits the user to configure the transmit sts-1 toh processor block to insert errors into the ?outbound? b2 bytes, per the contents within the ?transmit sts-1 transport ? transmit b2 byte error mask registers? as described below. 0 ? configures the transmit sts-1 toh processor block to not insert errors into the b2 bytes, within the outbound sts-3 signal. 1 ? configures the transmit sts-1 toh processor block to insert errors into the b2 b y tes (p er the contents within the ?transmit b2 b y te
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 758 error mask registers?). 0 a1a2 byte error insert r/w transmit a1a2 byte error insert enable: this read/write bit-field permits the user to configure the transmit sts-1 toh processor block to insert errors into the ?outbound? a1 and a2 bytes, per the contents within the ?transmit sts-1 transport ? transmit a1 byte error mask? and transmit a2 byte error mask? registers. 0 ? configures the transmit sts-1 toh processor block to not insert errors into the a1 and a2 bytes, within the outbound sts-3 data- stream. 1 ? configures the transmit sts-1 toh processor block to insert errors into the a1 and a2 bytes (per the contents within the ?transmit a1 byte error mask? and ?transmit a2 byte error mask? registers.
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 759 table 543: transmit sts-1 transport ? transmit a1 byte error mask ? low register ? byte 0 (address location= 0xn917; where n ranges in value from 5 to 7) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 unused a1 byte error in sts-1 # 2 a1 byte error in sts-1 # 1 a1 byte error in sts-1 # 0 r/o r/o r/o r/o r/o r/w r/w r/w 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7-3 unused r/o 2 a1 byte error in sts-1 # 2 r/w a1 byte error in sts-1 # 2, within outbound sts-3 signal: this read/write bit-field permits the user to configure the transmit sts-1 toh processor block to transmi t an erred a1 byte, within sts-1 # 2 within the outbound sts-3 signal, as described below. 0 ? configures the transmit sts-1 toh processor block to not transmit an erred a1 byte, within sts-1 channel 2. 1 ? configures the transmit sts-1 toh processor block to transmit an erred a1 byte, within sts-1 channel 2. in this configuration setting, the state of each bit (within this particular a1 byte) will be inverted. hence all 8-bits within this particular a1 byte will be erred. note: this bit-field is only valid if bit 0 (a1a2 byte error insert), within the ?transmit sts-1 transport ? sonet transmit control register ? byte 0 (address location= 0xn903) to ?1?. 1 a1 byte error in sts-1 # 1 r/w a1 byte error in sts-1 # 1, within outbound sts-3 signal: this read/write bit-field permits the user to configure the transmit sts-1 toh processor block to transmi t an erred a1 byte, within sts-1 # 1 within the outbound sts-3 signal, as described below. 0 ? configures the transmit sts-1 toh processor block to not transmit an erred a1 byte, within sts-1 channel 1. 1 ? configures the transmit sts-1 toh processor block to transmit an erred a1 byte, within sts-1 channel 1. in this configuration setting, the state of each bit (within this particular a1 byte) will be inverted. hence all 8-bits within this particular a1 byte will be erred. note: this bit-field is only valid if bit 0 (a1a2 byte error insert), within the ?transmit sts-1 transport ? sonet transmit control register ? byte 0 (address location= 0xn903) to ?1?. 0 a1 byte error in sts-1 # 0 r/w a1 byte error in sts-1 # 0, within outbound sts-3 signal: this read/write bit-field permits the user to configure the transmit sts-1 toh processor block to transmi t an erred a1 byte, within sts-1 # 0 within the outbound sts-3 signal, as described below. 0 ? configures the transmit sts-1 toh processor block to not transmit an erred a1 byte, within sts-1 channel 0. 1 ? configures the transmit sts-1 toh processor block to transmit an erred a1 byte, within sts-1 channel 0. in this configuration setting, the state of each bit (within this particular a1 byte) will be inverted. hence, all 8-bits within this particular a1 byte will be erred. note: this bit-field is only valid if bit 0 (a1a2 byte error insert), within the ?transmit sts-1 transport ? sonet transmit control register ? byte 0 (address location= 0xn903) to ?1?.
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 760
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 761 table 544: transmit sts-1 transport ? transmit a2 byte error mask ? low register ? byte 0 (address location= 0xn91f; where n ranges in value from 5 to 7) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 unused a2 byte error in sts-1 # 2 a2 byte error in sts-1 # 1 a2 byte error in sts-1 # 0 r/o r/o r/o r/o r/o r/w r/w r/w 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7-3 unused r/o 2 a2 byte error in sts-1 # 2 r/w a2 byte error in sts-1 # 2, within outbound sts-3 signal: this read/write bit-field permits the user to configure the transmit sts-1 toh processor block to transmit an erred a2 byte, within sts-1 # 2 within the outbound sts-3 signal, as described below. 0 ? configures the transmit sts-1 toh processor block to not transmit an erred a2 byte, within sts-1 channel 2. 1 ? configures the transmit sts-1 toh processor block to transmit an erred a2 byte, within sts-1 channel 2. in th is configuration settti ng, the state of bit (within this particular a2 byte) will be inverted. hence all 8-bits within this particular a2 byte will be erred. note: this bit-field is only valid if bit 0 (a1a2 byte error insert), within the ?transmit sts-1 transport ? sonet transmit control register ? byte 0 (address location= 0xn903) to ?1?. 1 a2 byte error in sts-1 # 1 r/w a2 byte error in sts-1 # 1, within outbound sts-3 signal: this read/write bit-field permits the user to configure the transmit sts-1 toh processor block to transmit an erred a2 byte, within sts-1 # 1 within the outbound sts-3 signal, as described below. 0 ? configures the transmit sts-1 toh processor block to not transmit an erred a2 byte, within sts-1 channel 1. 1 ? configures the transmit sts-1 toh processor block to transmit an erred a2 byte, within sts-1 channel 1. in this configuration se tting, the state of each bit (within this particular a2 byte) will be inverted. hence all 8-bits within this particular a2 byte will be erred. note: this bit-field is only valid if bit 0 (a1a2 byte error insert), within the ?transmit sts-1 transport ? sonet transmit control register ? byte 0 (address location= 0xn903) to ?1?. 0 a2 byte error in sts-1 # 0 r/w a2 byte error in sts-1 # 0, within the outbound sts-3 signal: this read/write bit-field permits the user to configure the transmit sts-1 toh processor block to transmit an erred a2 byte, within sts-1 # 0 within the outbound sts-3 signal, as described below. 0 ? configures the transmit sts-1 toh processor block to not transmit an erred a2 byte, within sts-1 channel 0. 1 ? configures the transmit sts-1 toh processor block to transmit an erred a2 byte, within sts-1 channel 0. in this configuration se tting, the state of each bit (within this particular a2 byte) will be inverted. hence, all 8-bits within this particular a2 byte will be erred. note: this bi t - field is onl y valid if bit 0 ( a1a2 b y te error insert ) , within the
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 762 ?transmit sts-1 transport ? sonet transmit control register ? byte 0 (address location= 0xn903) to ?1?.
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 763 table 545: transmit sts-1 transport ? b1 byte error mask register (address location= 0xn923; where n ranges in value from 5 to 7) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 b1_byte_error_mask[7:0] r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 ? 0 b1_byte_error_mask [7:0] r/w b1 byte error mask[7:0]: these read/write bit-fields permit the user to insert bit errors into the b1 bytes, within t he outbound sts-3 data stream. the transmit sts-1 toh processor block will perform an xor operation with the contents of t he b1 byte (within each outbound sts-3 frame), and the contents within this register. the results of this calculation will be inserted into the b1 byte position within the ?outbound? sts-3 dat a stream. for each bit-field (within this register) that is set to ?1?, the corresponding bit, within the b1 byte will be in error. note: for normal operation, the user should set this register to 0x00.
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 764 table 546: transmit sts-1 transport ? transmit b2 byte error mask register ? byte 0 (address location= 0xn927; where n ranges in value from 5 to 7) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 unused b2 byte error in sts-1 channel 0 r/o r/o r/o r/o r/o r/w r/w r/w 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7-1 unused r/o 0 b2 byte error in sts-1 channel # 0 r/w b2 byte error in sts-1 channel # 0: this read/write bit-field permits the user to configure the transmit sts-1 toh processor block to transmit an erred b2 byte, within sts-1 channel 0. if the user enables this feature, t hen the transmit sts-1 toh processor block will perform an xor operation of the contents of the b2 byte (within sts-1 channel 0) and the contents of the ?transmit sts-1 transport ? transmit b2 bit error mask register ? byte 0 (address location= 0xn92b). the results of th is calculation will be written back into the ?b2 byte? position, within sts-1 channel 0, prior to transmission to the remote terminal. 0 ? configures the transmit sts-1 toh processor block to not insert errors into the b2 byte, within sts-1 channel 0. 1 ? configures the transmit sts-1 toh processor block to insert errors into this particular b2 byte , within sts-1 channel 0. note: this bit-field is only valid if bit 1 (b2 byte error insert), within the ?transmit sts-1 transport ? sonet transmit control register ? byte 0 (address location= 0xn903) to ?1?.
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 765 table 547: transmit sts-1 transport ? transmit b2 bit error mask register ? byte 0 (address location= 0xn92b; where n ranges in value from 5 to 7) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 transmit_b2_error_mask[7:0] r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 ? 0 transmit_b2_error_mask[7:0] r/w transmit b2 error mask byte: these read/write bit-fields permit the user to specify exact which bits, within the ?selected? b2 byte (within the outbound sts-3 signal) will be erred. if the user configures the transmit sts-1 toh processor block to transmit one or more erred b2 bytes, then the transmit sts-1 toh processor block will perform an xor operation of the contents of the b2 byte (withi n the ?selected? sts-1 channel) and the contents of this register. the results of this calculation will be written back into the ?b2 byte? position within the ?selected? sts-1 channel, (within the outbound sts-3 signal) prior to transmission to the remote terminal. the user can select which sts-1 channels (within the outbound sts-3 signal) will contain the ?erred? b2 byte, by writing the appropriate data into the ?transmit sts-1 transport ? transmit b2 byte error mask register ? bytes 1 and 0 (address location= 0xn927). note: this bit-field is only valid if bit 1 (b2 error insert), within the ?transmit sts-1 transport ? sonet transmit control register ? byte 0 (address location= 0xn903) to ?1?.
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 766 table 548: transmit sts-1 transport ? k1k2 (aps) value register ? byte 1 (address location= 0xn92e; where n ranges in value from 5 to 7) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 transmit_k2_byte_value[7:0] r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 ? 0 transmit_k2_byte_value[7:0] r/w transmit k2 byte value: if the appropriate ?k1k2 insert me thod? is selected, then these read/write bit-fields will permit the user to specify the contents of the k2 byte, within the ?outbound? sts-3 signal. if bit 1 (k1k2 insert method) within the transmit sts-1 transport ? sonet transmit control register ? byte 1 (address location= 0xn902) is set to ?1?, then the transmit sts-1 toh processor block will load the contents of this register into the ?k2? byte-field, within each outbound sts-3 frame. note: these register bits are ignored if bit 1 (k1k2 insert method) is set to ?0?. table 549: transmit sts-1 transport ? k1k2 (aps) value register ? byte 0 (address location= 0xn92f; where n ranges in value from 5 to 7) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 transmit_k1_byte_value[7:0] r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 ? 0 transmit_k1_byte_value[7:0] r/w transmit k1 byte value: if the appropriate ?k1k2 insert me thod? is selected, then these read/write bit-fields will permit the user to specify the contents of the k1 byte, within the ?outbound? sts-3 signal. if bit 1 (k1k2 insert method) within the transmit sts-1 transport ? sonet transmit control register ? byte 1 (address location= 0xn902) is set to ?1?, then the transmit sts-1 toh processor block will load the content s of this register into the ?k1? byte-field, within each outbound sts-3 frame. note: these register bits are ignored if bit 1 (k1k2 insert method) is set to ?0?.
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 767 table 550: transmit sts-1 transport ? rdi-l control register (address location= 0xn933; where n ranges in value from 5 to 7) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 unused external rdi-l enable transmit rdi-l upon ais-l transmit rdi-l upon lof transmit rdi-l upon los r/o r/o r/o r/o r/w r/w r/w r/w 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 ? 4 unused r/o 3 external rdi-l enable r/w external rdi-l insertion enable: this read/write bit-field permits the user to configure the transmit sts-1 toh processor to accept data via the ?txtoh? input pin, when transmitting the rdi-l indicator to the remote terminal equipment. 0 ? configures the transmit sts-1 toh processor block to internally generate the rdi-l indicator based upon defect conditions that are being declared by the receive sts-3 toh processor block. 1 ? configure the transmit sts-1 toh processor block accept external data via the ?txtoh? input port and to load this value into bits 6, 7 and 8 (within the k2 byte) within each outbound sts-3 data-stream. 2 transmit rdi-l upon ais-l r/w transmit line remote defe ct indicator (rdi-l) upon declaration of the ais-l defect condition: this read/write bit-field permits the user to configure the transmit sts-1 toh processor block to automatically transmit the rdi-l indicator to the remote lte anytime (and for the duration) that the receive sts- 3 toh processor is declaring the line ais (ais-l) defect condition as described below. 0 ? configures the transmit sts-1 toh processor block to not automatically transmit the rdi-l indicator, whenever (and for the duration that) the receive st s-3 toh processor block is declares the ais-l defect condition. 1 ? configures the transmit sts-1 toh processor block to automatically transmit the rdi-l indicator, whenever (and for the duration that) the receive sts-3 toh processor block declares the ais-l defect condition. 1 transmit rdi-l upon lof r/w transmit line remote defe ct indicator (rdi-l) upon declaration of the lof defect condition: this read/write bit-field permits the user to configure the transmit sts-1 toh processor block to automatically transmit the rdi-l indicator to the remote lte anytime (and for the duration) that the receive sts-3 toh processor block is declaring the lof defect condition as described below. 0 ? configures the transmit sts-1 toh processor to not automatically transmit the rdi-l indicator, whenever the receive sts-3 toh processor block declares the lof defect condition. 1 ? confi g ures the transmit sts-1 toh processor block to
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 768 automatically transmit the rdi-l indicator, whenever (and for the duration that) the receive sts-3 toh processor block declares the lof defect condition. 0 transmit rdi-l upon los r/w transmit line remote defe ct indicator (rdi-l) upon declaration of the los defect condition: this read/write bit-field permits the user to configure the transmit sts-1 toh processor block to automatically transmit the rdi-l indicator to the remote lte anytime (and for the duration) that the receive sts-3 toh processor block declares the los defect condition. 0 ? configures the transmit sts-1 toh processor block to not automatically transmit the rdi-l indicator, whenever the receive sts-3 toh processor block declares the los defect condition. 1 ? configures the transmit sts-1 toh processor block to automatically transmit the rdi-l indicator, whenever (and for the duration that) the receive sts-3 toh processor block declares the los defect condition.
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 769 table 551: transmit sts-1 transport ? m1 byte value register (address location= 0xn937; where n ranges in value from 5 to 7) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 transmit_m1_byte_value[7:0] r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 ? 0 transmit_m1_byte_value [7:0] r/w transmit m1 byte value: if the appropriate ?m1 byte insert method? is selected, then these read/write bit-fields will permit the user to specify the contents of the m1 byte, within the ?outbound? sts-3 signal. if bit 0 (m1 byte insert method ? bit 1) within the transmit sts-1 transport ? sonet transmit control register ? byte 1 (address location= 0xn902) and bit 7 (m1 byte insert method ? bit 0) within the transmit sts-1 transport ? sonet transmit control register ? byte 0 (address location = 0xn903) is set to ?[0, 1]?, then the transmit sts-1 toh processor block will load the contents of this register into the ?m1? byte-field, within each outbound sts-3 frame. note: these register bits are ignored if the m1 byte insert method[1:0] bits are set to any value other than ?[0, 1]?. table 552: transmit sts-1 transport ? s1 byte value register (address location= 0xn93b; where n ranges in value from 5 to 7) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 transmit_s1_byte_value[7:0] r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 ? 0 transmit_s1_byte_value[7:0] r/w transmit s1 byte value: if the appropriate ?s1 insert me thod? is selected, then these read/write bit-fields will permit the user to specify the contents of the s1 byte, within the ?outbound? sts-3 signal. if bit 2 (s1 byte insert method) within the transmit sts-1 transport ? sonet transmit control register ? byte 1 (address location= 0xn902) is set to ?1?, then the transmit sts-1 toh processor block will load the content s of this register into the ?s1? byte-field, within each outbound sts-3 frame. note: these register bits are ignored if bit 2 (s1 byte insert method) is set to ?0?.
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 770 table 553: transmit sts-1 transport ? f1 byte value register (address location= 0xn93f; where n ranges in value from 5 to 7) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 transmit_f1_byte_value[7:0] r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 ? 0 transmit_f1_byte_value[7:0] r/w transmit f1 byte value : if the appropriate ?f1 byte insert method? is selected, then these read/write bit-fields will permit the user to specify the contents of the f1 byte, within the ?outbound? sts-3 signal. if bit 3 (f1 byte insert method) within the transmit sts-1 transport ? sonet transmit control register ? byte 1 (address location= 0xn902) is set to ?1?, then the transmit sts-1 toh processor block will load the contents of this register into the ?f1? byte-field, within each outbound sts-3 frame. note: these register bits are ignored if bit 3 (f1 byte insert method) is set to ?0?. table 554: transmit sts-1 transport ? e1 byte value register (address location= 0xn943; where n ranges in value from 5 to 7) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 transmit_e1_byte_value[7:0] r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 ? 0 transmit_e1_byte_value[7:0] r/w transmit e1 byte value: if the appropriate ?e1 byte insert method? is selected, then these read/write bit-fields will permit the user to specify the contents of the e1 byte, within the ?outbound? sts-3 signal. if bit 4 (e1 byte insert method) within the transmit sts-1 transport ? sonet transmit control register ? byte 1 (address location= 0xn902) is set to ?1?, then the transmit sts-1 toh processor block will load the contents of this register into the ?e1? byte-field, within each outbound sts-3 frame. note: these register bits are ignored if bit 4 (e1 byte insert method) is set to ?0?.
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 771 table 555: transmit sts-1 transport ? e2 byte control register (address location= 0xn944; where n ranges in value from 5 to 7) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 enable all sts-1s unused r/w r/o r/o r/o r/o r/o r/o r/o 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 enable all sts-1s r/w enable all sts-1s: this read/write bit-field permits the user to implement either of the following configurations options for soft ware control of the e2 byte value, within the outbound sts-3 signal. 0 ? configures the transmit sts-1 toh processor block to read out the contents of the ?transmit sts-1 transpor t ? e2 byte value? register and load that value into the e2 byte (w ithin sts-1 # 1) within the outbound sts-3 signal. 1 ? configures the transmit sts-1 toh processor block to read out the contents of the 3 ?shadow? registers, an d to load these values into the e2 byte positions, within each corresponding sts-1 signal; within the outbound sts-3 signal. note: this register bit is ignored if bit 5 (e2 byte insert method) within the ?transmit sts-1 transport ? sonet transmit control register ? byte 1? (address location= 0xn902) is set to ?0?. 6 - 0 unused r/o
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 772 table 556: transmit sts-1 transport ? e2 pointer register (address location= 0xn946; where n ranges in value from 5 to 7) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 unused e2_pointer[1:0] r/o r/o r/o r/o r/w r/w r/w r/w 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 ? 2 unused r/o 1 - 0 e2_pointer[1:0] r/w e2 pointer[3:0]: these read/write bit-fields permit the user to uniquely identify one of the 3 sts-1 e2 byte ?shadow? registers, when performing read or write operations to these registers. if the user has set bit 7 (enable all sts-1s), within this register to ?1?, then the contents of these four register bits, act as a pointer to a given ?shadow? register. once the user specifies this pointer value; then he/she completes the read or write operation (to or from the ?shadow? register) by performing a read or write to the ?transmit sts-1 transport ? e2 byte value? register (address location= 0xn947). valid ?shadow? pointer values range from ?0x00? to ?0x02? (where the pointer value of ?0x00? corresponds to the e2 ?shadow? register, corresponding to sts-1 # 1; and so on). note: this register bit is ignored if bit 7 (enable all sts-1s) is set to ?1?; or if bit 5 (e2 byte insert method) within the ?transmit sts- 1 transport ? sonet transmit control register ? byte 1? (address location= 0xn902) is set to ?0?.
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 773 table 557: transmit sts-1 transport ? e2 byte value register (address location=0xn947; where n ranges in value from 5 to 7) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 transmit_e2_byte_value[7:0] r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 ? 0 transmit_e2_byte_value[7:0] r/w transmit e2 byte value: the exact function of these register bits depends upon whether bit 7 (enable all sts-1s) within the ?transmit sts-1 transport ? e2 byte control? register (address location= 0xn944) has been set to ?0? or ?1?; as described below. if ?enable all sts-1s? is set to ?0? if the appropriate ?e2 insert me thod? is selected, then these read/write bit-fields will permit the user to specify the contents of the e2 byte, within the ?outbound? sts-3 signal. more specifically, this value will be loaded into the e2 byte position, within sts-1 # 1 (wit hin the outbound sts-3 signal). if bit 5 (e2 insert method) within the transmit sts-1 transport ? sonet transmit control register ? byte 1 (address location= 0xn902) is set to ?1?, then the transmit sts-1 toh processor block will load the contents of this register into the ?e2? byte-field, within each outbound sts-3 frame. if ?enable all sts-1s? is set to ?1? in this mode, these register bi t permit the user to have direct read/write access of the ?sts-1 e2 byte shadow? register; that is being pointed at by the ?e2 pointer[1:0]? value. these register bits are ignored if bit 5 (e2 byte insert method) is set to ?0?.
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 774 table 558: transmit sts-1 transport ? j0 byte value register (address location= 0xn94b; where n ranges in value from 5 to 7) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 transmit_j0_value[7:0] r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 ? 0 transmit_j0_value[7:0] r/w transmit j0 value byte: these read/write bits permit a user to specify the value of the j0 byte, that will be transmitted via the transport overhead, within the very next sts-3 frame. note: this register is only valid if the transmit sts-1 toh processor block is configur ed to read out the contents from this register and insert it into the j0 byte-field within each outbound sts-3 frame. the user accomplishes this by setting bits 1 and 0 (j0_type), within the transmit sts-1 transport ? j0 byte control register (address location= 0xn94f) to ?1, 0?.
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 775 table 559: transmit sts-1 transport ? transmit section trace message control register (address location= 0xn94f; where n ranges in value from 5 to 7) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 unused transmit section trace messsage l ength[1:0] transmit section trace message source[1:0] r/o r/o r/o r/o r/w r/w r/w r/w 0 0 0 0 1 1 0 0 b it n umber n ame t ype d escription 7 ? 4 unused r/o 3 ? 2 transmit section trace message length[1:0] r/w transmit section trace message length[1:0]: these two read/write bit-fields permit the user to specify the length of the section trace message that t he transmit sts-1 toh processor block will repeatedly transmit to the remote lte. the relationship between the contents of these bit-fields and the corresponding transmit section trace message length is presented below. transmit section trace message length[1:0] resulting section trace message length (in terms of bytes) 00 1 byte 01 16 bytes 10 or 11 64 bytes 1 ? 0 transmit section trace message source[1:0] r/w transmit section trace message source[1:0]: these two read/write bit-fields permit the user to specify the source of the ?outbound? section trace message that will be transported via the j0 byte channel within the out bound sts-3 data-stream, as depicted below. transmit section trace message source[1:0] resulting source of the section trace message. 00 fixed value: the transmit sts-1 toh processor block will automatically set the j0 byte, in each ?outbound? sts-3 frame to the value ?0x01?. 01 the ?transmit section trace message buffer?. the transmit sts-1 toh processor block will read out the contents within the transmit section trace message buffer, and will transmit this message to the remote lte. the ?transmit sts-1 toh processor block - transmit section trace message buffer? memory is located at address location 0x1b00 through 0x1b3f. 10 from the ?transmit j0 value[7:0]? register. in this settin g , the transmit sts-1 toh processor
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 776 block will read out the contents of the ?transmit j0 byte value[7:0]? register (address location= 0xn94b), and will insert this value into the j0 byte- position within each outbound sts-3 frame. 11 from the ?txtoh? input pin (pin f8). in this configuration setting, the transmit sts-1 toh processor block will externally accept the contents of the ?section trace message? via the ?txtoh input port? and it will transport this message (via the j0 byte-channel) to the remote lte.
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 777 table 560: transmit sts-1 transport ? serial port control register (address location= 0xn953; where n ranges in value from 5 to 7) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 unused txtoh_clock_speed[7:0] r/o r/o r/o r/o r/w r/w r/w r/w 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 - 4 unused r/o 3 - 0 txtoh_clock_speed[7:0] r/w txtohclk output clock signal speed: these read/write bit-fields permits the user to specify the frequency of the ?txtohclk output clock signal. the formula that relates the contents of these register bits to the ?txtohclk? frequency is presented below. freq = 19.44 /[2 * (txtoh_clock_speed + 1) note: for sts-3/stm-1 applications, the frequency of the txtohclk output signal mu st be in the range of 0.6075mhz to 9.72mhz
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 778 1.15 transmit sts-1 poh processor block registers table 561: transmit sts-1 path ? sonet control register ? byte 1 (address location= 0xn982; where n ranges in value from 5 to 7) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 unused z5 byte insertion type z4 byte insertion type z3 byte insertion type h4 byte insertion type r/w r/o r/o r/o r/w r/w r/w r/w 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 ? 4 unused r/o 3 z5 byte insertion type r/w z5 byte insertion type: this read/write bit-field permits the user to configure the transmit sts- 1 poh processor block to use either the contents within the ?transmit sts- 1 path ? transmit z5 byte value? register or the tpoh input pin as the source for the z5 byte, in the outbound sts-3c spe data-stream, as described below. 0 ? configures the transmit sts-1 poh processor block to insert the contents within the ?transmit sts-1 path ? transmit z5 byte value? register into the z5 byte position within ea ch outbound sts-3c spe. 1 ? configures the transmit sts-1 poh processor block to accept externally supplied data (via the ?tpoh? input port) and to insert this data into the z5 byte position within each outbound sts-3c spe. note: the address location of the transmit sts-1 poh processor block - transmit z5 byte value register is 0xn9b3 2 z4 byte insertion type r/w z4 byte insertion type: this read/write bit-field permits the user to configure the transmit sts- 1 poh processor block to use either the contents within the ?transmit sts- 1 path ? transmit z4 byte value? register or the txpoh input pin as the source for the z4 byte, in the outbound sts-3c spe data-stream, as described below. 0 ? configures the transmit sts-1 poh processor block to insert the contents within the ?transmit sts-1 path ? transmit z4 byte value? register into the z4 byte position within ea ch outbound sts-3c spe. 1 ? configures the transmit sts-1 poh processor block to accept externally supplied data (via the ?txpoh? input port) and to insert this data into the z4 byte position within each outbound sts-3c spe. note: the address location of the transmit sts-1 poh processor block - transmit z4 byte value register is 0xn9af 1 z3 byte insertion type r/w z3 byte insertion type: this read/write bit-field permits the user to configure the transmit sts- 1 poh processor block to use either the contents within the ?transmit sts- 1 path ? transmit z3 byte value? register or the txpoh input pin as the source for the z3 byte, in the outbound sts-3c spe data-stream, as described below. 0 ? configures the transmit sts-1 poh processor block to insert the contents within the ?transmit sts-1 path ? transmit z3 byte value? register into the z3 byte position within ea ch outbound sts-3c spe. 1 ? confi g ures the transmit sts-1 poh processor block to acce p t
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 779 externally supplied data (via the ?txpoh? input port) and to insert this data into the z3 byte position within each outbound sts-3c spe. note: the address location of the transmit sts-1 poh processor block - transmit z3 byte value register is 0xn9ab 0 h4 byte insertion type r/w h4 byte insertion type: this read/write bit-field permits the user to configure the transmit sts- 1 poh processor block to use either the contents within the ?transmit sts- 1 path ? transmit h4 byte value? register or the txpoh input pin as the source for the h4 byte, in the outbound sts-3c spe data-stream, as described below. 0 ? configures the transmit sts-1 poh processor block to insert the contents within the ?transmit sts-1 path ? transmit h4 byte value? register into the h4 byte positi on within each outbound sts-3c spe. 1 ? configures the transmit sts-1 poh processor block to accept externally supplied data (via the ?tpoh? input port) and to insert this data into the h4 byte position within each outbound sts-3c spe. note: the address location of the transmit sts-1 poh processor block -transmit h4 byte value register is 0xn9a7
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 780 table 562: transmit sts-1 path ? sonet control register ? byte 0 (address location= 0xn983; where n ranges in value from 5 to 7) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 f2 byte insertion type rei-p insertion type[1:0] rdi-p insertion type[1:0] c2 byte insertion type unused transmit ais- p enable r/w r/w r/w r/w r/w r/w r/o r/w 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 f2 byte insertion type r/w f2 byte insertion type: this read/write bit-field permits the user to configure the transmit sts-1 poh processor block to use either the contents within the ?transmit sts-1 path ? transmit f2 byte value? register or the txpoh input pin as the source for the f2 byte, in the outbound sts- 3c spe data-stream, as described below. 0 ? configures the transmit sts-1 poh pr ocessor block to insert the contents within the ?transmit sts-1 path ? transmit f2 byte value? register into the f2 byte position within each outbound sts-3c spe. 1 ? configures the transmit sts-1 poh pr ocessor block to accept externally supplied data (via the ?tpoh? input port) and to insert this data into the f2 byte position within each outbound sts-3c spe. note: the address location of the transmit sts-1 poh processor block - transmit f2 byte value register is 0xn9a3 6 - 5 rei-p insertion type[1:0] r/w rei-p insertion type[1:0]: these two read/write bit-fields permit the user to configure the transmit sts-1 poh processor block to use one of the three following sources for the rei-p bit-fields (e.g., bits 1 through 4, within the g1 byte) within each outbound sts-3c spe. ? from the corresponding receive sts-3c poh processor block (e.g., the transmit sts-1 poh processor block will set the rei-p bit-fields to the appropriate value, based upon the number of b3 byte errors that the receive sts-3c poh processor block detects and flags, within its incoming sts-3c spe data-stream). ? from the ?transmit g1 byte value? register. in this case, the transmit sts- 1 poh processor block will insert the contents of bits 7 through 4 within the ?transmit sts-1 poh processor block ? transmit g1 byte value? register into the rei-p bit-fields within each outbound sts-3c spe. ? from the ?tpoh? input pin. in th is case, the transmit sts-1 poh processor block will accept externally supplied data (v ia the ?tpoh? input port) and it will insert this data into the rei-p bit-fi elds within each outbound sts-3c spe. 00/11 ? configures the transmit sts-1 poh processor block to set bits 1 through 4 (in the g1 byte of the outbound spe) based upon the number of b3 byte errors that the receive sts-3c poh processor block detects and flags within the incoming sts-3c data-stream. 01 ? configures the transmit sts-1 poh processor block to set bits 1 through 4 (in the g1 byte of the outbound spe) based upon the contents within the ?transmit sts-1 poh processor block - transmit g1 byte value? register. 10 ? configures the transmit sts-1 poh processor block to accept externally supplied data (via the tpoh input port) and to insert this data into the rei-p bit- positions within each outbound sts-3c spe. note: the address location of the transmit sts - 1 poh processor block -
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 781 transmit g1 byte value register is 0xn99f 4 - 3 rdi-p insertion type[1:0] r/w rdi-p insertion type[1:0]: these two read/write bit-fields permit the user to configure the transmit sts-1 poh processor block to use one of the three following sources for the rdi-p bit-fields (e.g., bits 5 through 7, within the g1 byte) within each outbound sts-3c spe. ? from the corresponding receive sts-3c poh processor block (e g., the transmit sts-1 poh processor block will set the rdi-p bit-fields to the appropriate value, based upon which defect conditions are being declared by the receive sts-3c poh processor blo ck, within its incoming sts-3c spe data-stream). ? from the ?transmit g1 byte value? register. in this case, the transmit sts- 1 poh processor blolck will insert the c ontent of bits 2 through 0 within the ?transmit sts-1 poh processor block ? transmit g1 byte value? register into the rdi-p bit-fields within each outbound sts-3c spe. ? from the ?tpoh? input pin. in th is case, the transmit sts-1 poh processor block will accept externally supplied data (v ia the ?tpoh? input port) and it will insert this data into the rdi-p bit-fi elds within each outbound sts-3c spe. 00/11 ? configures the transmit sts-1 poh processor block to set bits 5 through 7 (in the g1 byte of the outbound spe) based upon the defects conditions that the receiv e sts-3c poh processor block is currently declaring within the incoming sts-3c data-stream. 01 ? configures the transmit sts-1 poh processor block to set bits 5 through 7 (in the g1 byte of the outbound spe) based upon the contents within the ?transmit sts-1 poh processor block - transmit g1 byte value? register. 10 ? configures the transmit sts-1 poh processor block to accept externally supplied data (via the tpoh input port) and to insert this data into the rdi-p bit- positions within each outbound sts-3c spe. note: the address location of the transmit sts-1 poh processor block - transmit g1 byte value register is 0xn99f 2 c2 byte insertion type r/w c2 byte insertion type: this read/write bit-field permits the user to configure the transmit sts-1 poh processor block to use either the contents within the ?transmit sts-1 path ? transmit c2 byte value? register or the tpoh input pin as the source for the c2 byte, in the outbound sts-3c spe data-stream, as described below. 0 ? configures the transmit sts-1 poh pr ocessor block to insert the contents within the ?transmit sts-1 path ? transmit c2 byte value? register into the c2 byte-position within each outbound sts-3c spe. 1 ? configures the transmit sts-1 poh pr ocessor block to accept externally supplied data (via the ?tpoh? input port) and to insert this data into the c2 byte position within each outbound sts-3c spe. note: the address location of the transmit sts-1 poh processor block - transmit c2 byte value register is 0xn99b 1 unused r/o 0 transmit ais-p enable r/w transmit ais-p enable: this read/write bit-field permits the user to configure the transmit sts-1 poh processor block to (via software co ntrol) transmit the ais-p indicator to the remote pte. if this feature is enabled, then the transmit sts-1 poh processor block will automatically set the h1, h2, h3 and all the ?outbound? sts-3c spe bytes to an ?all ones? p attern, p rior to routin g this data to the transmit sts-3 toh
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 782 processor block. 0 ? configures the transmit sts-1 poh processor block to not transmit the ais-p indicator to the remote pte. in this case, the transmit sts-1 poh processor block will transmit ?norma l? traffic to the remote pte. 1 ? configures the transmit sts-1 poh processor block to transmit the ais-p indicator to th e remote pte.
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 783 table 563: transmit sts-1 path ? transmitter j1 byte value register (address location= 0xn993; where n ranges in value from 5 to 7) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 transmit_j1_byte[7:0] r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 - 0 transmit j1 byte value[7:0] r/w transmit j1 byte value: these read/write bit-fields permit the user to have software control over the value of the j1 byte, within each outbound sts-3c spe. if the user configures the transmit sts-1 poh processor block to this register as the source of the j1 byte , then it will automatically write the contents of this register into the j1 byte location, within each ?outbound? sts-3c spe. this feature is enabled whenever the user writes the value ?[1, 0]? into bits 1 and 0 (insertion method) within the ?t ransmit sts-1 path ? sonet path j1 byte control register? register. note: the address location of the transmit sts-1 path ? sonet j1 byte control register is 0xn9bb table 564: transmit sts-1 path ? transmitter b3 byte error mask register (address location= 0xn997; where n ranges in value from 5 to 7) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 transmit_b3_byte_error_mask[7:0] r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 - 0 transmit b3 byte error_mask[7:0] r/w transmit b3 byte error mask[7:0]: this read/write bit-field permits the user to insert errors into the b3 byte within each ?outbound? sts-3c spe, prior to transmission to the transmit sts-3 toh processor block. the transmit sts-1 poh processor block will perform an xor operation with the contents of this register, and it s ?locally-computed? b3 byte value. the results of this operation will be written back into the b3 byte-position within each ?outbound? sts-3c spe. if the user sets a particular bit-field, within this register, to ?1?, then that corresponding bit, within the ?outbound? b3 byte will be in error. note: for normal operation, the user should set this register to 0x00.
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 784 table 565: transmit sts-1 path ? transmit c2 byte value register (address location= 0xn99b; where n ranges in value from 5 to 7) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 transmit_c2_byte_value[7:0] r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 - 0 transmit c2 byte value[7:0] r/w transmit c2 byte value: these read/write bit-fields permit the user to have software control over the value of the c2 byte, within each outbound sts-3c spe. if the user configures the transmit sts-1 poh processor block to this register as the source of the c2 byte , then it will automatically write the contents of this register into the c2 byte location, within each ?outbound? sts-3c spe. this feature is enabled whenever the user writes a ?0? into bit 2 (c2 insertion type) within the ?transmit sts-1 path ? sonet control register ? byte 0? register. note: the address location of the transmit sts-1 path ? sonet control register ? byte 0? register is 0xn983 table 566: transmit sts-1 path ? transmit g1 byte value register (address location= 0xn99f; where n ranges in value from 5 to 7) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 transmit_g1_byte_value[7:0] r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 - 0 transmit g1 byte value[7:0] r/w transmit g1 byte value: these read/write bit-fields permit the user to have software control over the contents of the rdi-p and rei-p bit-fields, within each g1 byte in the ?outbound? sts-3c spe. if the users sets ?rei-p_ins ertion_type[1:0]? and ?rdi- p_insertion_type[1:0]? bits to the val ue [0, 1], then contents of the rei-p and the rdi-p bit-fields (within each g1 byte of the ?outbound? sts-3c spe) will be dictated by the contents of this register. note: 1. the ?rei-p_insertion_type[1:0]? and ?rdi-p_insertion_type[1:0]? bit- fields are located in the ?transmit st s-1 path ? sonet control register ? byte 0? register. 2. the address location of the tr ansmit sts-1 path ? sonet control register ? byte 0? register is 0xn983
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 785 table 567: transmit sts-1 path ? transmit f2 byte value register (address location= 0xn9a3; where n ranges in value from 5 to 7) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 transmit_f2_byte_value[7:0] r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 - 0 transmit f2 byte value[7:0] r/w transmit f2 byte value: these read/write bit-fields permit the user to have software control over the value of the f2 byte, within each outbound sts-3c spe. if the user configures the transmit sts-1 poh processor block to this register as the source of the f2 byte , then it will automatically write the contents of this register into the f2 byte location, within each ?outbound? sts-3c spe. this feature is enabled whenever the user writes a ?0? into bit 7 (f2 insertion type) within the ?transmit sts-1 path ? sonet control register ? byte 0? register. note: the address location of the transmit sts-1 path ? sonet control register is 0xn983 table 568: transmit sts-1 path ? transmit h4 byte value register (address location= 0xn9a7; where n ranges in value from 5 to 7) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 transmit_h4_byte_value[7:0] r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 - 0 transmit h4 byte value[7:0] r/w transmit h4 byte value: these read/write bit-fields permit the user to have software control over the value of the h4 byte, within each outbound sts-3c spe. if the user configures the transmit sts-1 poh processor block to this register as the source of the h4 byte , then it will automatically write the contents of this register into the h4 byte location, within each ?outbound? sts-3c spe. this feature is enabled whenever the user writes a ?0? into bit 0 (h4 insertion type) within the ?transmit sts-1 path ? sonet control register ? byte 1? register. note: the address location for the ?transmit sts-1 path ? sonet control register ? byte 1? register is 0xn982
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 786 table 569: transmit sts-1 path ? transmit z3 byte value register (address location= 0xn9ab; where n ranges in value from 5 to 7) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 transmit_z3_byte_value[7:0] r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 - 0 transmit z3 byte value[7:0] r/w transmit z3 byte value: these read/write bit-fields permit the user to have software control over the value of the z3 byte, within each outbound sts-3c spe. if the user configures the transmit sts-1 poh processor block to this register as the source of the z3 byte , then it will automatically write the contents of this register into the z3 byte location, within each ?outbound? sts-3c spe. this feature is enabled whenever the user writes a ?0? into bit 1 (z3 insertion type) within the ?transmit sts-1 path ? sonet control register ? byte 1? register. note: the address location for the ?transmit sts-1 path ? sonet control register ? byte 1? register is 0xn982 table 570: transmit sts-1 path ? transmit z4 byte value register (address location= 0xn9af; where n ranges in value from 5 to 7) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 transmit_z4_byte_value[7:0] r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 - 0 transmit z4 byte value[7:0] r/w transmit z4 byte value: these read/write bit-fields permit the user to have software control over the value of the z4 byte, within each outbound sts-3c spe. if the user configures the transmit sts-1 poh processor block to this register as the source of the z4 byte , then it will automatically write the contents of this register into the z4 byte location, within each ?outbound? sts-3c spe. this feature is enabled whenever the user writes a ?0? into bit 2 (z4 insertion type) within the ?transmit sts-1 path ? sonet control register ? byte 0? register. note: the address location of the transmit sts-1 path ? sonet control register ? byte 0? register is 0xn982
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 787 table 571: transmit sts-1 path ? transmit z5 byte value register (address location= 0xn9b3; where n ranges in value from 5 to 7) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 transmit_z5_byte_value[7:0] r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 - 0 transmit z5 byte value[7:0] r/w transmit z5 byte value: these read/write bit-fields permit the user to have software control over the value of the z5 byte, within each outbound sts-3c spe. if the user configures the transmit sts-1 poh processor block to this register as the source of the z5 byte , then it will automatically write the contents of this register into the z5 byte location, within each ?outbound? sts-3c spe. this feature is enabled whenever the user writes a ?0? into bit 3 (z5 insertion type) within the ?transmit sts-1 path ? sonet control register ? byte 0? register. note: the address location of the transmit sts-1 path ? sonet control register ? byte 0? register is 0xn982
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 788 table 572: transmit sts-1 path ? transmit path control register (address location= 0xn9b7; where n ranges in value from 5 to 7) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 unused pointer force check stuff insert negative stuff insert positive stuff insert continuous ndf events insert single ndf event r/o r/o r/w r/w w w r/w r/w 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 - 6 unused r/o 5 pointer force r/w pointer force: this read/write bit-field permits the user to load the values contained within the ?transmit sts-1 poh arbitrary h1 pointer byte? and ?transmit sts-1 poh arbitrary h2 pointer byte? registers into the h1 and h2 bytes (within the outbound sts-3c data stream). note: the actual location of the spe will not be adjusted, per the value of h1 and h2 bytes. hence, this feature should cause the remote terminal to declare an ?invalid pointer? condition. 0 ? configures the transmit sts-1 poh and transmit sts-3 toh processor blocks to transmit sts-1/sts-3 data wi th normal and corre ct h1 and h2 bytes. 1 ? configures the transmit sts-1 poh and transmit sts-3 toh processor blocks to overwrite the values of the h1 and h2 bytes (i n the outbound sts- 3c/sts-3 data-stream) with the values in the ?transmit sts-1 poh arbitrary h1 and h2 pointer byte? registers. note: 1. the address location of the transmit sts-1 arbitrary h1 pointer byte register is 0xn9bf 2. the address location of the transmit sts-1 arbitrary h2 pointer byte register is 0xn9c3 4 check stuff r/w check stuff monitoring: this read/write bit-field permits the user to configure the transmit sts-1 poh and transmit sts-3 toh processor blocks to only execute a ?positive?, ?negative? or ?ndf? event (via the ?insert positive stuff?, ?insert negative stuff?, ?insert continuous or single ndf? options, via software command) if no pointer adjustment (ndf or otherwise ) has occurred during the last 3 sonet frame periods. 0 ? disables this feature. in this mode, the transmit sts-1 poh and transmit sts-3 toh processor blocks will execute a ?software-co mmanded? pointer adjustment event, independent of whether a pointer adjust ment event has occurred in the last 3 sonet frame periods. 1 ? enables this feature. in this mode, the transmit sts-1 poh and transmit sts-3 toh processor blocks will only execute a ?software- commanded? pointer adjustment event, if no pointer adjustment event has o ccurred during the last 3 sonet frame periods.
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 789 3 insert negative stuff r/w insert negative stuff: this read/write bit-field permits the user to configure the transmit sts-1 poh and transmit sts-3 toh processor blocks to insert a negative-stuff into the outbound sts-3c/sts-3 data stream. this command, in-turn will cause a ?pointer decrementing? event at the remote terminal. writing a ?0? to ?1? transition into this bit-field causes the following to happen. ? a negative-stuff will occur (e.g., a single payload byte will be inserted into the h3 byte position within the outbound sts-1/sts-3 data stream). ? the ?d? bits, within the h1 and h2 bytes will be inverted (to denote a ?decrementing? pointer adjustment event). ? the contents of the h1 and h2 bytes wi ll be decremented by ?1?, and will be used as the new pointer from this point on. note: once the user writes a ?1? into this bit-field, the XRT94L33 will automatically clear this bit-field. hence, there is no need to subsequently reset this bit-field to ?0?. 2 insert positive stuff r/w insert positive stuff: this read/write bit-field permits the user to configure the transmit sts-1 poh and transmit sts-3 toh processor bl ocks to insert a positive-stuff into the outbound sts-3c/sts-3 data stream. this command, in-turn will cause a ?pointer incrementing? event at the remote terminal. writing a ?0? to ?1? transition into this bit-field causes the following to happen. ? a positive-stuff will occur (e.g., a single stuff-byte will be inserted into the sts-3c/sts-3 data-stream, immediately a fter the h3 byte position within the outbound sts-3c/sts-3 data stream). ? the ?i? bits, within the h1 and h2 bytes will be inverted (to denote a ?incrementing? pointer adjustment event). ? the contents of the h1 and h2 bytes will be incremented by ?1?, and will be used as the new pointer from this point on. note: once the user writes a ?1? into this bit-field, the XRT94L33 will automatically clear this bit-field. hence, there is no need to subsequently reset this bit-field to ?0?. 1 insert continuous ndf events r/w insert continuous ndf events: this read/write bit-field permits the user configure the transmit sts-1 poh and transmit sts-3 toh processor bl ocks to continuously insert a new data flag (ndf) pointer adjustment into the outbound sts-3c/sts-3 data stream. note: as the transmit sts-1 poh and transmit sts-3 toh processor blocks insert the ndf event into the sts-1/sts-3 data stream, it will proceed to load in the content s of the ?transmit sts-1 poh arbitrary h1 pointer? and ?transmit sts-1 poh arbitrary h2 pointer? registers into the h1 and h2 bytes (within the outbound sts-3c/sts-3 data stream). 0 ? configures the ?transmit sts-1 toh and transmit sts-3 poh processor? blocks to not continuously insert ndf events in to the ?outbound? sts-3c/sts-3 data stream. 1- configures the ?transmit sts-1 toh and transmit sts-3 poh processor? blocks to continuously insert ndf even ts into the ?outbound? sts-3c/sts-3 data stream. 0 insert single ndf event r/w insert single ndf event: this read/write bit-field permits the user to configure the transmit sts-1 poh and transmit sts-3 toh processor blocks to insert a new data fla g
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 790 (ndf) pointer adjustment into the out bound sts-3c/sts-3 data stream. writing a ?0? to ?1? transition into this bit-field causes the following to happen. ? the ?n? bits, within the h1 byte will set to the value ?1001? ? the ten pointer-value bits (within the h1 and h2 bytes) will be set to new pointer value per the contents within the ?transmit sts-1 poh ? arbitrary h1 pointer? and ?transmit sts-1 poh arbitrary h2 pointer? registers (address location= 0xn9bf and 0xn9c3). ? afterwards, the ?n? bits will resume their normal value of ?0110?; and this new pointer value will be used as the new pointer from this point on. note: 1. once the user writes a ?1? into this bit-field, the XRT94L33 will automatically clear this bit-field. h ence, there is no need to subsequently reset this bit-field to ?0?. 2. the address location of the transmit sts-1 arbitrary h1 pointer byte register is 0xn9bf 3. the address location of the transmit sts-1 arbitrary h2 pointer byte register is 0xn9c3
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 791 table 573: transmit sts-1 path ? sonet path j1 byte control register (address location= 0xn9bb; where n ranges in value from 5 to 7) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 unused transmit path trace message_length[1:0] insertion_method[1:0] r/o r/o r/o r/o r/w r/w r/w r/w 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 ? 4 unused r/o 3 - 2 transmit path trace message_length[1:0] r/w transmit path message length[1:0]: these read/write bit-fields permit the user to specify the length of the j1 trace message, that the transmit sts-1 poh processor block will transmit. the relationship between the content of these bit-fields and the corresponding j1 trace message length is presented below. msg length resulting j1 trace message length 00 1 byte 01 16 bytes 10/11 64 bytes 1 - 0 insertion_method[1:0] r/w j1 insertion_method[1:0]: these read/write bit-fields permit the user to specify the method that he/she will use to insert the j1 byte into the outbound sts-3c spe. the relationship between the content s of these bit-fields and the corresponding j1 insertion method is presented below. j1 insertion method[1:0] resulting insertion method 00 insert the value ?0x00? 01 insert from the j1 trace buffer 10 insert from the ?transmit sts-1 path ? transmit j1 byte value register. 11 insert via the ?txpoh_n? input port
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 792 table 574: transmit sts-1 path ? transmit arbitrary h1 pointer register (address location= 0xn9bf; where n ranges in value from 5 to 7) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 ndf bits ss bits h1 pointer value r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 - 4 ndf bits r/w ndf (new data flag) bits: these read/write bit-fields permit the user provide the value that will be loaded into the ?ndf? bit-field (of the h1 byte), whenever a ?0 to 1? transition occurs in bit 5 (pointer force) within the ?transmit sts-1 path ? transmit path control? register. note: the address location of the transmit sts-1 path ? transmit path control register is 0xn9b7 3 - 2 ss bits r/w ss bits these read/write bit-fields permits the user to provide the value that will be loaded into the ?ss? bit-fi elds (of the h1 byte) whenever a ?0 to 1? transition occurs in bit 5 (pointer force) within the ?transmit sts-1 path ? transmit path control? register. note: 1. the ?ss? bits have no functional value, within the h1 byte. 2. the address location of the transmit sts-1 path ? transmit path control register is 0xn9b7 1 - 0 h1 pointer value[1:0] r/w h1 pointer value[1:0]: these two read/write bit-fields, along with the constants of the ?transmit sts-1 path ? transmit arbitrary h2 pointer? register (address location= 0xn9c3) permit the user to provide the contents of the pointer word. these two read/write bit-fields permit the user to define the value of the two most significant bits within the pointer word. whenever a ?0 to 1? transition occurs in bit 5 (pointer force) within the transmit sts-1 path ? transmit path co ntrol? register, the values of these two bits will be loaded into the two most significant bits within the pointer word. note: the address location of the transmit sts-1 path ? transmit path control register is 0xn9b7
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 793 table 575: transmit sts-1 path ? transmit arbitrar y h2 pointer register (address location= 0xn9c3; where n ranges in value from 5 to 7) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 h2 pointer value[7:0] r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 - 0 h2 pointer value[7:0] r/w h2 pointer value[1:0]: these eight read/write bit-fields, along with the constants of bits 1 and 0 within the ?transmit sts-1 path ? transmit arbitrary h1 pointer? register permit the user to provide the contents of the pointer word. these two read/write bit-fields permit the user to define the value of the eight least significant bits within the pointer word. whenever a ?0 to 1? transition occurs in bit 5 (pointer force) within the transmit sts-1 path ? transmit path co ntrol? register, the values of these eight bits will be loaded into the h2 byte, within the outbound sts-3c/sts-3 data stream. note: 1. the address location of the transmit sts-1 path ? transmit arbitrary h1 pointer? register is 0xn9c3 2. the address location of the transmit sts-1 path ? transmit path control register is 0xn9b7 table 576: transmit sts-1 path ? transmit current pointer byte register ? byte 1 (address location= 0xn9c6; where n ranges in value from 5 to 7) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 unused tx_pointer_high[1:0] r/o r/o r/o r/o r/o r/o r/o r/o 0 0 0 0 0 0 1 0 b it n umber n ame t ype d escription 7 ? 2 unused r/o 1 - 0 tx_pointer_hi gh[1:0] r/o transmit pointer word ? high[1:0]: these two read-only bits, along with the contents of the ?transmit sts-1 path ? transmit current pointer byte register ? byte 0? reflect the current value of the pointer (o r offset of spe within the sts-3c frame). these two bits contain the two most sign ificant bits within the ?10-bit pointer? word. note: the address location of the transmit sts-1 path ? transmit current pointer byte ? byte 0 register is 0xn9c7
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 794 table 577: transmit sts-1 path ? transmit current pointer byte register ? byte 0 (address location= 0xn9c7; where n ranges in value from 5 to 7) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 tx_pointer_low[7:0] r/o r/o r/o r/o r/o r/o r/o r/o 0 0 0 0 1 0 1 0 b it n umber n ame t ype d escription 7 ? 0 tx_pointer_lo w[7:0] r/o transmit pointer word ? low[7:0]: these two read-only bits, along with the contents of the ?transmit sts-1 path ? transmit current pointer byte register ? byte 1? reflect the current value of the pointer (o r offset of spe within the sts-3c frame). these two bits contain the eight least sign ificant bits within the ?10-bit pointer? word. note: the address location of the transmit sts-1 path ? transmit current pointer byte ? byte 0 register is 0xn9c6
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 795 table 578: transmit sts-1 path ? rdi-p control register ? byte 2 (address location= 0xn9c9; where n ranges in value from 5 to 7) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 unused plm-p rdi-p code[2:0] transmit rdi-p upon plm-p r/o r/o r/o r/o r/w r/w r/w r/w 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 ? 4 unused r/o 3 - 1 plm-p rdi-p code[2:0] r/w plm-p (path ? payload mismatch) defect ? rdi-p code: these three read/write bit-fields permit the user to specify the value that the transmit sts-1 poh processor block will transmit, within the rdi-p bit-fields of the g1 byte (within each ?outbound? sts-3c spe), whenever (and for t he duration that) the receive sts- 3c poh processor block detects and declares the plm-p defect condition. note: in order to enable this feat ure, the user must set bit 0 (transmit rdi-p upon plm-p) within this register to ?1?. 0 transmit rdi-p upon plm-p r/w transmit the rdi-p indicator upon declaration of the plm-p defect condition: this read/write bit-field permits the user to configure the transmit sts-1 poh processor block to aut omatically transmit the rdi-p code (as configured in bits 3 through 1 ? within this register) towards the remote pte whenever (and for the duration that) the receive sts-3c poh processor block declares the plm-p defect condition. 0 ? configures the transmit sts-1 poh processor block to not automatically transmit the rdi-p indicator whenever (and for the duration that) the receive sts-3c poh processor block declares the plm-p defect condition. 1 ? configures the transmit sts-1 poh processor block to automatically transmit the rdi-p indicator whenever (and for the duration that) the receive sts-3c poh processor block declares the plm-p defect condition. note: the transmit sts-1 poh processor block will transmit the rdi-p indicator (in response to the receive sts-3c poh processor block declaring the plm-p defect condition) by setting the rdi-p bit- fields (within each out bound sts-3c spe) to the contents within the ?plm-p rdi-p code[2:0]? bit-fi elds within this register.
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 796 table 579: transmit sts-1 path ? rdi-p control register ? byte 1 (address location= 0xn9ca; where n ranges in value from 5 to 7) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 tim-p rdi-p code[2:0] transmit rdi-p upon tim-p uneq-p rdi-p code[2:0] transmit rdi-p upon uneq-p r/w r/w r/w r/w r/w r/w r/w r/w 1 1 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 - 5 tim-p rdi-p code[2:0] r/w tim-p (path ? trace identification mismatch) defect ? rdi-p code: these three read/write bit-fields permit the user to specify the value that the transmit sts-1 poh processor block will transmit, within the rdi-p bit-fields of the g1 byte (within each ?outbound? sts-3c spe), whenever (and for t he duration that) the receive sts- 3c poh processor block detects and declares the tim-p defect condition. note: in order to enable this feat ure, the user must set bit 4 (transmit rdi-p upon tim-p) within this register to ?1?. 4 transmit rdi-p upon tim-p r/w transmit the rdi-p indicator upon declaration of the tim-p defect condition: this read/write bit-field permits the user to configure the transmit sts-1 poh processor block to aut omatically transmit the rdi-p code (as configured in bits 7 through 5 ? within this register) towards the remote pte whenever (and for the duration that) the receive sts-3c poh processor block decla res the tim-p defect condition. 0 ? configures the transmit sts-1 poh processor block to not automatically transmit the rdi-p indicator whenever (and for the duration that) the receive sts-3c poh processor block declares the tim-p defect condition. 1 ? configures the transmit sts-1 poh processor block to automatically transmit the rdi-p indicator whenever (and for the duration that) the receive sts-3c poh processor blolck declares the tim-p defect condition. note: the transmit sts-1 poh processor block will transmit the rdi-p indicator (in response to the receive sts-3c poh processor block declaring the tim-p defect condition) by setting the rdi-p bit- fields (within each out bound sts-3c spe) to the contents within the ?tim-p rdi-p code[2:0]? bit-fi elds within this register. 3 - 1 uneq-p rdi-p code[2:0] r/w uneq-p (path ? unequipped) defect ? rdi-p code: these three read/write bit-fields permit the user to specify the value that the transmit sts-1 poh processor block will transmit, within the rdi-p bit-fields of the g1 byte (within each ?outbound? sts-3c spe), whenever (and for t he duration that) the receive sts- 3c poh processor block detects and declares the uneq-p defect condition. note: in order to enable this feat ure, the user must set bit 0 (transmit rdi-p upon uneq-p) within this register to ?1?. 0 transmit rdi-p upon uneq-p r/w transmit the rdi-p indicator upon declaration of the uneq-p defect condition: this read/write bit-field p ermits the user to confi g ure the transmit
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 797 sts-1 poh processor block to aut omatically transmit the rdi-p code (as configured in bits 7 through 5 ? within this register) towards the remote pte whenever (and for the duration that) the receive sts-3c poh processor block declare s the uneq-p defect condition. 0 ? configures the transmit sts-1 poh processor block to not automatically transmit the rdi-p indicator whenever (and for the duration that) the receive sts-3c poh processor block declares the uneq-p defect condition. 1 ? configures the transmit sts-1 poh processor block to automatically transmit the rdi-p indicator whenever (and for the duration that) the receive sts-3c poh processor block declares the uneq-p defect condition. note: the transmit sts-1 poh processor block will transmit the rdi-p indicator (in response to the receive sts-3c poh processor block declaring the uneq-p defect co ndition) by setting the rdi-p bit-fields (within each outbound sts-3c spe) to the contents within the ?uneq-p rdi-p code[2:0]? bit- fields within this register.
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 798 table 580: transmit sts-1 path ? rdi-p control register ? byte 1 (address location= 0xn9cb; where n ranges in value from 5 to 7) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 lop-p rdi-p code[2:0] transmit rdi-p upon lop-p ais-p rdi-p code[2:0] transmit rdi- p upon ais-p r/w r/w r/w r/w r/w r/w r/w r/w 1 1 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 - 5 lop-p rdi-p code[2:0] r/w lop-p (path ? loss of pointer) defect ? rdi-p code: these three read/write bit-fields permit the user to specify the value that the transmit sts-1 poh processor block will transmit, within the rdi-p bit-fields of the g1 byte (within each ?outbound? sts-3c spe), whenever (and for t he duration that) the receive sts- 3c poh processor block detect s and declares the lop-p defect condition. note: in order to enable this feat ure, the user must set bit 4 (transmit rdi-p upon lop-p) within this register to ?1?. 4 transmit rdi-p upon lop-p r/w transmit the rdi-p indicator upon declaration of the lop-p defect condition: this read/write bit-field permits the user to configure the transmit sts-1 poh processor block to aut omatically transmit the rdi-p code (as configured in bits 7 through 5 ? within this register) towards the remote pte whenever (and for the duration that) the receive sts-3c poh processor block declares the lop-p defect condition. 0 ? configures the transmit sts-1 poh processor block to not automatically transmit the rdi-p indicator whenever (and for the duration that) the receive sts-3c poh processor block declares the lop-p defect condition. 1 ? configures the transmit sts-1 poh processor block to automatically transmit the rdi-p indicator whenever (and for the duration that) the receive sts-3c poh processor block declares the lop-p defect condition. note: the transmit sts-1 poh processor block will transmit the rdi-p indicator (in response to the receive sts-3c poh processor block declaring the lop-p defect condition) by setting the rdi-p bit- fields (within each out bound sts-3c spe) to the contents within the ?lop-p rdi-p code[2:0]? bit-fi elds within this register. 3 - 1 ais-p rdi-p code[2:0] r/w ais-p (path ? ais) defect ? rdi-p code: these three read/write bit-fields permit the user to specify the value that the transmit sts-1 poh processor block will transmit, within the rdi-p bit-fields of the g1 byte (within the ?outbound? sts- 3c spe), whenever (and for the duration that) the receive sts-3c poh processor block detects and declares the ais-p defect condition. note: in order to enable this feat ure, the user must set bit 0 (transmit rdi-p upon ais-p) within this register to ?1?. 0 transmit rdi-p upon ais-p r/w transmit the rdi-p indicator upon declaration of the ais-p defect condition: this read/write bit-field p ermits the user to confi g ure the transmit
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 799 sts-1 poh processor block to aut omatically transmit the rdi-p code (as configured in bits 7 through 5 ? within this register) towards the remote pte whenever (and for the duration that) the receive sts-3c poh processor block decla res the ais-p defect condition. 0 ? configures the transmit sts-1 poh processor block to not automatically transmit the rdi-p indicator whenever (and for the duration that) the receive sts-3c poh processor block declares the ais-p defect condition. 1 ? configures the transmit sts-1 poh processor block to automatically transmit the rdi-p indicator whenever (and for the duration that) the receive sts-3c poh processor block declares the ais-p defect condition. note: the transmit sts-1 poh processor block will transmit the rdi-p indicator (in response to the receive sts-3c poh processor block declaring the ais-p defect c ondition) by setting the rdi-p bit- field (within each outb ound sts-3c spe) to t he contents within the ?ais-p rdi-p code[2:0]? bit-fi elds within this register.
XRT94L33 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s rev 2 2 2 . . . 0 0 0 . . . 0 0 0 800 table 581: transmit sts-1 path ? serial port control register (address location= 0xn9cf; where n ranges in value from 5 to 7) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 unused txpoh clock speed [3:0] r/o r/o r/o r/o r/w r/w r/w r/w 0 0 0 0 0 0 0 0 b it n umber n ame t ype d escription 7 ? 4 unused r/o 3 ? 0 txpoh clock speed [3:0] r/w txpohclk output clock signal speed: these read/write bit-fields permit the user to specify the frequency of the ?txpohclk output clock signal. the formula that relates the contents of these re gister bits to the ?txpohclk? frequency is presented below. freq = 19.44/[2 * (txpoh_clock_speed + 1) note: for sts-3/stm-1 applications, the frequency of the rxpohclk output signal must be in the range of 0.304mhz to 9.72mhz
XRT94L33 rev 2 2 2 . . . 0 0 0 . . . 0 0 0 3 3 3 - - - c c c h h h a a a n n n n n n e e e l l l d d d s s s 3 3 3 / / / e e e 3 3 3 / / / s s s t t t s s s - - - 1 1 1 t t t o o o s s s t t t s s s - - - 3 3 3 / / / s s s t t t m m m - - - 1 1 1 m m m a a a p p p p p p e e e r r r ? ? ? s s s o o o n n n e e e t t t r r r e e e g g g i i i s s s t t t e e e r r r s s s 801 notes: rev. 2.0.0 - added bit descriptions for bits 7, 6, 5 & 4in register 0x011b. notice exar corporation reserves the right to make changes to th e products contained in this publication in order to improve design, performance or reli ability. exar corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. ch arts and schedules contained here in are only for illustration purposes and may vary depending upon a user?s specific application. while the information in this publication has been carefully checked; no responsi bility, however, is assumed for inaccuracies. exar corporation does not re commend the use of any of its products in life suppo rt applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. products are not autho rized for use in such applications unless exar corporation receives, in writ ing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; (c) potential liabilit y of exar corporation is adequately protected under the circumstances. copyright 2007 exar corporation datasheet march 2007 reproduction in part or whole, without prior wri tten consent of exar corporation is prohibited.

▲Up To Search▲

Price & Availability of XRT94L33

	To Download XRT94L33 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .